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dt-bindings: clock: renesas: Document RZ/G3E SoC CPG

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Document the device tree bindings for the Renesas RZ/G3E SoC
Clock Pulse Generator (CPG).

Also define constants for the core clocks of the RZ/G3E SoC.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
2024-12-03 10:49:31 +00:00
committed by Geert Uytterhoeven
parent 2bf1a3ca1d
commit 25458fdd39
2 changed files with 30 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
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@@ -4,19 +4,22 @@
$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
and control of clock signals for the IP modules, generation and control of resets,
and control over booting, low power consumption and power supply domains.
On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
generation and control of clock signals for the IP modules, generation and
control of resets, and control over booting, low power consumption and power
supply domains.
properties:
compatible:
const: renesas,r9a09g057-cpg
enum:
- renesas,r9a09g047-cpg # RZ/G3E
- renesas,r9a09g057-cpg # RZ/V2H
reg:
maxItems: 1
@@ -37,7 +40,7 @@ properties:
description: |
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
and a core clock reference, as defined in
<dt-bindings/clock/renesas,r9a09g057-cpg.h>,
<dt-bindings/clock/renesas,r9a09g0*-cpg.h>,
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
a module number. The module number is calculated as the CLKON register
offset index multiplied by 16, plus the actual bit in the register

21
include/dt-bindings/clock/renesas,r9a09g047-cpg.h Normal file
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@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* Core Clock list */
#define R9A09G047_SYS_0_PCLK 0
#define R9A09G047_CA55_0_CORECLK0 1
#define R9A09G047_CA55_0_CORECLK1 2
#define R9A09G047_CA55_0_CORECLK2 3
#define R9A09G047_CA55_0_CORECLK3 4
#define R9A09G047_CA55_0_PERIPHCLK 5
#define R9A09G047_CM33_CLK0 6
#define R9A09G047_CST_0_SWCLKTCK 7
#define R9A09G047_IOTOP_0_SHCLK 8
#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */