mirror of
https://github.com/Dasharo/linux.git
synced 2026-03-06 15:25:10 -08:00
Merge tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"This is the usual mix of updates for drivers that are used on (mostly
ARM) SoCs with no other top-level subsystem tree, including:
- The SCMI firmware subsystem gains support for version 3.2 of the
specification and updates to the notification code
- Feature updates for Tegra and Qualcomm platforms for added hardware
support
- A number of platforms get soc_device additions for identifying
newly added chips from Renesas, Qualcomm, Mediatek and Google
- Trivial improvements for firmware and memory drivers amongst
others, in particular 'const' annotations throughout multiple
subsystems"
* tag 'soc-drivers-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (96 commits)
tee: make tee_bus_type const
soc: qcom: aoss: add missing kerneldoc for qmp members
soc: qcom: geni-se: drop unused kerneldoc struct geni_wrapper param
soc: qcom: spm: fix building with CONFIG_REGULATOR=n
bus: ti-sysc: constify the struct device_type usage
memory: stm32-fmc2-ebi: keep power domain on
memory: stm32-fmc2-ebi: add MP25 RIF support
memory: stm32-fmc2-ebi: add MP25 support
memory: stm32-fmc2-ebi: check regmap_read return value
dt-bindings: memory-controller: st,stm32: add MP25 support
dt-bindings: bus: imx-weim: convert to YAML
watchdog: s3c2410_wdt: use exynos_get_pmu_regmap_by_phandle() for PMU regs
soc: samsung: exynos-pmu: Add regmap support for SoCs that protect PMU regs
MAINTAINERS: Update SCMI entry with HWMON driver
MAINTAINERS: samsung: gs101: match patches touching Google Tensor SoC
memory: tegra: Fix indentation
memory: tegra: Add BPMP and ICC info for DLA clients
memory: tegra: Correct DLA client names
dt-bindings: memory: renesas,rpc-if: Document R-Car V4M support
firmware: arm_scmi: Update the supported clock protocol version
...
This commit is contained in:
Linus Torvalds
@@ -1,58 +0,0 @@
|
||||
SPM AVS Wrapper 2 (SAW2)
|
||||
|
||||
The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
|
||||
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
|
||||
power-controller that transitions a piece of hardware (like a processor or
|
||||
subsystem) into and out of low power modes via a direct connection to
|
||||
the PMIC. It can also be wired up to interact with other processors in the
|
||||
system, notifying them when a low power state is entered or exited.
|
||||
|
||||
Multiple revisions of the SAW hardware are supported using these Device Nodes.
|
||||
SAW2 revisions differ in the register offset and configuration data. Also, the
|
||||
same revision of the SAW in different SoCs may have different configuration
|
||||
data due the differences in hardware capabilities. Hence the SoC name, the
|
||||
version of the SAW hardware in that SoC and the distinction between cpu (big
|
||||
or Little) or cache, may be needed to uniquely identify the SAW register
|
||||
configuration and initialization data. The compatible string is used to
|
||||
indicate this parameter.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Must have
|
||||
"qcom,saw2"
|
||||
A more specific value could be one of:
|
||||
"qcom,apq8064-saw2-v1.1-cpu"
|
||||
"qcom,msm8226-saw2-v2.1-cpu"
|
||||
"qcom,msm8974-saw2-v2.1-cpu"
|
||||
"qcom,apq8084-saw2-v2.1-cpu"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the first element specifies the base address and size of
|
||||
the register region. An optional second element specifies
|
||||
the base address and size of the alias register region.
|
||||
|
||||
- regulator:
|
||||
Usage: optional
|
||||
Value type: boolean
|
||||
Definition: Indicates that this SPM device acts as a regulator device
|
||||
device for the core (CPU or Cache) the SPM is attached
|
||||
to.
|
||||
|
||||
Example 1:
|
||||
|
||||
power-controller@2099000 {
|
||||
compatible = "qcom,saw2";
|
||||
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
|
||||
regulator;
|
||||
};
|
||||
|
||||
Example 2:
|
||||
saw0: power-controller@f9089000 {
|
||||
compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
|
||||
reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
|
||||
};
|
||||
@@ -1,117 +0,0 @@
|
||||
Device tree bindings for i.MX Wireless External Interface Module (WEIM)
|
||||
|
||||
The term "wireless" does not imply that the WEIM is literally an interface
|
||||
without wires. It simply means that this module was originally designed for
|
||||
wireless and mobile applications that use low-power technology.
|
||||
|
||||
The actual devices are instantiated from the child nodes of a WEIM node.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should contain one of the following:
|
||||
"fsl,imx1-weim"
|
||||
"fsl,imx27-weim"
|
||||
"fsl,imx51-weim"
|
||||
"fsl,imx50-weim"
|
||||
"fsl,imx6q-weim"
|
||||
- reg: A resource specifier for the register space
|
||||
(see the example below)
|
||||
- clocks: the clock, see the example below.
|
||||
- #address-cells: Must be set to 2 to allow memory address translation
|
||||
- #size-cells: Must be set to 1 to allow CS address passing
|
||||
- ranges: Must be set up to reflect the memory layout with four
|
||||
integer values for each chip-select line in use:
|
||||
|
||||
<cs-number> 0 <physical address of mapping> <size>
|
||||
|
||||
Optional properties:
|
||||
|
||||
- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
|
||||
devices, it should be the phandle to the system General
|
||||
Purpose Register controller that contains WEIM CS GPR
|
||||
register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
|
||||
should be set up as one of the following 4 possible
|
||||
values depending on the CS space configuration.
|
||||
|
||||
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
|
||||
---------------------------------------------
|
||||
05 128M 0M 0M 0M
|
||||
033 64M 64M 0M 0M
|
||||
0113 64M 32M 32M 0M
|
||||
01111 32M 32M 32M 32M
|
||||
|
||||
In case that the property is absent, the reset value or
|
||||
what bootloader sets up in IOMUXC_GPR1[11:0] will be
|
||||
used.
|
||||
|
||||
- fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
|
||||
devices, the presence of this property indicates that
|
||||
the weim bus should operate in Burst Clock Mode.
|
||||
|
||||
- fsl,continuous-burst-clk Make Burst Clock to output continuous clock.
|
||||
Without this option Burst Clock will output clock
|
||||
only when necessary. This takes effect only if
|
||||
"fsl,burst-clk-enable" is set.
|
||||
|
||||
Timing property for child nodes. It is mandatory, not optional.
|
||||
|
||||
- fsl,weim-cs-timing: The timing array, contains timing values for the
|
||||
child node. We get the CS indexes from the address
|
||||
ranges in the child node's "reg" property.
|
||||
The number of registers depends on the selected chip:
|
||||
For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
|
||||
registers: CSxU, CSxL.
|
||||
For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
|
||||
there are three registers: CSCRxU, CSCRxL, CSCRxA.
|
||||
For i.MX50, i.MX53 ("fsl,imx50-weim"),
|
||||
i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
|
||||
there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
|
||||
CSxRCR2, CSxWCR1, CSxWCR2.
|
||||
|
||||
Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
|
||||
|
||||
weim: weim@21b8000 {
|
||||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
clocks = <&clks 196>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x08000000>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
|
||||
0x0000c000 0x1404a38e 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
|
||||
|
||||
In this case, both chip select 0 and 1 will be configured with the same timing
|
||||
array values.
|
||||
|
||||
weim: weim@21b8000 {
|
||||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
clocks = <&clks 196>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x02000000
|
||||
1 0 0x0a000000 0x02000000
|
||||
2 0 0x0c000000 0x02000000
|
||||
3 0 0x0e000000 0x02000000>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
|
||||
acme@0 {
|
||||
compatible = "acme,whatever";
|
||||
reg = <0 0 0x100>, <0 0x400000 0x800>,
|
||||
<1 0x400000 0x800>;
|
||||
fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
|
||||
0x00000000 0xa0000240 0x00000000>;
|
||||
};
|
||||
};
|
||||
@@ -33,6 +33,7 @@ properties:
|
||||
- const: samsung,exynos7-hsi2c
|
||||
- items:
|
||||
- enum:
|
||||
- google,gs101-hsi2c
|
||||
- samsung,exynos850-hsi2c
|
||||
- const: samsung,exynosautov9-hsi2c
|
||||
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim-peripherals.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: i.MX WEIM Bus Peripheral Nodes
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
|
||||
description:
|
||||
This binding is meant for the child nodes of the WEIM node. The node
|
||||
represents any device connected to the WEIM bus. It may be a Flash chip,
|
||||
RAM chip or Ethernet controller, etc. These properties are meant for
|
||||
configuring the WEIM settings/timings and will accompany the bindings
|
||||
supported by the respective device.
|
||||
|
||||
properties:
|
||||
reg: true
|
||||
|
||||
fsl,weim-cs-timing:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
Timing values for the child node.
|
||||
minItems: 2
|
||||
maxItems: 6
|
||||
|
||||
# the WEIM child will have its own native properties
|
||||
additionalProperties: true
|
||||
@@ -0,0 +1,204 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,imx-weim.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: i.MX Wireless External Interface Module (WEIM)
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawnguo@kernel.org>
|
||||
- Sascha Hauer <s.hauer@pengutronix.de>
|
||||
|
||||
description:
|
||||
The term "wireless" does not imply that the WEIM is literally an interface
|
||||
without wires. It simply means that this module was originally designed for
|
||||
wireless and mobile applications that use low-power technology. The actual
|
||||
devices are instantiated from the child nodes of a WEIM node.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^memory-controller@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx1-weim
|
||||
- fsl,imx27-weim
|
||||
- fsl,imx50-weim
|
||||
- fsl,imx51-weim
|
||||
- fsl,imx6q-weim
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx31-weim
|
||||
- fsl,imx35-weim
|
||||
- const: fsl,imx27-weim
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx6sx-weim
|
||||
- fsl,imx6ul-weim
|
||||
- const: fsl,imx6q-weim
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
fsl,weim-cs-gpr:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Phandle to the system General Purpose Register controller that contains
|
||||
WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
|
||||
should be set up as one of the following 4 possible values depending on
|
||||
the CS space configuration.
|
||||
|
||||
IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
|
||||
---------------------------------------------
|
||||
05 128M 0M 0M 0M
|
||||
033 64M 64M 0M 0M
|
||||
0113 64M 32M 32M 0M
|
||||
01111 32M 32M 32M 32M
|
||||
|
||||
In case that the property is absent, the reset value or what bootloader
|
||||
sets up in IOMUXC_GPR1[11:0] will be used.
|
||||
|
||||
fsl,burst-clk-enable:
|
||||
type: boolean
|
||||
description:
|
||||
The presence of this property indicates that the weim bus should operate
|
||||
in Burst Clock Mode.
|
||||
|
||||
fsl,continuous-burst-clk:
|
||||
type: boolean
|
||||
description:
|
||||
Make Burst Clock to output continuous clock. Without this option Burst
|
||||
Clock will output clock only when necessary.
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-7],[0-9a-f]+$":
|
||||
type: object
|
||||
description: Devices attached to chip selects are represented as subnodes.
|
||||
$ref: fsl,imx-weim-peripherals.yaml
|
||||
additionalProperties: true
|
||||
required:
|
||||
- fsl,weim-cs-timing
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
not:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx50-weim
|
||||
- fsl,imx6q-weim
|
||||
then:
|
||||
properties:
|
||||
fsl,weim-cs-gpr: false
|
||||
fsl,burst-clk-enable: false
|
||||
- if:
|
||||
not:
|
||||
required:
|
||||
- fsl,burst-clk-enable
|
||||
then:
|
||||
properties:
|
||||
fsl,continuous-burst-clk: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: fsl,imx1-weim
|
||||
then:
|
||||
patternProperties:
|
||||
"^.*@[0-7],[0-9a-f]+$":
|
||||
properties:
|
||||
fsl,weim-cs-timing:
|
||||
items:
|
||||
items:
|
||||
- description: CSxU
|
||||
- description: CSxL
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx27-weim
|
||||
- fsl,imx31-weim
|
||||
- fsl,imx35-weim
|
||||
then:
|
||||
patternProperties:
|
||||
"^.*@[0-7],[0-9a-f]+$":
|
||||
properties:
|
||||
fsl,weim-cs-timing:
|
||||
items:
|
||||
items:
|
||||
- description: CSCRxU
|
||||
- description: CSCRxL
|
||||
- description: CSCRxA
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- fsl,imx50-weim
|
||||
- fsl,imx51-weim
|
||||
- fsl,imx6q-weim
|
||||
- fsl,imx6sx-weim
|
||||
- fsl,imx6ul-weim
|
||||
then:
|
||||
patternProperties:
|
||||
"^.*@[0-7],[0-9a-f]+$":
|
||||
properties:
|
||||
fsl,weim-cs-timing:
|
||||
items:
|
||||
items:
|
||||
- description: CSxGCR1
|
||||
- description: CSxGCR2
|
||||
- description: CSxRCR1
|
||||
- description: CSxRCR2
|
||||
- description: CSxWCR1
|
||||
- description: CSxWCR2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
memory-controller@21b8000 {
|
||||
compatible = "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
clocks = <&clks 196>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x08000000>;
|
||||
fsl,weim-cs-gpr = <&gpr>;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x02000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <2>;
|
||||
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
|
||||
0x0000c000 0x1404a38e 0x00000000>;
|
||||
};
|
||||
};
|
||||
@@ -37,5 +37,6 @@ allOf:
|
||||
- $ref: ingenic,nemc-peripherals.yaml#
|
||||
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
|
||||
- $ref: ti,gpmc-child.yaml#
|
||||
- $ref: fsl/fsl,imx-weim-peripherals.yaml
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@@ -145,7 +145,7 @@ patternProperties:
|
||||
"^emc-table@[0-9]+$":
|
||||
$ref: "#/$defs/emc-table"
|
||||
|
||||
"^emc-tables@[a-z0-9-]+$":
|
||||
"^emc-tables@[a-f0-9-]+$":
|
||||
type: object
|
||||
properties:
|
||||
reg:
|
||||
|
||||
@@ -45,6 +45,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r8a779g0-rpc-if # R-Car V4H
|
||||
- renesas,r8a779h0-rpc-if # R-Car V4M
|
||||
- const: renesas,rcar-gen4-rpc-if # a generic R-Car gen4 device
|
||||
|
||||
- items:
|
||||
|
||||
@@ -23,7 +23,9 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32mp1-fmc2-ebi
|
||||
enum:
|
||||
- st,stm32mp1-fmc2-ebi
|
||||
- st,stm32mp25-fmc2-ebi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -34,6 +36,9 @@ properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 2
|
||||
|
||||
|
||||
46
Documentation/devicetree/bindings/soc/qcom/qcom,pbs.yaml
Normal file
46
Documentation/devicetree/bindings/soc/qcom/qcom,pbs.yaml
Normal file
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/qcom/qcom,pbs.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. Programmable Boot Sequencer
|
||||
|
||||
maintainers:
|
||||
- Anjelique Melendez <quic_amelende@quicinc.com>
|
||||
|
||||
description: |
|
||||
The Qualcomm Technologies, Inc. Programmable Boot Sequencer (PBS)
|
||||
supports triggering power up and power down sequences for clients
|
||||
upon request.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,pmi632-pbs
|
||||
- const: qcom,pbs
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/spmi/spmi.h>
|
||||
|
||||
pmic@0 {
|
||||
reg = <0x0 SPMI_USID>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pbs@7400 {
|
||||
compatible = "qcom,pmi632-pbs", "qcom,pbs";
|
||||
reg = <0x7400>;
|
||||
};
|
||||
};
|
||||
@@ -32,6 +32,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sm8650-pmic-glink
|
||||
- qcom,x1e80100-pmic-glink
|
||||
- const: qcom,sm8550-pmic-glink
|
||||
- const: qcom,pmic-glink
|
||||
|
||||
@@ -65,6 +66,7 @@ allOf:
|
||||
enum:
|
||||
- qcom,sm8450-pmic-glink
|
||||
- qcom,sm8550-pmic-glink
|
||||
- qcom,x1e80100-pmic-glink
|
||||
then:
|
||||
properties:
|
||||
orientation-gpios: false
|
||||
|
||||
@@ -35,6 +35,8 @@ properties:
|
||||
description: Phandle to an RPM MSG RAM slice containing the master stats
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
items:
|
||||
maxItems: 1
|
||||
|
||||
qcom,master-names:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
|
||||
@@ -1,23 +1,33 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml#
|
||||
$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Subsystem Power Manager
|
||||
title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2)
|
||||
|
||||
maintainers:
|
||||
- Andy Gross <agross@kernel.org>
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Qualcomm Subsystem Power Manager, used to control
|
||||
the peripheral logic surrounding the application cores in Qualcomm platforms.
|
||||
The Qualcomm Subsystem Power Manager is used to control the peripheral logic
|
||||
surrounding the application cores in Qualcomm platforms.
|
||||
|
||||
The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the
|
||||
Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable
|
||||
power-controller that transitions a piece of hardware (like a processor or
|
||||
subsystem) into and out of low power modes via a direct connection to
|
||||
the PMIC. It can also be wired up to interact with other processors in the
|
||||
system, notifying them when a low power state is entered or exited.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,ipq4019-saw2-cpu
|
||||
- qcom,ipq4019-saw2-l2
|
||||
- qcom,ipq8064-saw2-cpu
|
||||
- qcom,sdm660-gold-saw2-v4.1-l2
|
||||
- qcom,sdm660-silver-saw2-v4.1-l2
|
||||
- qcom,msm8998-gold-saw2-v4.1-l2
|
||||
@@ -26,16 +36,27 @@ properties:
|
||||
- qcom,msm8916-saw2-v3.0-cpu
|
||||
- qcom,msm8939-saw2-v3.0-cpu
|
||||
- qcom,msm8226-saw2-v2.1-cpu
|
||||
- qcom,msm8226-saw2-v2.1-l2
|
||||
- qcom,msm8960-saw2-cpu
|
||||
- qcom,msm8974-saw2-v2.1-cpu
|
||||
- qcom,msm8974-saw2-v2.1-l2
|
||||
- qcom,msm8976-gold-saw2-v2.3-l2
|
||||
- qcom,msm8976-silver-saw2-v2.3-l2
|
||||
- qcom,apq8084-saw2-v2.1-cpu
|
||||
- qcom,apq8084-saw2-v2.1-l2
|
||||
- qcom,apq8064-saw2-v1.1-cpu
|
||||
- const: qcom,saw2
|
||||
|
||||
reg:
|
||||
description: Base address and size of the SPM register region
|
||||
maxItems: 1
|
||||
items:
|
||||
- description: Base address and size of the SPM register region
|
||||
- description: Base address and size of the alias register region
|
||||
minItems: 1
|
||||
|
||||
regulator:
|
||||
$ref: /schemas/regulator/regulator.yaml#
|
||||
description: Indicates that this SPM device acts as a regulator device
|
||||
device for the core (CPU or Cache) the SPM is attached to.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
@@ -82,4 +103,17 @@ examples:
|
||||
reg = <0x17912000 0x1000>;
|
||||
};
|
||||
|
||||
- |
|
||||
/*
|
||||
* Example 3: SAW2 with the bundled regulator definition.
|
||||
*/
|
||||
power-manager@2089000 {
|
||||
compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
|
||||
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
|
||||
|
||||
regulator {
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -72,6 +72,8 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-peric0-sysreg
|
||||
- google,gs101-peric1-sysreg
|
||||
- samsung,exynos850-cmgp-sysreg
|
||||
- samsung,exynos850-peri-sysreg
|
||||
- samsung,exynos850-sysreg
|
||||
|
||||
@@ -9091,6 +9091,7 @@ F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
|
||||
F: arch/arm64/boot/dts/exynos/google/
|
||||
F: drivers/clk/samsung/clk-gs101.c
|
||||
F: include/dt-bindings/clock/google,gs101.h
|
||||
K: [gG]oogle.?[tT]ensor
|
||||
|
||||
GPD POCKET FAN DRIVER
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
@@ -17369,7 +17370,6 @@ F: Documentation/devicetree/bindings/pinctrl/renesas,*
|
||||
F: drivers/pinctrl/renesas/
|
||||
|
||||
PIN CONTROLLER - SAMSUNG
|
||||
M: Tomasz Figa <tomasz.figa@gmail.com>
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
R: Alim Akhtar <alim.akhtar@samsung.com>
|
||||
@@ -19428,7 +19428,6 @@ F: drivers/media/platform/samsung/exynos4-is/
|
||||
SAMSUNG SOC CLOCK DRIVERS
|
||||
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
M: Tomasz Figa <tomasz.figa@gmail.com>
|
||||
M: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
R: Alim Akhtar <alim.akhtar@samsung.com>
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
@@ -21348,6 +21347,7 @@ F: drivers/clk/clk-sc[mp]i.c
|
||||
F: drivers/cpufreq/sc[mp]i-cpufreq.c
|
||||
F: drivers/firmware/arm_scmi/
|
||||
F: drivers/firmware/arm_scpi.c
|
||||
F: drivers/hwmon/scmi-hwmon.c
|
||||
F: drivers/pmdomain/arm/
|
||||
F: drivers/powercap/arm_scmi_powercap.c
|
||||
F: drivers/regulator/scmi-regulator.c
|
||||
|
||||
@@ -186,11 +186,12 @@ config SUNXI_RSB
|
||||
|
||||
config TEGRA_ACONNECT
|
||||
tristate "Tegra ACONNECT Bus Driver"
|
||||
depends on ARCH_TEGRA_210_SOC
|
||||
depends on ARCH_TEGRA
|
||||
depends on OF && PM
|
||||
help
|
||||
Driver for the Tegra ACONNECT bus which is used to interface with
|
||||
the devices inside the Audio Processing Engine (APE) for Tegra210.
|
||||
the devices inside the Audio Processing Engine (APE) for
|
||||
Tegra210 and later.
|
||||
|
||||
config TEGRA_GMI
|
||||
tristate "Tegra Generic Memory Interface bus driver"
|
||||
|
||||
@@ -128,7 +128,7 @@ struct sunxi_rsb {
|
||||
};
|
||||
|
||||
/* bus / slave device related functions */
|
||||
static struct bus_type sunxi_rsb_bus;
|
||||
static const struct bus_type sunxi_rsb_bus;
|
||||
|
||||
static int sunxi_rsb_device_match(struct device *dev, struct device_driver *drv)
|
||||
{
|
||||
@@ -177,7 +177,7 @@ static int sunxi_rsb_device_modalias(const struct device *dev, struct kobj_ueven
|
||||
return of_device_uevent_modalias(dev, env);
|
||||
}
|
||||
|
||||
static struct bus_type sunxi_rsb_bus = {
|
||||
static const struct bus_type sunxi_rsb_bus = {
|
||||
.name = RSB_CTRL_NAME,
|
||||
.match = sunxi_rsb_device_match,
|
||||
.probe = sunxi_rsb_device_probe,
|
||||
|
||||
@@ -2400,7 +2400,7 @@ static int sysc_child_add_clocks(struct sysc *ddata,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct device_type sysc_device_type = {
|
||||
static const struct device_type sysc_device_type = {
|
||||
};
|
||||
|
||||
static struct sysc *sysc_child_to_parent(struct device *dev)
|
||||
|
||||
@@ -105,7 +105,7 @@ static struct attribute *ffa_device_attributes_attrs[] = {
|
||||
};
|
||||
ATTRIBUTE_GROUPS(ffa_device_attributes);
|
||||
|
||||
struct bus_type ffa_bus_type = {
|
||||
const struct bus_type ffa_bus_type = {
|
||||
.name = "arm_ffa",
|
||||
.match = ffa_device_match,
|
||||
.probe = ffa_device_probe,
|
||||
|
||||
@@ -141,6 +141,17 @@ out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int scmi_protocol_table_register(const struct scmi_device_id *id_table)
|
||||
{
|
||||
int ret = 0;
|
||||
const struct scmi_device_id *entry;
|
||||
|
||||
for (entry = id_table; entry->name && ret == 0; entry++)
|
||||
ret = scmi_protocol_device_request(entry);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* scmi_protocol_device_unrequest - Helper to unrequest a device
|
||||
*
|
||||
@@ -186,6 +197,15 @@ static void scmi_protocol_device_unrequest(const struct scmi_device_id *id_table
|
||||
mutex_unlock(&scmi_requested_devices_mtx);
|
||||
}
|
||||
|
||||
static void
|
||||
scmi_protocol_table_unregister(const struct scmi_device_id *id_table)
|
||||
{
|
||||
const struct scmi_device_id *entry;
|
||||
|
||||
for (entry = id_table; entry->name; entry++)
|
||||
scmi_protocol_device_unrequest(entry);
|
||||
}
|
||||
|
||||
static const struct scmi_device_id *
|
||||
scmi_dev_match_id(struct scmi_device *scmi_dev, struct scmi_driver *scmi_drv)
|
||||
{
|
||||
@@ -263,7 +283,7 @@ static void scmi_dev_remove(struct device *dev)
|
||||
scmi_drv->remove(scmi_dev);
|
||||
}
|
||||
|
||||
struct bus_type scmi_bus_type = {
|
||||
const struct bus_type scmi_bus_type = {
|
||||
.name = "scmi_protocol",
|
||||
.match = scmi_dev_match,
|
||||
.probe = scmi_dev_probe,
|
||||
@@ -279,7 +299,7 @@ int scmi_driver_register(struct scmi_driver *driver, struct module *owner,
|
||||
if (!driver->probe)
|
||||
return -EINVAL;
|
||||
|
||||
retval = scmi_protocol_device_request(driver->id_table);
|
||||
retval = scmi_protocol_table_register(driver->id_table);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
@@ -299,7 +319,7 @@ EXPORT_SYMBOL_GPL(scmi_driver_register);
|
||||
void scmi_driver_unregister(struct scmi_driver *driver)
|
||||
{
|
||||
driver_unregister(&driver->driver);
|
||||
scmi_protocol_device_unrequest(driver->id_table);
|
||||
scmi_protocol_table_unregister(driver->id_table);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(scmi_driver_unregister);
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user