dasharo/linux
0
0
Fork 0
mirror of https://github.com/Dasharo/linux.git synced 2026-03-06 15:25:10 -08:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

Browse Source 
Pull phy updates from Vinod Koul:
 "New hardware support:

   - ST STM32MP25 combophy support

   - Sparx5 support for lan969x serdes and updates to driver to support
     this

   - NXP PTN3222 eUSB2 to USB2 redriver

   - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2
     support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP
     UFS PHY support and SA8775P eDP PHY support

   - Rockchip rk3576 usbdp and rk3576 usb2 phy support

   - Binding for Microchip ATA6561 can phy

  Updates:

   - Freescale driver updates from hdmi support

   - Conversion of rockchip rk3228 hdmi phy binding to yaml

   - Broadcom usb2-phy deprecated support dropped and USB init array
     update for BCM4908

   - TI USXGMII mode support in J7200

   - Switch back to platform_driver::remove() subsystem update"

* tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits)
  phy: qcom: qmp: Fix lecacy-legacy typo
  phy: lan969x-serdes: add support for lan969x serdes driver
  dt-bindings: phy: sparx5: document lan969x
  phy: sparx5-serdes: add support for branching on chip type
  phy: sparx5-serdes: add indirection layer to register macros
  phy: sparx5-serdes: add function for getting the CMU index
  phy: sparx5-serdes: add ops to match data
  phy: sparx5-serdes: add constant for the number of CMU's
  phy: sparx5-serdes: add constants to match data
  phy: sparx5-serdes: add support for private match data
  phy: bcm-ns-usb2: drop support for old binding variant
  dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant
  dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300
  dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible
  dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561
  phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions
  phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll()
  phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l()
  phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out()
  phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL
  ...
This commit is contained in:
Linus Torvalds
2024-11-27 13:33:43 -08:00
parent 7536c1a50e 32f4a76b8e
commit 0ce9a5ffca
81 changed files with 3056 additions and 1069 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.yaml
View File

@@ -18,16 +18,8 @@ properties:
const: brcm,ns-usb2-phy
reg:
anyOf:
- maxItems: 1
description: PHY control register
- maxItems: 1
description: iomem address range of DMU (Device Management Unit)
deprecated: true
reg-names:
items:
- const: dmu
maxItems: 1
description: PHY control register
brcm,syscon-clkset:
description: phandle to syscon for clkset register
@@ -50,12 +42,7 @@ required:
- clocks
- clock-names
- "#phy-cells"
oneOf:
- required:
- brcm,syscon-clkset
- required:
- reg-names
- brcm,syscon-clkset
additionalProperties: false

1
Documentation/devicetree/bindings/phy/fsl,mxs-usbphy.yaml
View File

@@ -32,6 +32,7 @@ properties:
- enum:
- fsl,imx8dxl-usbphy
- fsl,imx8qm-usbphy
- fsl,imx8qxp-usbphy
- fsl,imx8ulp-usbphy
- const: fsl,imx7ulp-usbphy

10
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
View File

@@ -125,6 +125,16 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
default: 28
power-domains:
description:
The TPHY of MediaTek should exist within a power domain. The
developer should be aware that the hardware design of MediaTek TPHY
does not require the addition of MTCMOS. If the power to the TPHY
is turned off, it will impact other functions. From the current
perspective of USB hardware design, even if MTCMOS is added to the
TPHY, it should remain always on.
maxItems: 1
# Required child node:
patternProperties:
"^(usb|pcie|sata)-phy@[0-9a-f]+$":

17
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml
View File

@@ -8,6 +8,7 @@ title: Microchip Sparx5 Serdes controller
maintainers:
- Steen Hegelund <steen.hegelund@microchip.com>
- Daniel Machon <daniel.machon@microchip.com>
description: |
The Sparx5 SERDES interfaces share the same basic functionality, but
@@ -62,12 +63,26 @@ description: |
* 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
* 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
lan969x has ten SERDES10G interfaces that share the same features, operating
modes and data rates as the equivalent Sparx5 SERDES10G interfaces.
properties:
$nodename:
pattern: "^serdes@[0-9a-f]+$"
compatible:
const: microchip,sparx5-serdes
oneOf:
- enum:
- microchip,sparx5-serdes
- microchip,lan9691-serdes
- items:
- enum:
- microchip,lan9698-serdes
- microchip,lan9696-serdes
- microchip,lan9694-serdes
- microchip,lan9693-serdes
- microchip,lan9692-serdes
- const: microchip,lan9691-serdes
reg:
minItems: 1

55
Documentation/devicetree/bindings/phy/nxp,ptn3222.yaml Normal file
View File

@@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/nxp,ptn3222.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP PTN3222 1-port eUSB2 to USB2 redriver
maintainers:
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
properties:
compatible:
enum:
- nxp,ptn3222
reg:
maxItems: 1
"#phy-cells":
const: 0
vdd1v8-supply:
description: power supply (1.8V)
vdd3v3-supply:
description: power supply (3.3V)
reset-gpios: true
required:
- compatible
- reg
- '#phy-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
redriver@4f {
compatible = "nxp,ptn3222";
reg = <0x4f>;
#phy-cells = <0>;
vdd3v3-supply = <&vreg_3p3>;
vdd1v8-supply = <&vreg_1p8>;
reset-gpios = <&gpio_reset GPIO_ACTIVE_LOW>;
};
};
...

2
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
View File

@@ -96,7 +96,7 @@ patternProperties:
Specifies the type of PHY for which the group of PHY lanes is used.
Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [2, 4]
enum: [2, 4, 8, 9]
cdns,num-lanes:
description:

43
Documentation/devicetree/bindings/phy/phy-rockchip-inno-hdmi.txt
View File

@@ -1,43 +0,0 @@
ROCKCHIP HDMI PHY WITH INNO IP BLOCK
Required properties:
- compatible : should be one of the listed compatibles:
* "rockchip,rk3228-hdmi-phy",
* "rockchip,rk3328-hdmi-phy";
- reg : Address and length of the hdmi phy control register set
- clocks : phandle + clock specifier for the phy clocks
- clock-names : string, clock name, must contain "sysclk" for system
control and register configuration, "refoclk" for crystal-
oscillator reference PLL clock input and "refpclk" for pclk-
based refeference PLL clock input.
- #clock-cells: should be 0.
- clock-output-names : shall be the name for the output clock.
- interrupts : phandle + interrupt specified for the hdmiphy interrupt
- #phy-cells : must be 0. See ./phy-bindings.txt for details.
Optional properties for rk3328-hdmi-phy:
- nvmem-cells = phandle + nvmem specifier for the cpu-version efuse
- nvmem-cell-names : "cpu-version" to read the chip version, required
for adjustment to some frequency settings
Example:
hdmi_phy: hdmi-phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
#phy-cells = <0>;
clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
clock-names = "sysclk", "refoclk", "refpclk";
#clock-cells = <0>;
clock-output-names = "hdmi_phy";
status = "disabled";
};
Then the PHY can be used in other nodes such as:
hdmi: hdmi@200a0000 {
compatible = "rockchip,rk3228-dw-hdmi";
...
phys = <&hdmi_phy>;
phy-names = "hdmi";
...
};

1
Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
View File

@@ -13,6 +13,7 @@ maintainers:
properties:
compatible:
enum:
- rockchip,rk3576-usbdp-phy
- rockchip,rk3588-usbdp-phy
reg:

1
Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
View File

@@ -17,6 +17,7 @@ description:
properties:
compatible:
enum:
- qcom,sa8775p-edp-phy
- qcom,sc7280-edp-phy
- qcom,sc8180x-edp-phy
- qcom,sc8280xp-dp-phy

7
Documentation/devicetree/bindings/phy/qcom,sa8775p-dwmac-sgmii-phy.yaml
View File

@@ -15,7 +15,12 @@ description:
properties:
compatible:
const: qcom,sa8775p-dwmac-sgmii-phy
oneOf:
- items:
- enum:
- qcom,qcs8300-dwmac-sgmii-phy
- const: qcom,sa8775p-dwmac-sgmii-phy
- const: qcom,sa8775p-dwmac-sgmii-phy
reg:
items:

3
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
View File

@@ -41,6 +41,7 @@ properties:
- qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x4-pcie-phy
- qcom,x1e80100-qmp-gen4x8-pcie-phy
reg:
minItems: 1
@@ -172,6 +173,7 @@ allOf:
- qcom,x1e80100-qmp-gen3x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x4-pcie-phy
- qcom,x1e80100-qmp-gen4x8-pcie-phy
then:
properties:
clocks:
@@ -202,6 +204,7 @@ allOf:
- qcom,sm8650-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x2-pcie-phy
- qcom,x1e80100-qmp-gen4x4-pcie-phy
- qcom,x1e80100-qmp-gen4x8-pcie-phy
then:
properties:
resets:

49
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
View File

@@ -15,26 +15,35 @@ description:
properties:
compatible:
enum:
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
- qcom,sc7180-qmp-ufs-phy
- qcom,sc7280-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm6115-qmp-ufs-phy
- qcom,sm6125-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm7150-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8450-qmp-ufs-phy
- qcom,sm8475-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
- qcom,sm8650-qmp-ufs-phy
oneOf:
- items:
- enum:
- qcom,qcs615-qmp-ufs-phy
- const: qcom,sm6115-qmp-ufs-phy
- items:
- enum:
- qcom,qcs8300-qmp-ufs-phy
- const: qcom,sa8775p-qmp-ufs-phy
- enum:
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
- qcom,sc7180-qmp-ufs-phy
- qcom,sc7280-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm6115-qmp-ufs-phy
- qcom,sm6125-qmp-ufs-phy
- qcom,sm6350-qmp-ufs-phy
- qcom,sm7150-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8450-qmp-ufs-phy
- qcom,sm8475-qmp-ufs-phy
- qcom,sm8550-qmp-ufs-phy
- qcom,sm8650-qmp-ufs-phy
reg:
maxItems: 1

2
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
View File

@@ -20,6 +20,7 @@ properties:
- qcom,ipq8074-qmp-usb3-phy
- qcom,ipq9574-qmp-usb3-phy
- qcom,msm8996-qmp-usb3-phy
- qcom,qcs8300-qmp-usb3-uni-phy
- qcom,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
- qcom,sc8180x-qmp-usb3-uni-phy
@@ -111,6 +112,7 @@ allOf:
compatible:
contains:
enum:
- qcom,qcs8300-qmp-usb3-uni-phy
- qcom,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
- qcom,sc8180x-qmp-usb3-uni-phy

1
Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml
View File

@@ -17,6 +17,7 @@ properties:
oneOf:
- items:
- enum:
- qcom,sar2130p-snps-eusb2-phy
- qcom,sdx75-snps-eusb2-phy
- qcom,sm8650-snps-eusb2-phy
- qcom,x1e80100-snps-eusb2-phy

1
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
View File

@@ -22,6 +22,7 @@ properties:
- const: qcom,usb-snps-hs-5nm-phy
- items:
- enum:
- qcom,qcs8300-usb-hs-phy
- qcom,qdu1000-usb-hs-phy
- qcom,sc7280-usb-hs-phy
- qcom,sc8180x-usb-hs-phy

45
Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
View File

@@ -20,6 +20,7 @@ properties:
- rockchip,rk3366-usb2phy
- rockchip,rk3399-usb2phy
- rockchip,rk3568-usb2phy
- rockchip,rk3576-usb2phy
- rockchip,rk3588-usb2phy
- rockchip,rv1108-usb2phy
@@ -34,10 +35,15 @@ properties:
const: 0
clocks:
maxItems: 1
minItems: 1
maxItems: 3
clock-names:
const: phyclk
minItems: 1
items:
- const: phyclk
- const: aclk
- const: aclk_slv
assigned-clocks:
description:
@@ -172,6 +178,41 @@ allOf:
- interrupts
- interrupt-names
- if:
properties:
compatible:
contains:
enum:
- rockchip,px30-usb2phy
- rockchip,rk3128-usb2phy
- rockchip,rk3228-usb2phy
- rockchip,rk3308-usb2phy
- rockchip,rk3328-usb2phy
- rockchip,rk3366-usb2phy
- rockchip,rk3399-usb2phy
- rockchip,rk3568-usb2phy
- rockchip,rk3588-usb2phy
- rockchip,rv1108-usb2phy
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3576-usb2phy
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
additionalProperties: false
examples:

97
Documentation/devicetree/bindings/phy/rockchip,rk3228-hdmi-phy.yaml Normal file
View File

@@ -0,0 +1,97 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,rk3228-hdmi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip HDMI PHY with Innosilicon IP block
maintainers:
- Heiko Stuebner <heiko@sntech.de>
properties:
compatible:
enum:
- rockchip,rk3228-hdmi-phy
- rockchip,rk3328-hdmi-phy
reg:
maxItems: 1
clocks:
maxItems: 3
clock-names:
items:
- const: sysclk
- const: refoclk
- const: refpclk
clock-output-names:
description:
The hdmiphy output clock name, that gets fed back to the CRU.
"#clock-cells":
const: 0
interrupts:
maxItems: 1
nvmem-cells:
maxItems: 1
description: A phandle + nvmem specifier for the cpu-version efuse
for adjustment to some frequency settings, depending on cpu-version
nvmem-cell-names:
items:
- const: cpu-version
'#phy-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- clock-output-names
- '#clock-cells'
- '#phy-cells'
allOf:
- if:
properties:
compatible:
contains:
const: rockchip,rk3228-hdmi-phy
then:
properties:
interrupts: false
- if:
properties:
compatible:
contains:
const: rockchip,rk3328-hdmi-phy
then:
required:
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/rk3228-cru.h>
hdmi_phy: phy@12030000 {
compatible = "rockchip,rk3228-hdmi-phy";
reg = <0x12030000 0x10000>;
#phy-cells = <0>;
clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>;
clock-names = "sysclk", "refoclk", "refpclk";
#clock-cells = <0>;
clock-output-names = "hdmi_phy";
};

119
Documentation/devicetree/bindings/phy/st,stm32mp25-combophy.yaml Normal file
View File

@@ -0,0 +1,119 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/st,stm32mp25-combophy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32MP25 USB3/PCIe COMBOPHY
maintainers:
- Christian Bruel <christian.bruel@foss.st.com>
description:
Single lane PHY shared (exclusive) between the USB3 and PCIe controllers.
Supports 5Gbit/s for USB3 and PCIe gen2 or 2.5Gbit/s for PCIe gen1.
properties:
compatible:
const: st,stm32mp25-combophy
reg:
maxItems: 1
"#phy-cells":
const: 1
clocks:
minItems: 2
items:
- description: apb Bus clock mandatory to access registers.
- description: ker Internal RCC reference clock for USB3 or PCIe
- description: pad Optional on board clock input for PCIe only. Typically an
external 100Mhz oscillator wired on dedicated CLKIN pad. Used as reference
clock input instead of the ker
clock-names:
minItems: 2
items:
- const: apb
- const: ker
- const: pad
resets:
maxItems: 1
reset-names:
const: phy
power-domains:
maxItems: 1
wakeup-source: true
interrupts:
maxItems: 1
description: interrupt used for wakeup
access-controllers:
maxItems: 1
description: Phandle to the rifsc device to check access right.
st,ssc-on:
$ref: /schemas/types.yaml#/definitions/flag
description:
A property whose presence indicates that the Spread Spectrum Clocking is active.
st,rx-equalizer:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
default: 2
description:
A 3 bit value to tune the RX fixed equalizer setting for optimal eye compliance
st,output-micro-ohms:
minimum: 3999000
maximum: 6090000
default: 4968000
description:
A value property to tune the Single Ended Output Impedance, simulations results
at 25C for a VDDP=0.8V. The hardware accepts discrete values in this range.
st,output-vswing-microvolt:
minimum: 442000
maximum: 803000
default: 803000
description:
A value property in microvolt to tune the Single Ended Output Voltage Swing to change the
Vlo, Vhi for a VDDP = 0.8V. The hardware accepts discrete values in this range.
required:
- compatible
- reg
- "#phy-cells"
- clocks
- clock-names
- resets
- reset-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
phy@480c0000 {
compatible = "st,stm32mp25-combophy";
reg = <0x480c0000 0x1000>;
#phy-cells = <1>;
clocks = <&rcc CK_BUS_USB3PCIEPHY>, <&rcc CK_KER_USB3PCIEPHY>;
clock-names = "apb", "ker";
resets = <&rcc USB3PCIEPHY_R>;
reset-names = "phy";
access-controllers = <&rifsc 67>;
power-domains = <&CLUSTER_PD>;
wakeup-source;
interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
};

13
Documentation/devicetree/bindings/phy/ti,tcan104x-can.yaml
View File

@@ -14,10 +14,15 @@ properties:
pattern: "^can-phy"
compatible:
enum:
- nxp,tjr1443
- ti,tcan1042
- ti,tcan1043
oneOf:
- items:
- enum:
- microchip,ata6561
- const: ti,tcan1042
- enum:
- ti,tcan1042
- ti,tcan1043
- nxp,tjr1443
'#phy-cells':
const: 0

4
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
View File

@@ -26,6 +26,7 @@ properties:
- qcom,msm8998-dwc3
- qcom,qcm2290-dwc3
- qcom,qcs404-dwc3
- qcom,qcs8300-dwc3
- qcom,qdu1000-dwc3
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
@@ -201,6 +202,7 @@ allOf:
- qcom,msm8953-dwc3
- qcom,msm8996-dwc3
- qcom,msm8998-dwc3
- qcom,qcs8300-dwc3
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
@@ -465,6 +467,7 @@ allOf:
- qcom,ipq4019-dwc3
- qcom,ipq8064-dwc3
- qcom,msm8994-dwc3
- qcom,qcs8300-dwc3
- qcom,qdu1000-dwc3
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
@@ -490,6 +493,7 @@ allOf:
minItems: 4
maxItems: 5
interrupt-names:
minItems: 4
items:
- const: pwr_event
- const: hs_phy_irq

Some files were not shown because too many files have changed in this diff Show More