4010 Commits

Author SHA1 Message Date
Michał Iwanicki
03d1e9923c Merge remote-tracking branch 'upstream/main' into sync
Change-Id: Iedd0b91ca800373460c35de69427ea4056e6e8b9
Signed-off-by: Michał Iwanicki <michal.iwanicki@3mdeb.com>
2025-09-17 12:41:44 +02:00
Antonio Vázquez Blanco
b6843e012e meson: Separate documentation options
Change-Id: Ie7ad3e6acaf7fcac93b7542f3b3d65e072858802
Signed-off-by: Antonio Vázquez Blanco <antoniovazquezblanco@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-09-05 12:15:53 +00:00
Vincent Fazio
5a4abf6a3c flashchips: Mark MT25QL02G as tested for PREW
Tested via linux_spi [0].

[0]: https://paste.flashrom.org/view.php?id=3775

Change-Id: Ied3439b95104e37b7d22547ded883870eb2ab500
Tested-by: Jacob Zarnstorff <jzarnstorff@xes-inc.com>
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-09-01 10:47:44 +00:00
Vincent Fazio
09b72c2d56 flashchips: Mark MT25QU02G as tested for PREW
Tested via linux_spi [0].

[0]: https://paste.flashrom.org/view.php?id=3774

Change-Id: Ida2ba300adf18280da325c1cf94a2df32f9163c6
Tested-by: Jacob Zarnstorff <jzarnstorff@xes-inc.com>
Signed-off-by: Vincent Fazio <vfazio@xes-inc.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88985
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-09-01 10:23:51 +00:00
Jacob Rothbauer
9e0a4fe374 build: only add git describe for git checkouts
Some tools, such as Buildroot, will use packed tarballs of cloned git
repositories and trigger builds for the sources. This results in
flashrom grabbing incorrect git information. The best option is to
solely rely on the VERSION file.

Change-Id: Iac60ae253263eab42361b0f73a9c9c95cd547eb5
Signed-off-by: Jacob Rothbauer <rothbauerj@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-08-31 08:10:05 +00:00
Mario Limonciello (AMD)
c6ceecf311 Add missing /* __FLASHROM_LITTLE_ENDIAN__ */
To make it clearer what a #endif matches add a comment.

Change-Id: Ie3a251a85f03e4ff6babd71d5df9c6725c187265
Suggested-by: Anastasia Klimchuk <aklm@flashrom.org>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-08-23 00:02:15 +00:00
Mario Limonciello (AMD)
f74f02e22c Add guard for compare_region_with_dump()
Big endian architectures don't use the function. This fixes a FTBFS
on big endian architectures.

Change-Id: Ied3e12352e7fde73355f6a8a226eea0e5b101721
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88817
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-23 00:02:08 +00:00
Simon Buhrow
182902ee01 cli_classic.c: Print runtime measurement in seconds in debug
To get a fast and easy feedback on how parameters affect runtime
(e.g. clock setting, polling delays, etc).

The runtime is measured starting from programmer_init and to
programmer_shutdown, inclusive. Message is displayed in debug
verbosity level.

Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de>
Change-Id: I2238b3f3e6c2ab7745994662a88787fa2e86d480
Co-Developed-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/47805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-08-20 06:34:31 +00:00
Anastasia Klimchuk
008919aa69 Erase should respect --noverify option
This commit adds check for the flag `verify_after_write` after
erase operation and does not perfom verification if the flag
disabled.
From command line, this is set by --noverify option.
libflashrom flag is FLASHROM_FLAG_VERIFY_AFTER_WRITE

Default stays the same, by default verification is performed.

This commit also adds test for the scenario.

Previously, erase operation ignored --noverify option and always
performed verification.

For more details, see
Ticket: https://ticket.coreboot.org/issues/520

Change-Id: I9f6cb7210f4dcdc32870f9096657a08b12e77c7f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88734
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Carly Zlabek <carlyzlabek@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Vincent Fazio <vfazio@gmail.com>
2025-08-20 06:33:56 +00:00
Anastasia Klimchuk
fa2d2ccb94 Check verify flag in prepare_flash_access before erase operation
The last argument in `prepare_flash_access` function indicates
whether verify operation was requested. This information is
in the flag `verify_after_write` in flash context, so lets pass
it to the function.

Previously, the last argument which is called `verify_it`
was always `false`. This hasn't been detected because in the
current implementation of `prepare_flash_access`,
`verify_it` is always checked together with `erase_it`, the
latter was passed always true.

`verify_it` being false is wrong because we have a flag to decide
about verification. Also this false value contradicts reality,
because erase operation ignores the flag and always verifies
(this has always been the case even with earlier implementations
of erase logic).

Additional context is in the next commit and ticket
https://ticket.coreboot.org/issues/520

Change-Id: Idd7526084e4942b7adbbab57a62f7de84b4a4bb5
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-08-20 06:33:46 +00:00
Anastasia Klimchuk
e754f17af1 doc: Add items to recent development document
Change-Id: Id5c254f011fac2ded919c2d86dc443b36b104527
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2025-08-08 22:53:48 +00:00
Anastasia Klimchuk
7e38723877 tests: Add tests which run a chain of operations
The main purpose is to run one operation after the other to
check that data is carried in flash context correctly.

As the most common chains, the first tests perform:
probe+read
probe+write
probe+erase

Change-Id: I9b09e04c7dbee7e7658118d66aacb640885f4d23
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88257
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-05 00:59:38 +00:00
Varun Upadhyay
44df54b5e4 util/ich_descriptors_tool: Add Wildcat Lake SoC to supported chipsets
TEST=ich_descriptors_tool is able to detect "wildcat" chipset and show
below information:

> ./util/ich_descriptors_tool/ich_descriptors_tool
Need the file name of a descriptor image to read from.
usage: './util/ich_descriptors_tool/ich_descriptors_tool -f
<image file name> [-c <chipset name>] [-d]'
...
...
To also print the data stored in the descriptor straps you have to
indicate the chipset series with the '-c' parameter and one of the
possible arguments:
	- "ich8",
	- "ich9",
	- "ich10",
	- "apollo" for Intel's Apollo Lake SoC.
	- "gemini" for Intel's Gemini Lake SoC.
	- "jasper" for Intel's Jasper Lake SoC.
	- "meteor" for Intel's Meteor Lake SoC.
	- "panther" for Intel's Panther Lake SoC.
        - "wildcat" for Intel's Wildcat Lake SoC.
	...
	...
	- "300" or "cannon" for Intel's 300 series chipsets.
	- "400" or "comet" for Intel's 400 series chipsets.
	- "500" or "tiger" for Intel's 500 series chipsets.
	- "600" or "alder" for Intel's 600 series chipsets.

Change-Id: I2957eab19d8b8fdd2479f7d1b50ecdb48f491954
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88049
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-08-03 08:03:16 +00:00
Varun Upadhyay
446af8ae1c ichspi: Add support for Wildcat Lake
TEST=Flashrom is able to detect WCL SPI DID and show chipset name as
below:

> flashrom --flash-name
....
Found chipset "Intel Wildcat Lake".
....
> flashrom -p internal --ifd -i fd -i bios -r /tmp/bios.rom
....
Found chipset "Intel Wildcat Lake".
Reading ich_descriptor... done.
Using regions: "bios", "fd".
Reading flash... done.
SUCCESS

Change-Id: Iaf1dc346b215c53cd2a0f6cf6e2cf4a8e6b5c19c
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-08-03 08:03:07 +00:00
James Vogenthaler
ff7091e9f4 flashchips: Add P25D80H
Adds support for the PUYA P25D80H flashchip.
Tested:     Probing RDID, reading, erasing, and writing to a single chip.
Programmer: A serprog implementation that was flashed to a Raspbery Pi Pico 2.
Parameters: Tested at 1Mhz
OS:         Raspberry Pi OS 64-bit running kernel version 6.12.38
Datasheet:  https://lcsc.com/datasheet/lcsc_datasheet_2304140030_PUYA-P25D80H-SSH-IT_C559199.pdf

Change-Id: I48612c369b555fb8c3f3cfe3ce0d00d3fd35a64f
Signed-off-by: James Vogenthaler <james.vogenthaler@mantech.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
2025-08-01 08:04:10 +00:00
Anastasia Klimchuk
2beb555a6a MAINTAINERS: Add Anastasia Klimchuk for [lib]flashrom.c
Change-Id: Ief22cc11df9813a1e08a4f3a6805d2d6d61fd57b
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-25 08:58:11 +00:00
Andranux
c0bf7928a2 flashchips: Add EN25QX128A
I tested with an "ch341a" usb adapter.
I was able to read, erase and write successfully.

Datasheet: https://www.esmt.com.tw/upload/pdf/ESMT/datasheets/EN25QX128A(2V).pdf

Change-Id: If6c5c3c37f3d817d93abdbc60c2d9280ff2585c3
Signed-off-by: Andranux <andranux+coding@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88327
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-25 08:56:37 +00:00
Anastasia Klimchuk
7649c805fb VERSION: Update version to v1.7.0-devel
Change-Id: I741dcb6459f02903f5d6136d3095e0630fb033f2
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-25 02:52:38 +00:00
Anastasia Klimchuk
c7946a3d3f doc/release_notes: Add link to tarball for v1.6.0
Change-Id: I469b1c3da3a8ed4a8a1667705a0ef9d67bdfa3de
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88550
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-24 05:13:26 +00:00
Anastasia Klimchuk
8e36840a28 VERSION: Update version to v1.6.0
Change-Id: I3561aa49ee7b3c30d40beddcd1457ca9b8e803db
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-24 01:31:52 +00:00
Anastasia Klimchuk
b0cdde91db doc: Release notes for v1.6.0
Change-Id: I7067f0756bd7a3e6387039cbc4290526723dc4d8
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-23 23:49:45 +00:00
Peter Marheine
546c74e1fc doc: hall of fame: support correcting names that are wrong
We identified somebody whose name was malformed in git history such that
they were credited wrong in the hall of fame, so add some code to handle
names that manage to be committed with incorrect formatting.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I33b04932403b2d69da4648a3a7016aee57741d0d
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88477
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-21 09:32:31 +00:00
Anastasia Klimchuk
4e1d9ad953 VERSION: Update version to v1.6.0-rc2
Change-Id: I3d62baf6083a5ae2936ec16771e8e3a5a213181f
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-17 03:07:11 +00:00
Anastasia Klimchuk
af51624516 doc: Check minimum sphinx version for building hall of fame
Building authors/reviewers list (aka Hall of Fame) requires
more modern sphinx version than the rest of documentation. Also
we have separate meson options, `documentation` and
`generate_authors_list`, which both default to `auto`.

Auto mode is expected to check the environment and enable the
option if environment is suitable - or disable otherwise.

The patch check minimun required sphinx version specifically
for building hall of fame, the rest of documentation just checks
that sphinx is present.

So if developer has old version of sphinx, all the documentation
will be built, just without hall of fame.

Without this patch, developer with generate_authors_list=auto
(which is default) and old version of sphinx gets a build error
like this:
Exception occurred:
  File "/usr/lib/python3/dist-packages/docutils/nodes.py",
		line 652, in __getitem__
    return self.attributes[key]
KeyError: 'colwidth'
and a stack trace from sphinx source code

Change-Id: I8f0ae62f33dca04c2c5233ea45c6263f10cbe4f9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-16 08:34:35 +00:00
Anastasia Klimchuk
966cd5194c VERSION: Update version to v1.6.0-rc1
Change-Id: Iefe3c3b2bdd62dd6afff97dc3fddef89d60e06ba
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/88280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
2025-07-04 01:55:39 +00:00