mirror of
https://github.com/Dasharo/f4pga.git
synced 2026-06-13 19:16:35 -07:00
f4pga/utils: all python scripts moved from xc7 arch-defs tarballs
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
This commit is contained in:
Unai Martinez-Corral
@@ -91,7 +91,7 @@ xc7a50t: &xc7
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params:
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stage_name: ioplace
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interpreter: '${python3}'
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script: '${shareDir}/scripts/prjxray_create_ioplace.py'
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script: ['-m', 'f4pga.utils.xc7.create_ioplace']
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outputs:
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io_place:
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mode: stdout
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@@ -107,7 +107,7 @@ xc7a50t: &xc7
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params:
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stage_name: place_constraints
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interpreter: '${python3}'
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script: '${shareDir}/scripts/prjxray_create_place_constraints.py'
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script: ['-m', 'f4pga.utils.xc7.create_place_constraints']
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outputs:
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place_constraints:
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mode: stdout
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@@ -0,0 +1,96 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2019-2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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# Top level keywords defining the begin of a cell definition.
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top_level = [
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"model",
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"inputs",
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"outputs",
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"names",
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"latch",
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"subckt",
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]
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# Keywords defining cell attributes / parameters. Those can be specified for
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# each cell multiple times. Parameter names and values are stored in a dict
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# under the parsed blif data.
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#
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# For example: the construct ".param MODE SYNC" will add to the dict under
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# the key "param" entry "MODE":"SYNC".
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#
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sub_level = [
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"attr",
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"param",
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]
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def parse_blif(f):
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current = None
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data = {}
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def add(d):
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if d["type"] not in data:
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data[d["type"]] = []
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data[d["type"]].append(d)
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current = None
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for oline in f:
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line = oline
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if "#" in line:
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line = line[: line.find("#")]
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line = line.strip()
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if not line:
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continue
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if line.startswith("."):
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args = line.split(" ", maxsplit=1)
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if len(args) < 2:
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args.append("")
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ctype = args.pop(0)
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assert ctype.startswith("."), ctype
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ctype = ctype[1:]
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if ctype in top_level:
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if current:
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add(current)
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current = {
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"type": ctype,
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"args": args[-1].split(),
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"data": [],
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}
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elif ctype in sub_level:
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if ctype not in current:
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current[ctype] = {}
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key, value = args[-1].split(maxsplit=1)
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current[ctype][key] = value
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else:
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current[ctype] = args[-1].split()
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continue
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current["data"].append(line.strip().split())
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if current:
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add(current)
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assert len(data["inputs"]) == 1
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data["inputs"] = data["inputs"][0]
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assert len(data["outputs"]) == 1
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data["outputs"] = data["outputs"][0]
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return data
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@@ -0,0 +1,63 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2019-2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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"""
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Supported PCF commands:
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* set_io <net> <pad> - constrain a given <net> to a given physical <pad> in eFPGA pinout.
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* set_clk <pin> <net> - constrain a given global clock <pin> to a given <net>
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Every tile where <net> is present will be constrained to use a given global clock.
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"""
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from collections import namedtuple
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import re
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PcfIoConstraint = namedtuple("PcfIoConstraint", "net pad line_str line_num")
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PcfClkConstraint = namedtuple("PcfClkConstraint", "pin net")
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def parse_simple_pcf(f):
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"""Parse a simple PCF file object and yield PcfIoConstraint objects."""
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for line_number, line in enumerate(f):
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line_number += 1
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# Remove comments.
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args = re.sub(r"#.*", "", line.strip()).split()
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if not args:
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continue
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# Ignore arguments.
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args = [arg for arg in args if arg[0] != "-"]
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assert len(args) == 3, args
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if args[0] == "set_io":
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yield PcfIoConstraint(
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net=args[1],
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pad=args[2],
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line_str=line.strip(),
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line_num=line_number,
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)
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if args[0] == "set_clk":
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yield PcfClkConstraint(
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pin=args[1],
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net=args[2],
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)
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@@ -0,0 +1,264 @@
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#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2019-2022 F4PGA Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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from __future__ import print_function
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from collections import OrderedDict, namedtuple
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import itertools
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import re
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import lxml.etree as ET
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from f4pga.utils.eblif import parse_blif
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IoConstraint = namedtuple("IoConstraint", "name x y z comment")
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HEADER_TEMPLATE = """\
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#{name:<{nl}} x y z pcf_line
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#{s:-^{nl}} -- -- - ----"""
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CONSTRAINT_TEMPLATE = "{name:<{nl}} {x: 3} {y: 3} {z: 2} # {comment}"
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INOUT_REGEX = re.compile(r"^(.+)(_\$inp|_\$out)(.*)$")
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NETNAME_REGEX = re.compile(r"(.+?)(\[[0-9]+\]$|$)")
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class IoPlace(object):
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def __init__(self):
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self.constraints = OrderedDict()
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self.inputs = set()
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self.outputs = set()
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self.net_to_block = None
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self.net_map = {}
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self.block_to_inst = {}
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self.inout_nets = set()
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self.net_to_pad = set()
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self.net_file_io = set()
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def read_io_loc_pairs(self, blif):
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"""
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Read IO_LOC_PAIRS parameters from eblif carrying the information
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which package pin a specified top port is constrained, e.g. O_LOC_PAIRS = "portA:D1"
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In case of differential inputs/outputs there are two pairs of the parameter,
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i.e. IO_LOC_PAIRS = "portA_p:D2,portA_n:D4"
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"""
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if "subckt" not in blif:
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return
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for attr in blif["subckt"]:
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if "param" not in attr:
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continue
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if "IO_LOC_PAIRS" in attr["param"]:
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locs = attr["param"]["IO_LOC_PAIRS"][1:-1].split(",")
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if "NONE" in locs:
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continue
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for loc in locs:
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net, pad = loc.split(":")
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self.net_to_pad.add((net, pad))
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def read_io_list_from_eblif(self, eblif_file):
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blif = parse_blif(eblif_file)
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self.inputs = set(blif["inputs"]["args"])
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self.outputs = set(blif["outputs"]["args"])
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# Build a net name map that maps products of an inout port split into
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# their formet name.
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#
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# For example, an inout port 'A' is split into 'A_$inp' and 'A_$out',
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# port B[2] into 'B_$inp[2]' and 'B_$out[2]'.
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self.net_map = {}
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self.inout_nets = set()
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for net in itertools.chain(self.inputs, self.outputs):
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match = INOUT_REGEX.match(net)
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if match:
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alias = match.group(1) + match.group(3)
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self.inout_nets.add(alias)
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self.net_map[net] = alias
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else:
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self.net_map[net] = net
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self.read_io_loc_pairs(blif)
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def load_block_names_from_net_file(self, net_file):
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"""
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.place files expect top-level block (cluster) names, not net names, so
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build a mapping from net names to block names from the .net file.
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"""
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net_xml = ET.parse(net_file)
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net_root = net_xml.getroot()
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self.net_to_block = {}
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for block in net_root.xpath("//block"):
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instance = block.attrib["instance"]
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if instance != "inpad[0]" and instance != "outpad[0]":
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continue
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top_block = block.getparent()
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assert top_block is not None
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while top_block.getparent() is not net_root:
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assert top_block is not None
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top_block = top_block.getparent()
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self.net_to_block[block.get("name")] = top_block.get("name")
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# Loop over all top-level blocks. Store block name to its instance
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# correspondences.
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for block_xml in net_root.findall("block"):
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name = block_xml.attrib["name"]
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inst = block_xml.attrib["instance"]
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assert name not in self.block_to_inst, block_xml.attrib
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self.block_to_inst[name] = inst
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def load_net_file_ios(self, net_file):
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"""
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Loads input and outputs net names from the netlist file.
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"""
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def get_ios(net_root, io_types):
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"Get the top level io signals from the netlist XML root."
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for io_type in io_types:
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io = net_root.xpath("/block/{}/text ()".format(io_type))
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if len(io) == 1:
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yield io[0]
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net_xml = ET.parse(net_file)
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net_root = net_xml.getroot()
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for io_line in get_ios(net_root, ["inputs", "outputs"]):
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io_list = io_line.split(" ")
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for io in io_list:
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self.net_file_io.add(io.replace("out:", ""))
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def get_top_level_block_instance_for_net(self, net_name):
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"""
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Returns a name of the top-level block instance for the given net
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name.
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"""
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assert self.is_net(net_name)
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# VPR prefixes output constraints with "out:"
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if net_name in self.outputs:
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net_name = "out:" + net_name
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# This is an inout net
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if net_name in self.inout_nets:
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block_names = set()
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for prefix, suffix in zip(["", "out:"], ["_$inp", "_$out"]):
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match = NETNAME_REGEX.match(net_name)
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name = prefix + match.group(1) + suffix + match.group(2)
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block_names.add(self.net_to_block[name])
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# Both parts of the net should point to the same block
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assert len(block_names) == 1, (net_name, block_names)
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return self.block_to_inst[list(block_names)[0]]
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# A regular net
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else:
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if net_name in self.net_to_block:
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block_name = self.net_to_block[net_name]
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return self.block_to_inst[block_name]
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else:
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return None
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def constrain_net(self, net_name, loc, comment=""):
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assert len(loc) == 3
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assert net_name not in self.constraints
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assert self.is_net(net_name), "net {} not in eblif".format(net_name)
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# VPR prefixes output constraints with "out:"
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if net_name in self.outputs:
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net_name = "out:" + net_name
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# This is an inout net
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if net_name in self.inout_nets:
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for prefix, suffix in zip(["", "out:"], ["_$inp", "_$out"]):
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|
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match = NETNAME_REGEX.match(net_name)
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name = prefix + match.group(1) + suffix + match.group(2)
|
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|
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self.constraints[name] = IoConstraint(
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name=name,
|
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x=loc[0],
|
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y=loc[1],
|
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z=loc[2],
|
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comment=comment,
|
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)
|
||||
|
||||
# A regular net
|
||||
else:
|
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self.constraints[net_name] = IoConstraint(
|
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name=net_name,
|
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x=loc[0],
|
||||
y=loc[1],
|
||||
z=loc[2],
|
||||
comment=comment,
|
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)
|
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|
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def output_io_place(self, f):
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max_name_length = max(len(c.name) for c in self.constraints.values())
|
||||
print(HEADER_TEMPLATE.format(name="Block Name", nl=max_name_length, s=""), file=f)
|
||||
|
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constrained_blocks = {}
|
||||
|
||||
for vpr_net, constraint in self.constraints.items():
|
||||
name = constraint.name
|
||||
name = self.net_to_block.get(name) if self.net_to_block else name
|
||||
|
||||
# This block is already constrained, check if there is no
|
||||
# conflict there.
|
||||
if name in constrained_blocks:
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||||
existing = constrained_blocks[name]
|
||||
|
||||
if existing.x != constraint.x or existing.y != constraint.y or existing.z != constraint.z:
|
||||
|
||||
print("Error: block '{}' has multiple conflicting constraints!".format(name))
|
||||
print("", constrained_blocks[name])
|
||||
print("", constraint)
|
||||
exit(-1)
|
||||
|
||||
# Don't write the second constraing
|
||||
continue
|
||||
|
||||
# omit if no corresponding block name for the net
|
||||
if name is not None:
|
||||
print(
|
||||
CONSTRAINT_TEMPLATE.format(
|
||||
name=name,
|
||||
nl=max_name_length,
|
||||
x=constraint.x,
|
||||
y=constraint.y,
|
||||
z=constraint.z,
|
||||
comment=constraint.comment,
|
||||
),
|
||||
file=f,
|
||||
)
|
||||
|
||||
# Add to constrained block list
|
||||
constrained_blocks[name] = constraint
|
||||
|
||||
def is_net(self, net):
|
||||
return net in self.net_map.values()
|
||||
|
||||
def is_net_packed(self, net):
|
||||
return net in self.net_file_io
|
||||
|
||||
def get_nets(self):
|
||||
for net in self.inputs:
|
||||
yield self.net_map[net]
|
||||
for net in self.outputs:
|
||||
yield self.net_map[net]
|
||||
@@ -0,0 +1,175 @@
|
||||
#!/usr/bin/env python3
|
||||
# -*- coding: utf-8 -*-
|
||||
#
|
||||
# Copyright (C) 2019-2022 F4PGA Authors
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
"""
|
||||
Convert a PCF file into a VPR io.place file.
|
||||
"""
|
||||
|
||||
|
||||
from argparse import ArgumentParser, FileType
|
||||
from pathlib import Path
|
||||
from csv import DictReader as csv_DictReader
|
||||
from sys import stdout, stderr, exit as sys_exit
|
||||
from json import dump as json_dump, load as json_load
|
||||
|
||||
from f4pga.utils.vpr_io_place import IoPlace
|
||||
from f4pga.utils.pcf import parse_simple_pcf
|
||||
|
||||
|
||||
def p_main(blif, map, net, pcf=None, output=stdout, iostandard_defs_file=None, iostandard="LVCMOS33", drive=12):
|
||||
io_place = IoPlace()
|
||||
io_place.read_io_list_from_eblif(blif)
|
||||
io_place.load_block_names_from_net_file(net)
|
||||
|
||||
# Map of pad names to VPR locations.
|
||||
pad_map = {}
|
||||
|
||||
for pin_map_entry in csv_DictReader(map):
|
||||
pad_map[pin_map_entry["name"]] = (
|
||||
(
|
||||
int(pin_map_entry["x"]),
|
||||
int(pin_map_entry["y"]),
|
||||
int(pin_map_entry["z"]),
|
||||
),
|
||||
pin_map_entry["is_output"],
|
||||
pin_map_entry["iob"],
|
||||
pin_map_entry["real_io_assoc"],
|
||||
)
|
||||
|
||||
iostandard_defs = {}
|
||||
|
||||
# Load iostandard constraints. This is a temporary workaround that allows
|
||||
# to pass them into fasm2bels. As soon as there is support for XDC this
|
||||
# will not be needed anymore.
|
||||
# If there is a JSON file with the same name as the PCF file then it is
|
||||
# loaded and used as iostandard constraint source NOT for the design but
|
||||
# to be used in fasm2bels.
|
||||
iostandard_constraints = {}
|
||||
|
||||
if pcf is not None:
|
||||
fname = Path(pcf.name.replace(".pcf", ".json"))
|
||||
if fname.is_file():
|
||||
with fname.open("r") as fp:
|
||||
iostandard_constraints = json_load(fp)
|
||||
net_to_pad = io_place.net_to_pad
|
||||
if pcf is not None:
|
||||
net_to_pad |= set((constr.net, constr.pad) for constr in parse_simple_pcf(pcf))
|
||||
# Check for conflicting pad constraints
|
||||
net_to_pad_map = dict()
|
||||
for (net, pad) in net_to_pad:
|
||||
if net not in net_to_pad_map:
|
||||
net_to_pad_map[net] = pad
|
||||
elif pad != net_to_pad_map[net]:
|
||||
print(
|
||||
f"ERROR: Conflicting pad constraints for net {net}:\n{pad}\n{net_to_pad_map[net]}",
|
||||
file=stderr,
|
||||
)
|
||||
sys_exit(1)
|
||||
|
||||
# Constrain nets
|
||||
for net, pad in net_to_pad:
|
||||
if not io_place.is_net(net):
|
||||
nets = "\n".join(io_place.get_nets())
|
||||
print(
|
||||
f"ERROR: Constrained net {net} is not in available netlist:\n{nets}",
|
||||
file=stderr,
|
||||
)
|
||||
sys_exit(1)
|
||||
|
||||
if pad not in pad_map:
|
||||
pads = "\n".join(sorted(pad_map.keys()))
|
||||
print(
|
||||
f"ERROR: Constrained pad {pad} is not in available pad map:\n{pads}",
|
||||
file=stderr,
|
||||
)
|
||||
sys_exit(1)
|
||||
|
||||
loc, is_output, iob, real_io_assoc = pad_map[pad]
|
||||
|
||||
io_place.constrain_net(net_name=net, loc=loc, comment="set_property LOC {} [get_ports {{{}}}]".format(pad, net))
|
||||
if real_io_assoc == "True":
|
||||
iostandard_defs[iob] = (
|
||||
iostandard_constraints[pad]
|
||||
if pad in iostandard_constraints
|
||||
else ({"DRIVE": drive, "IOSTANDARD": iostandard} if is_output else {"IOSTANDARD": iostandard})
|
||||
)
|
||||
|
||||
io_place.output_io_place(output)
|
||||
|
||||
# Write iostandard definitions
|
||||
if iostandard_defs_file is not None:
|
||||
with Path(iostandard_defs_file).open("w") as f:
|
||||
json_dump(iostandard_defs, f, indent=2)
|
||||
|
||||
|
||||
def main(
|
||||
blif,
|
||||
map,
|
||||
net,
|
||||
pcf=None,
|
||||
output=None,
|
||||
iostandard_defs_file=None,
|
||||
iostandard="LVCMOS33",
|
||||
drive=12,
|
||||
):
|
||||
p_main(
|
||||
blif=Path(blif).open("r"),
|
||||
map=Path(map).open("r"),
|
||||
net=Path(net).open("r"),
|
||||
pcf=None if pcf is None else Path(pcf).open("r"),
|
||||
output=stdout if output is None else Path(output).open("w"),
|
||||
iostandard_defs_file=iostandard_defs_file,
|
||||
iostandard=iostandard,
|
||||
drive=drive,
|
||||
)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
parser = ArgumentParser(description="Convert a PCF file into a VPR io.place file.")
|
||||
parser.add_argument("--pcf", "-p", "-P", type=FileType("r"), required=False, help="PCF input file")
|
||||
parser.add_argument("--blif", "-b", type=FileType("r"), required=True, help="BLIF / eBLIF file")
|
||||
parser.add_argument("--map", "-m", "-M", type=FileType("r"), required=True, help="Pin map CSV file")
|
||||
parser.add_argument("--output", "-o", "-O", type=FileType("w"), default=stdout, help="The output io.place file")
|
||||
parser.add_argument("--iostandard_defs", help="(optional) Output IOSTANDARD def file")
|
||||
parser.add_argument(
|
||||
"--iostandard",
|
||||
default="LVCMOS33",
|
||||
help="Default IOSTANDARD to use for pins",
|
||||
)
|
||||
parser.add_argument(
|
||||
"--drive",
|
||||
type=int,
|
||||
default=12,
|
||||
help="Default drive to use for pins",
|
||||
)
|
||||
parser.add_argument("--net", "-n", type=FileType("r"), required=True, help="top.net file")
|
||||
|
||||
args = parser.parse_args()
|
||||
|
||||
p_main(
|
||||
blif=args.blif,
|
||||
map=args.map,
|
||||
net=args.net,
|
||||
pcf=args.pcf,
|
||||
output=args.output,
|
||||
iostandard_defs_file=args.iostandard_defs,
|
||||
iostandard=args.iostandard,
|
||||
drive=args.drive,
|
||||
)
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -37,6 +37,11 @@ isQuickLogic = FPGA_FAM != "xc7"
|
||||
SH_SUBDIR = "quicklogic" if isQuickLogic else FPGA_FAM
|
||||
|
||||
|
||||
if not isQuickLogic:
|
||||
from f4pga.utils.xc7.create_ioplace import main as xc7_create_ioplace
|
||||
from f4pga.utils.xc7.create_place_constraints import main as xc7_create_place_constraints
|
||||
|
||||
|
||||
# Helper functions
|
||||
|
||||
|
||||
@@ -472,26 +477,22 @@ fi
|
||||
)
|
||||
else:
|
||||
(eblif, net, part, device, arch_def) = sys_argv[1:6]
|
||||
pcf_opts = f"'--pcf' '{sys_argv[6]}'" if len(sys_argv) > 6 else ""
|
||||
ioplace_file = f"{Path(eblif).stem}.ioplace"
|
||||
p_run_bash_cmds(
|
||||
f"""
|
||||
set -e
|
||||
python3 '{F4PGA_SHARE_DIR}/scripts/prjxray_create_ioplace.py' \
|
||||
--blif '{eblif}' \
|
||||
--net '{net}' {pcf_opts} \
|
||||
--map '{F4PGA_SHARE_DIR}/arch/{device}/{part}/pinmap.csv' \
|
||||
> '{ioplace_file}'
|
||||
python3 '{F4PGA_SHARE_DIR}'/scripts/prjxray_create_place_constraints.py \
|
||||
--blif '{eblif}' \
|
||||
--net '{net}' \
|
||||
--arch '{arch_def}' \
|
||||
--part '{part}' \
|
||||
--vpr_grid_map '{F4PGA_SHARE_DIR}/arch/{device}/vpr_grid_map.csv' \
|
||||
--input '{ioplace_file}' \
|
||||
--db_root "${{DATABASE_DIR:-$(prjxray-config)}}" \
|
||||
> constraints.place
|
||||
"""
|
||||
xc7_create_ioplace(
|
||||
blif=eblif,
|
||||
map=f"{F4PGA_SHARE_DIR}/arch/{device}/{part}/pinmap.csv",
|
||||
net=net,
|
||||
output=ioplace_file,
|
||||
pcf=Path(sys_argv[6]).open("r") if len(sys_argv) > 6 else None,
|
||||
)
|
||||
xc7_create_place_constraints(
|
||||
blif=eblif,
|
||||
net=net,
|
||||
arch=arch_def,
|
||||
part=part,
|
||||
vpr_grid_map=f"{F4PGA_SHARE_DIR}/arch/{device}/vpr_grid_map.csv",
|
||||
input=ioplace_file,
|
||||
output="constraints.place",
|
||||
)
|
||||
|
||||
|
||||
|
||||
@@ -191,7 +191,7 @@ techmap -map $::env(TECHMAP_PATH)/carry_map.v
|
||||
clean_processes
|
||||
write_json $::env(OUT_JSON).carry_fixup.json
|
||||
|
||||
exec $::env(PYTHON3) $::env(UTILS_PATH)/fix_xc7_carry.py < $::env(OUT_JSON).carry_fixup.json > $::env(OUT_JSON).carry_fixup_out.json
|
||||
exec $::env(PYTHON3) -m f4pga.utils.xc7.fix_xc7_carry < $::env(OUT_JSON).carry_fixup.json > $::env(OUT_JSON).carry_fixup_out.json
|
||||
design -push
|
||||
read_json $::env(OUT_JSON).carry_fixup_out.json
|
||||
|
||||
|
||||
Reference in New Issue
Block a user