Modern AMD platforms cannot initialize graphics in 32bit mode (using
PEI GOP or VBIOS), because of UMA memory allocation above 4G by
default. One would have to force the recovery path so that UMA is
allocated below 4G. To allow running AMD x64 GOP, some modifications
are needed. Firstly, the GOP still needs VBIOS, so PCI IO must provide
it from FFS. Then, the GOP driver must also be included in the FFS, so
that DXE dispatcher picks it up and runs it.
TEST=Successfully initialize integrated graphics on MSI PRO B850-P WIFI.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
coreboot always uses TSC for timestamps, force correct timer library
so measurements are accurate. A mismatch of timers will result in
incorrect tick and nanosecond calculations due to different timer
frequency.
Add a copy of BaseCpuTimerLib from UefiCpuPkg and replace TSC frequency
calculation with the value obtained from coreboot timestamp table.
On Intel systems where the UefiCpuPkg/CpuTimerLib is used, there is no
mismatch. However, AMD systems do not have the required CPUID, so the
default timer is HPET, not TSC.
TEST=Boot Gigabyte MZ33-AR1 and use systemd-analyze. The firmware boot
time is no longer 19 minutes, but indicates correct time spent in
firmware.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
AMD silicon has different definitions for SLP_Sx states written
to the ACPI PM register than Intel.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add an override from openSIL/amd-edk2-platforms repo for USB mass
storage. On Gigabyte MZ33-AR1 there are lots of errors from virtual
CD-ROM from BMC. These additional resets help a bit in USB enumeration
during boot.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The timer/counter start and end value were hardcoded instead of being
read from the performance protocol.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending
coreboot always uses TSC for timestamps, force correct timer library
so measurements are accurate. A mismatch of timers will result in
incorrect tick and nanosecond calculations due to different timer
frequency.
Add a copy of BaseCpuTimerLib from UefiCpuPkg and replace TSC frequency
calculation with the value obtained from coreboot timestamp table.
On Intel systems where the UefiCpuPkg/CpuTimerLib is used, there is no
mismatch. However, AMD systems do not have the required CPUID, so the
default timer is HPET, not TSC.
TEST=Boot Gigabyte MZ33-AR1 and use systemd-analyze. The firmware boot
time is no longer 19 minutes, but indicates correct time spent in
firmware.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Do not clear testd attribute from above 4G RAM memory. It caused the
payload to mark above 4G ranges as reserved. As a result, Linux kernel
had only as much memory, as there is available memory below 4G reported
by coreboot. It caused out of memory processes kills in Linux.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending
FWTS complains on MMCONF not being reseved in memory map. So reserve
it.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending
There was a dirty hack for Intel platforms that read TOLUD register
to determine the boundary between MMIO and DRAM. It caused problems
on AMD platforms such as apu2, which does not have TOLUD register. As
a result, regions which held reserved memory were incorrectly
reported as RAM buffers or RAM itself and the OS allocated DMA there.
It could be observed with many IO_PAGE_FAULTs occurring in the OS.
See: Dasharo/dasharo-issues#1134
FWTS complains on ECAM MMCONF not being reserved in the memory map.
So carve it out of the memory map and report it as reserved.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending
Mark the range 0x1000-0xa0000 as tested. It caused the payload to mark
this range as reserved. As a result, Linux kernel could not allocate
memory for real mode and panicked.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Upstream-Status: Pending
On AMD server systems there are multiple PCI root bridges. The root
bridge scanning in UEFI Payload is not sufficient to detect the memory
and I/O apertures properly. For example, on Turin system, the I/O
aperture on the first root bridge containing the FCH may not have any
I/O resources detected on the PCI devices. This results in the I/O
decoding to be disabled on the root bridge, effectively breaking the
I/O-based serial ports, e.g. on Super I/Os and BMCs.
Populate the root bridge info from CB_TAG_RB_INFO which contains data
compatible with the Universal Payload PCI Root Bridges Info HOB. Make
the PciHostBridgeLib pick the HOB up, if available, and populate
proper root bridge apertures for AMD systems. Otherwise, fall back
to root bridge scanning.
Relevant coreboot patches:
https://review.coreboot.org/c/coreboot/+/89486https://review.coreboot.org/c/coreboot/+/89487
TEST=Boot UEFI Payload and see the serial console no longer breaks
after PCI enumeration in UEFI Payload on Gigabyte MZ33-AR1.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add a note that the `Keep IOMMU enabled(...)` option is incompatible
with Windows, making the OS unable to boot.
Signed-off-by: Filip Lewinski <filip.lewinski@3mdeb.com>
Fixes an issue where entering FUM twice in a row is prevented by the
Request variable being the same as the Active variable, being volatile
and without runtime write access.
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Checking if Boot Guard is enabled and probing the manifests had to be
adapted for the new Top Swap region-aware GetCbfs and GetFmap
Signed-off-by: Filip Lewinski <filip.lewinski@3mdeb.com>
When flashing during a capsule update, migrate the redundancy-related
Slot A - FMAP regions BOOTBLOCK and COREBOOT
Signed-off-by: Filip Lewinski <filip.lewinski@3mdeb.com>
Michał Żygowski
Michał Kopeć
Filip Lewiński
Sergii Dmytruk