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Align the DT description of the SMMU topology and stream IDs with the actual routing of the SoC. As with the preceding IORT change, this is mostly a cleanup exercise, but it does actually fix an issue with the CCP crypto accelerator on B1 silicon. Since the CCP shares its SMMU with the second SATA controller, which is only enabled on B1 silicon, we can drop the logic that disables this SMMU on B0 silicon or on platforms that do not expose any SATA ports on the second controller (such as the Cello). Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Leif Lindholm <leif.lindholm@linaro.org>