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Platform/Overdrive: clean up stream ID descriptions in DT

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Align the DT description of the SMMU topology and stream IDs with the
actual routing of the SoC. As with the preceding IORT change, this is
mostly a cleanup exercise, but it does actually fix an issue with the
CCP crypto accelerator on B1 silicon.

Since the CCP shares its SMMU with the second SATA controller, which
is only enabled on B1 silicon, we can drop the logic that disables
this SMMU on B0 silicon or on platforms that do not expose any SATA
ports on the second controller (such as the Cello).

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
2019-11-27 19:44:33 +01:00
parent ff5e2c5c4c
commit 7a1cd6efbb
2 changed files with 18 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
Platform/AMD/OverdriveBoard/DeviceTree/OverdriveBoard.dts
View File

@@ -86,7 +86,7 @@
*/
<0 332 4>,
<0 332 4>;
#iommu-cells = <2>;
#iommu-cells = <1>;
dma-coherent;
};
@@ -99,7 +99,7 @@
*/
<0 331 4>,
<0 331 4>;
#iommu-cells = <2>;
#iommu-cells = <1>;
dma-coherent;
};
@@ -109,7 +109,12 @@
interrupts = <0x0 0x163 0x4>;
clocks = <&sata_clk>;
dma-coherent;
iommus = <&sata0_smmu 0x00 0x1f>; /* 0-31 */
iommus = <&sata0_smmu 0x0a>,
<&sata0_smmu 0x0b>,
<&sata0_smmu 0x0e>,
<&sata0_smmu 0x0f>,
<&sata0_smmu 0x1a>,
<&sata0_smmu 0x1e>;
};
sata@e0d00000 {
@@ -119,7 +124,9 @@
interrupts = <0x0 0x162 0x4>;
clocks = <&sata_clk>;
dma-coherent;
iommus = <&sata1_smmu 0x00 0x1f>; /* 0-31 */
iommus = <&sata1_smmu 0x0e>,
<&sata1_smmu 0x0f>,
<&sata1_smmu 0x1e>;
};
i2c@e1000000 {
@@ -233,6 +240,10 @@
interrupts = <0x0 0x3 0x4>;
dma-coherent;
amd,zlib-support = <0x1>;
iommus = <&sata1_smmu 0x00>,
<&sata1_smmu 0x02>,
<&sata1_smmu 0x40>,
<&sata1_smmu 0x42>;
};
pcie: pcie@f0000000 {
@@ -409,7 +420,7 @@
phy-handle = <&xgmac0_phy>;
phy-mode = "xgmii";
dma-coherent;
iommus = <&xgmac0_smmu 0x00 0x1f>; /* 0-31 */
iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
};
xgmac@e0900000 {
@@ -428,7 +439,7 @@
phy-handle = <&xgmac1_phy>;
phy-mode = "xgmii";
dma-coherent;
iommus = <&xgmac1_smmu 0x00 0x1f>; /* 0-31 */
iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
};
};

6
Silicon/AMD/Styx/Library/StyxDtbLoaderLib/StyxDtbLoaderLib.c
View File

@@ -212,8 +212,6 @@ DisableSmmu (
Node = fdt_path_offset (Fdt, SmmuNodeName);
if (Node <= 0) {
DEBUG ((DEBUG_WARN, "%a: Failed to find path %s: %a\n",
__FUNCTION__, SmmuNodeName, fdt_strerror (Node)));
return;
}
@@ -251,9 +249,7 @@ SetSocIdStatus (
if (!PcdGetBool (PcdEnableSmmus)) {
DisableSmmu (Fdt, "iommu-map", "/smb/smmu@e0a00000", "/smb/pcie@f0000000");
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0200000", "/smb/sata@e0300000");
}
if (!PcdGetBool (PcdEnableSmmus) || !IsRevB1 || FixedPcdGet8 (PcdSata1PortCount) == 0) {
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/ccp@e0100000");
DisableSmmu (Fdt, "iommus", "/smb/smmu@e0c00000", "/smb/sata@e0d00000");
}