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WhitleyOpenBoardPkg/AcpiTablesLib: Add library for AcpiPlatform driver
AcpiTablesLib allows for board specific updates to ACPI tables. Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Signed-off-by: Isaac Oram <isaac.w.oram@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Isaac Oram
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## @file
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# Library functions for ACPI Table Update library.
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#
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# @copyright
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# Copyright 2015 - 2020 Intel Corporation. <BR>
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#
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# SPDX-License-Identifier: BSD-2-Clause-Patent
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##
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################################################################################
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#
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# Defines Section - statements that will be processed to create a Makefile.
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#
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################################################################################
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[Defines]
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INF_VERSION = 0x00010005
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BASE_NAME = AcpiPlatformTableLib
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FILE_GUID = 09114814-BF6D-4B2D-BD61-C1F0668DE06E
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MODULE_TYPE = BASE
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VERSION_STRING = 1.0
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LIBRARY_CLASS = AcpiPlatformTableLib
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CONSTRUCTOR = AcpiPlatformLibConstructor
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#
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# The following information is for reference only and not required by the build tools.
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#
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# VALID_ARCHITECTURES = X64
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#
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################################################################################
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#
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# Sources Section - list of files that are required for the build to succeed.
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#
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################################################################################
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[Sources]
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AcpiPlatformLibApic.c
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AcpiPlatformLibBdat.c
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AcpiPlatformLibDsdt.c
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AcpiPlatformLibFadt.c
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AcpiPlatformLibMcfg.c
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AcpiPlatformLibMsct.c
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AcpiPlatformLib.c
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AcpiPlatformLibLocal.h
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AcpiPlatformLibNfit.c
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AcpiPlatformLibPcat.c
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AcpiPlatformLibSlit.c
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AcpiPlatformLibSrat.c
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AcpiPlatformLibSsdt.c
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AcpiPlatformLibMigt.c
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AcpiPlatformLibPmtt.c
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AcpiPlatformLibHmat.c
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################################################################################
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#
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# Package Dependency Section - list of Package files that are required for
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# this module.
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#
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################################################################################
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[Packages]
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MdePkg/MdePkg.dec
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MdeModulePkg/MdeModulePkg.dec
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UefiCpuPkg/UefiCpuPkg.dec
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WhitleyOpenBoardPkg/PlatformPkg.dec
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WhitleySiliconPkg/SiliconPkg.dec
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WhitleySiliconPkg/CpRcPkg.dec
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WhitleySiliconPkg/Cpu/CpuRcPkg.dec
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WhitleySiliconPkg/WhitleySiliconPkg.dec
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[LibraryClasses]
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BaseLib
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DebugLib
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PcdLib
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MemoryAllocationLib
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BuildAcpiTablesLib
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CrcLib
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UbaPlatLib
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PlatformSpecificAcpiTableLib
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CompressDxeLib
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UefiDecompressLib
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[Protocols]
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gDxePchPlatformPolicyProtocolGuid
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gEfiNfitTableUpdateProtocolGuid
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gSmbiosMemInfoProtocolGuid
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gAcpiPlatformProtocolGuid
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gEfiSmbiosProtocolGuid
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gEfiCpuCsrAccessGuid
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gDynamicSiLibraryProtocolGuid ## CONSUMES
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gDynamicSiLibraryProtocol2Guid ## CONSUMES
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[Guids]
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gEfiPlatformInfoGuid
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gFpgaSocketVariableGuid
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gEwlBdatSchemaGuid
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gSpdBdatSchemaGuid
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gSpdVersion1Guid
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gSpdVariableGuid
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gMemTrainingDataBdatSchemaGuid
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gMemTrainingDataVersion1Guid
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gMemTrainingDataHobGuid
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[Pcd]
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
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gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
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gPlatformTokenSpaceGuid.ReservedB
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gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
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gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
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gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiTable
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gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiBdatTable
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gPlatformModuleTokenSpaceGuid.PcdWsmtProtectionFlags
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gPlatformTokenSpaceGuid.PcdHalfWidth
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gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer ## CONSUMES
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[FixedPcd]
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gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
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gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount
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gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuThreadCount
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gEfiCpRcPkgTokenSpaceGuid.SaveSpdToBdat
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gEfiCpRcPkgTokenSpaceGuid.SaveMrcTrainingDataToBdat
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[Depex]
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gDynamicSiLibraryProtocolGuid AND
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gDynamicSiLibraryProtocol2Guid
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/** @file
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ACPI Platform Driver Hooks
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@copyright
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Copyright 1996 - 2018 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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//
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// Statements that include other files
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//
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#include "AcpiPlatformLibLocal.h"
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#include <Library/PchPcieRpLib.h>
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extern UINT8 mKBPresent;
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extern UINT8 mMousePresent;
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extern SOCKET_PROCESSORCORE_CONFIGURATION mSocketProcessorCoreConfiguration;
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extern SOCKET_POWERMANAGEMENT_CONFIGURATION mSocketPowermanagementConfiguration;
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EFI_STATUS
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PatchFadtTable (
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IN OUT EFI_ACPI_COMMON_HEADER *Table
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)
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{
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UINT16 LegacyDevice;
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EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader;
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EFI_STATUS Status;
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UINT8 PcieGlobalAspm;
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Status = GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF(SOCKET_IIO_CONFIGURATION, PcieGlobalAspm), &PcieGlobalAspm, sizeof(UINT8));
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if (EFI_ERROR (Status)) {
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PcieGlobalAspm = 0x2;
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}
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//
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// Patch FADT for legacy free
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//
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LegacyDevice = 0;
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FadtHeader = (EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
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//
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// Control of setting ASPM disabled bit in FADT
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//
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switch (mSocketPowermanagementConfiguration.NativeAspmEnable) {
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case 0:
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LegacyDevice |= (1 << 4);
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break;
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case 1:
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LegacyDevice &= ~(1 << 4);
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break;
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case 2:
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if (PcieGlobalAspm == 0) {
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LegacyDevice |= (1 << 4);
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} else {
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LegacyDevice &= ~(1 << 4);
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}
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break;
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default:
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LegacyDevice &= ~(1 << 4);
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DEBUG ((DEBUG_ERROR, "\n Native ASPM = %d is not valid (expected values are 0, 1, 2). \n", mSocketPowermanagementConfiguration.NativeAspmEnable ));
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ASSERT (0);
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break;
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}
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FadtHeader->IaPcBootArch = LegacyDevice;
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FadtHeader->Flags |= (mSocketProcessorCoreConfiguration.ForcePhysicalModeEnable) ? EFI_ACPI_6_2_FORCE_APIC_PHYSICAL_DESTINATION_MODE : 0;
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return EFI_SUCCESS;
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}
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/** @file
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@copyright
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Copyright 1999 - 2020 Intel Corporation. <BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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#ifndef _ACPI_PLATFORM__LIB_LOCAL_H_
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#define _ACPI_PLATFORM__LIB_LOCAL_H_
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//
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// Statements that include other header files
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//
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#include <Library/PcdLib.h>
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#include <Library/IoLib.h>
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#include <Library/BaseMemoryLib.h>
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#include <Library/AcpiPlatformLib.h>
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#include <Library/CpuConfigLib.h>
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#include <Library/DevicePathLib.h>
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#include <Library/SetupLib.h>
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#include <Library/MemoryAllocationLib.h>
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#include <Library/BuildAcpiTablesLib.h>
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#include <Guid/PlatformInfo.h>
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#include <Guid/MemoryMapData.h>
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#include <Guid/GlobalVariable.h>
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#include <Protocol/AcpiTable.h>
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#include <Protocol/Smbios.h>
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#include <Protocol/SuperIo.h>
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#include <Protocol/NfitTableUpdateProtocol.h>
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#include <DataTypes.h>
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#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
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#include <IndustryStandard/HighPrecisionEventTimerTable.h>
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#include <IioRegs.h>
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#include <Platform.h>
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#include <Protocol/GlobalNvsArea.h>
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#include <Protocol/IioUds.h>
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#include <SystemBoard.h>
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#include <Protocol/SerialIo.h>
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#include <Protocol/DevicePath.h>
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#include <Register/ArchitecturalMsr.h>
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#include <PpmPolicyPeiDxeCommon.h>
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#include <Acpi/Bdat.h>
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#include <Acpi/Hpet.h>
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#include <Acpi/Mcfg.h>
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#include <Acpi/Msct.h>
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#include <Acpi/Slit.h>
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#include <Acpi/Srat.h>
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#include <Acpi/Migt.h>
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#include <Acpi/Nfit.h>
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#include <Acpi/Pcat.h>
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#include <Acpi/Pmtt.h>
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#include <Acpi/Hmat.h>
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#include <Acpi/Wsmt.h>
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#include <Acpi/amlresrc.h> // came from https://acpica.org/downloads/source_code.php acpica-win-20130214.zip/source/include
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#include <IndustryStandard/AcpiAml.h>
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#include <Guid/SocketMpLinkVariable.h>
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#include <Guid/SocketIioVariable.h>
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#include <Guid/SocketPowermanagementVariable.h>
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#include <Guid/SocketCommonRcVariable.h>
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#include <Guid/FpgaSocketVariable.h>
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#include <Fpga.h>
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#include <Register/Cpuid.h>
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#include <Protocol/DynamicSiLibraryProtocol.h>
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#include <Protocol/DynamicSiLibraryProtocol2.h>
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#include <Upi/KtiHost.h>
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#define OEM1_SSDT_TABLE_SIGNATURE SIGNATURE_32('O', 'E', 'M', '1')
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#define OEM2_SSDT_TABLE_SIGNATURE SIGNATURE_32('O', 'E', 'M', '2')
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#define OEM3_SSDT_TABLE_SIGNATURE SIGNATURE_32('O', 'E', 'M', '3')
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#define OEM4_SSDT_TABLE_SIGNATURE SIGNATURE_32('O', 'E', 'M', '4')
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#define AML_NAME_OP 0x08
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#define AML_NAME_PREFIX_SIZE 0x06
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#define AML_NAME_DWORD_SIZE 0x0C
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#ifndef AML_EXTERNAL_OP
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#define AML_EXTERNAL_OP 0x15 /* ACPI 6.0 */
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#endif
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#define GPSS_FVID_MAX_STATES 40 // Greater Than 16 p-state support
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//
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// mCpuPCPSInfo usage
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//
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#define B_PCPS_DISABLE (1 << 17) // Bit 17
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#define B_PCPS_HT_ENABLE (1 << 16) // Bit 16
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#define PCIE_BUS_0 0x00
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#define PCIE_BUS_1 0x01
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#define PCIE_BUS_2 0x02
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#define PCIE_BUS_3 0x03
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#define PCIE_BUS_4 0x04
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#define PCIE_BUS_5 0x05
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#define PCIE_PORT_ALL_FUNC 0x00
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#define PCIE_PORT_0_DEV 0x00
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#define PCIE_PORT_1A_DEV 0x00
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#define PCIE_PORT_1B_DEV 0x01
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#define PCIE_PORT_1C_DEV 0x02
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#define PCIE_PORT_1D_DEV 0x03
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#define PCIE_PORT_2A_DEV 0x00
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#define PCIE_PORT_2B_DEV 0x01
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#define PCIE_PORT_2C_DEV 0x02
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#define PCIE_PORT_2D_DEV 0x03
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#define PCIE_PORT_3A_DEV 0x00
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#define PCIE_PORT_3B_DEV 0x01
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#define PCIE_PORT_3C_DEV 0x02
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#define PCIE_PORT_3D_DEV 0x03
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#define PCIE_PORT_4A_DEV 0x00
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#define PCIE_PORT_4B_DEV 0x01
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#define PCIE_PORT_4C_DEV 0x02
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#define PCIE_PORT_4D_DEV 0x03
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#define PCIE_PORT_5_DEV 0x00
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#define MAX_IO_APICS_10NM 1
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//
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// Define flag bits
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//
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#define POLARITY_ACTIVE_HIGH 0x01
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#define POLARITY_ACTIVE_LOW 0x03
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#define TRIGGERMODE_EDGE 0x04
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#define TRIGGERMODE_LEVEL 0x0C
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#pragma pack(1)
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typedef struct {
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UINT32 AcpiProcessorId;
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UINT32 ApicId;
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UINT32 Flags;
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UINT32 SocketNum;
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} CPU_ID_ORDER_MAP;
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typedef struct {
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UINT8 AcpiProcessorId;
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UINT8 ApicId;
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UINT16 Flags;
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} CPU_ID_MAP;
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typedef struct {
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UINT8 StartByte;
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UINT32 NameStr;
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UINT8 Size;
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UINT32 Value;
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} ACPI_NAMEPACK_DWORD;
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typedef struct {
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UINT8 StartByte;
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UINT32 NameStr;
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UINT8 OpCode;
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UINT16 Size; // Hardcode to 16bit width because the table we use is fixed size
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UINT8 NumEntries;
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} ACPI_NAME_COMMAND;
|
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|
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typedef struct {
|
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UINT8 PackageOp;
|
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UINT8 PkgLeadByte;
|
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UINT8 NumEntries;
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UINT8 DwordPrefix0;
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UINT32 CoreFreq;
|
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UINT8 DwordPrefix1;
|
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UINT32 Power;
|
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UINT8 DwordPrefix2;
|
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UINT32 TransLatency;
|
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UINT8 DwordPrefix3;
|
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UINT32 BMLatency;
|
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UINT8 DwordPrefix4;
|
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UINT32 Control;
|
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UINT8 DwordPrefix5;
|
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UINT32 Status;
|
||||
} PSS_PACKAGE;
|
||||
|
||||
typedef struct {
|
||||
UINT8 NameOp; // 08h ;First opcode is a NameOp.
|
||||
UINT32 PackageName; // PSDC/PSDE
|
||||
UINT8 Length;
|
||||
UINT8 DwordPrefix1;
|
||||
UINT8 Revision;
|
||||
UINT8 PackageOp;
|
||||
UINT8 PackageLen;
|
||||
UINT8 PackLen;
|
||||
UINT16 WordValue1;
|
||||
UINT16 WordValue2;
|
||||
UINT8 BytePrefix2;
|
||||
UINT32 Domain;
|
||||
UINT8 BytePrefix3;
|
||||
UINT8 CoordType; // 0xFC(SW_ALL), 0xFE(HW_ALL)
|
||||
UINT8 BytePrefix4;
|
||||
UINT32 NumProcessors;
|
||||
} PSD_PACKAGE_LAYOUT;
|
||||
|
||||
struct CpcRegPack {
|
||||
UINT8 ResourceOp; // 11h
|
||||
UINT8 Length; // 14h
|
||||
UINT32 FFixedHW;
|
||||
UINT32 RegisterBitsUsage;
|
||||
UINT32 RegisterBitsShift;
|
||||
UINT32 RegisterOffset;
|
||||
UINT32 RegisterByteSize;
|
||||
};
|
||||
|
||||
typedef struct {
|
||||
UINT8 ExternalOp;
|
||||
UINT8 RootChar;
|
||||
UINT8 MultiNamePrefix;
|
||||
UINT8 SegCount;
|
||||
UINT32 NameStr[0];
|
||||
} EXTERNAL_OBJECT_DECL;
|
||||
|
||||
#define ACPI_NAME_COMMAND_FROM_NAME_STR(a) BASE_CR (a, ACPI_NAME_COMMAND, NameStr)
|
||||
#define ACPI_NAME_COMMAND_FROM_NAMEPACK_STR(a) BASE_CR (a, ACPI_NAMEPACK_DWORD, NameStr)
|
||||
#define ACPI_EXTERNAL_OBJECT_DECL_FROM_NAME_STR(a) BASE_CR (a, EXTERNAL_OBJECT_DECL, NameStr)
|
||||
|
||||
//
|
||||
// Private Driver Data
|
||||
//
|
||||
//
|
||||
// Define Union of IO APIC & Local APIC structure;
|
||||
//
|
||||
typedef union {
|
||||
EFI_ACPI_6_2_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
|
||||
EFI_ACPI_6_2_IO_APIC_STRUCTURE AcpiIoApic;
|
||||
EFI_ACPI_6_2_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
|
||||
struct {
|
||||
UINT8 Type;
|
||||
UINT8 Length;
|
||||
} AcpiApicCommon;
|
||||
} ACPI_APIC_STRUCTURE_PTR;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
EFI_STATUS
|
||||
PatchBdatAcpiTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
/**
|
||||
Build from scratch and install the MADT.
|
||||
|
||||
@retval EFI_SUCCESS The MADT was installed successfully.
|
||||
@retval EFI_OUT_OF_RESOURCES Could not allocate required structures.
|
||||
**/
|
||||
EFI_STATUS
|
||||
InstallMadtFromScratch (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
InstallSratTable (
|
||||
VOID
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchFadtTable(
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchDsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchMcfgAcpiTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchSLitTable(
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
InstallSlitTable(
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Finds the Proximity Domain which the element in the Memory Map belongs to.
|
||||
|
||||
@param [in] SocketId SocketId which the element belongs to.
|
||||
@param [in] MemType MemType of the element.
|
||||
@param [in] SncEnabled Bit to indicate if SNC is enabled in the setup options.
|
||||
@param [in] ImcInterBitmap IMC interleave bitmap for this element.
|
||||
@param [in] MemMode Current memory mode. 1LM, 2LM etc.
|
||||
@param [in] LastDomainId Last Domain ID.
|
||||
|
||||
@retval Proximity Domain.
|
||||
|
||||
**/
|
||||
UINT32
|
||||
ProximityDomainOf (
|
||||
UINT8 SocketId,
|
||||
UINT16 MemType,
|
||||
UINT8 MaxEnabledImc,
|
||||
UINT8 SncEnabled,
|
||||
UINT8 SncNumOfCluster,
|
||||
UINT8 ImcInterBitmap,
|
||||
UINT8 MemMode,
|
||||
UINT32 LastDomainId
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchSratTable (
|
||||
IN OUT STATIC_RESOURCE_AFFINITY_TABLE *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchSsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table,
|
||||
IN OUT EFI_ACPI_TABLE_VERSION *Version
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchCpuPmSsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchOem1SsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchOem2SsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchOem3SsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
PatchOem4SsdtTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
UpdateNfitTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
EFI_STATUS
|
||||
UpdatePcatTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
);
|
||||
|
||||
/**
|
||||
Detect the APICID map and initialize the module global pointer.
|
||||
**/
|
||||
VOID
|
||||
DetectApicIdMap (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Sort CPU Local APIC Information.
|
||||
|
||||
This function gets the CPU local APIC information from the MP service
|
||||
protocol into the local table structure, and sorts it based on APIC ID.
|
||||
|
||||
@retval EFI_SUCCESS Local APIC information was successfully sorted.
|
||||
**/
|
||||
EFI_STATUS
|
||||
SortCpuLocalApicInTable (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Get the socket logical index.
|
||||
|
||||
This function convert the socket physical index to logical index (0 based).
|
||||
If the specified physical socket is not enabled, an invalid logical index 0xff
|
||||
will be returned. The socket physical index and logical index will be the same
|
||||
if the indexes of enabled sockets are continuous.
|
||||
|
||||
@param[in] SocketPhysicalId Socket physical index.
|
||||
|
||||
@retval Socket logical index.
|
||||
**/
|
||||
UINT8
|
||||
GetSocketLogicalId (
|
||||
IN UINT8 SocketPhysicalId
|
||||
);
|
||||
|
||||
/**
|
||||
Get the socket physical index.
|
||||
|
||||
This function convert the socket logical index to physical index (0 based).
|
||||
If the specified logical socket does not exist, an invalid physical index 0xff
|
||||
will be returned. The socket physical index and logical index will be the same
|
||||
if the indexes of enabled sockets are continuous.
|
||||
|
||||
@param[in] SocketLogicalId Socket logical index.
|
||||
|
||||
@retval Socket physical index.
|
||||
**/
|
||||
UINT8
|
||||
GetSocketPhysicalId (
|
||||
IN UINT8 SocketlogicId
|
||||
);
|
||||
|
||||
/**
|
||||
Verifies whether sockets are linked
|
||||
|
||||
@param[in] SourceSocket Source Socket ID
|
||||
@param[in] TargetSocket Targer Socket ID
|
||||
|
||||
@retval TRUE link between source socket and target socket was found
|
||||
FALSE otherwise
|
||||
|
||||
**/
|
||||
BOOLEAN
|
||||
SocketsLinked (
|
||||
IN UINT32 SourceSocket,
|
||||
IN UINT32 TargetSocket
|
||||
);
|
||||
|
||||
//
|
||||
// AcpiPlatformTableLib private share
|
||||
//
|
||||
extern EFI_MP_SERVICES_PROTOCOL *mMpService;
|
||||
extern BOOLEAN mCpuOrderSorted;
|
||||
extern CPU_ID_ORDER_MAP mCpuApicIdOrderTable[];
|
||||
extern UINTN mNumberOfCPUs;
|
||||
extern UINTN mNumberOfEnabledCPUs;
|
||||
extern AML_OFFSET_TABLE_ENTRY *mAmlOffsetTablePointer;
|
||||
extern CPU_CONFIG_CONTEXT_BUFFER *mCpuConfigLibConfigContextBuffer;
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,134 @@
|
||||
/** @file
|
||||
ACPI Platform Driver Hooks
|
||||
|
||||
@copyright
|
||||
Copyright 1996 - 2015 Intel Corporation. <BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiPlatformLibLocal.h"
|
||||
|
||||
|
||||
extern BIOS_ACPI_PARAM *mAcpiParameter;
|
||||
extern EFI_IIO_UDS_PROTOCOL *mIioUds;
|
||||
extern CPU_CSR_ACCESS_VAR *mCpuCsrAccessVarPtr;
|
||||
extern SYSTEM_CONFIGURATION mSystemConfiguration;
|
||||
|
||||
EFI_STATUS
|
||||
PatchMcfgAcpiTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
)
|
||||
{
|
||||
UINT8 NodeId;
|
||||
UINT8 NodeCount;
|
||||
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE *McfgTable;
|
||||
|
||||
McfgTable = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE *)Table;
|
||||
|
||||
//
|
||||
// mAcpiParameter memory buffer has been zero'ed out, so mAcpiParameter->PcieSegNum[] are 0's
|
||||
// Patch \_SB.PSYS.SGEN with User Setup Option data
|
||||
//
|
||||
//
|
||||
// dynamically allow multi-seg support
|
||||
//
|
||||
mAcpiParameter->PcieMultiSegSupport = 0;
|
||||
for (NodeId = 0; NodeId < MAX_SOCKET; NodeId++) {
|
||||
if ((UINT16) (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[NodeId].PcieSegment) > 0) {
|
||||
mAcpiParameter->PcieMultiSegSupport = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Update MCFG table entries (segment number, base addr and start/end bus numbers)
|
||||
//
|
||||
if (mAcpiParameter->PcieMultiSegSupport == 0) {
|
||||
|
||||
//
|
||||
// Original code for single PCIe segment start
|
||||
//
|
||||
McfgTable->Segment[0].BaseAddress = mIioUds->IioUdsPtr->PlatformData.PciExpressBase;
|
||||
McfgTable->Segment[0].EndBusNumber = (UINT8)RShiftU64 (mIioUds->IioUdsPtr->PlatformData.PciExpressSize, 20) - 1;
|
||||
//
|
||||
// Original code for single PCIe segment end
|
||||
//
|
||||
|
||||
//
|
||||
// Single segment with segment number as 0
|
||||
//
|
||||
McfgTable->Segment[0].PciSegmentGroupNumber = 0;
|
||||
NodeCount = 1;
|
||||
|
||||
} else {
|
||||
//
|
||||
// PCIe Multi-Segment handling - Assume each CPU socket as a segment, and copy Segement info from IioUds HOB to MCFG table entries
|
||||
//
|
||||
|
||||
//
|
||||
// Segment count = 0
|
||||
//
|
||||
NodeCount = 0;
|
||||
|
||||
for (NodeId = 0; NodeId < MAX_SOCKET; NodeId++) {
|
||||
|
||||
//
|
||||
// Skip a socket if it does not exist or does not contain valid bus range data
|
||||
//
|
||||
if ( (UINT8)(mCpuCsrAccessVarPtr->SocketLastBus[NodeId]) ==
|
||||
(UINT8)(mCpuCsrAccessVarPtr->SocketFirstBus[NodeId]) ) {
|
||||
continue;
|
||||
}
|
||||
|
||||
//
|
||||
// Copy PCIe Segement info from IioUds HOB to MCFG table entries
|
||||
//
|
||||
McfgTable->Segment[NodeCount].PciSegmentGroupNumber = (UINT16)(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[NodeId].PcieSegment);
|
||||
|
||||
McfgTable->Segment[NodeCount].BaseAddress = \
|
||||
LShiftU64 (mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[NodeId].SegMmcfgBase.hi, 32) + \
|
||||
(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[NodeId].SegMmcfgBase.lo);
|
||||
|
||||
McfgTable->Segment[NodeCount].StartBusNumber = (UINT8)(mCpuCsrAccessVarPtr->SocketFirstBus[NodeId]);
|
||||
|
||||
McfgTable->Segment[NodeCount].EndBusNumber = (UINT8)(mCpuCsrAccessVarPtr->SocketLastBus[NodeId]);
|
||||
|
||||
//
|
||||
// Update segment number returned by AML _SEG() . It resides in mAcpiParameter region now.
|
||||
//
|
||||
mAcpiParameter->PcieSegNum[NodeId] = (UINT8)(mIioUds->IioUdsPtr->PlatformData.CpuQpiInfo[NodeId].PcieSegment);
|
||||
|
||||
//
|
||||
// Update count of valid segments
|
||||
//
|
||||
NodeCount++;
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Set MCFG table "Length" field based on the number of PCIe segments enumerated so far
|
||||
//
|
||||
McfgTable->Header.Header.Length = \
|
||||
sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) + \
|
||||
sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE) * NodeCount;
|
||||
|
||||
//
|
||||
// Debug dump of MCFG table
|
||||
//
|
||||
DEBUG ((DEBUG_ERROR, "ACPI MCFG table @ address 0x%x\n", Table ));
|
||||
DEBUG ((DEBUG_ERROR, " Multi-Seg Support = %x\n", mAcpiParameter->PcieMultiSegSupport));
|
||||
DEBUG ((DEBUG_ERROR, " Number of Segments (sockets): %2d\n", NodeCount ));
|
||||
DEBUG ((DEBUG_ERROR, " Table Length = 0x%x\n\n", McfgTable->Header.Header.Length ));
|
||||
for (NodeId = 0; NodeId < NodeCount; NodeId ++) {
|
||||
DEBUG ((DEBUG_ERROR, " Segment[%2d].BaseAddress = %x\n", NodeId, McfgTable->Segment[NodeId].BaseAddress));
|
||||
DEBUG ((DEBUG_ERROR, " Segment[%2d].PciSegmentGroupNumber = %x\n", NodeId, McfgTable->Segment[NodeId].PciSegmentGroupNumber));
|
||||
DEBUG ((DEBUG_ERROR, " Segment[%2d].StartBusNumber = %x\n", NodeId, McfgTable->Segment[NodeId].StartBusNumber));
|
||||
DEBUG ((DEBUG_ERROR, " Segment[%2d].EndBusNumber = %x\n\n", NodeId, McfgTable->Segment[NodeId].EndBusNumber));
|
||||
}
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,69 @@
|
||||
/** @file
|
||||
ACPI Platform Driver Hooks
|
||||
|
||||
@copyright
|
||||
Copyright 1996 - 2018 Intel Corporation. <BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiPlatformLibLocal.h"
|
||||
|
||||
extern BIOS_ACPI_PARAM *mAcpiParameter;
|
||||
|
||||
/**
|
||||
Update the MIGT ACPI table
|
||||
|
||||
@param *TableHeader - The table to be set
|
||||
|
||||
@retval EFI_SUCCESS - Returns Success
|
||||
**/
|
||||
EFI_STATUS
|
||||
PatchMigtAcpiTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
UINT64 Address;
|
||||
UINTN idx;
|
||||
UINT8 checksum;
|
||||
EFI_MIGT_ACPI_DESCRIPTION_TABLE *MigtAcpiTable;
|
||||
|
||||
MigtAcpiTable = (EFI_MIGT_ACPI_DESCRIPTION_TABLE *)Table;
|
||||
Address = 0xffffffff;
|
||||
|
||||
Status = gBS->AllocatePages (
|
||||
AllocateMaxAddress,
|
||||
EfiACPIMemoryNVS,
|
||||
1, //page
|
||||
&Address
|
||||
);
|
||||
|
||||
if (EFI_ERROR (Status)) {
|
||||
return Status;
|
||||
}
|
||||
//
|
||||
// update MIGT ACPI table
|
||||
//
|
||||
MigtAcpiTable->ActionRegion.Address = Address;
|
||||
|
||||
//
|
||||
// update checksum
|
||||
//
|
||||
MigtAcpiTable->Header.Checksum = 0;
|
||||
checksum = 0;
|
||||
for(idx = 0; idx < sizeof(EFI_MIGT_ACPI_DESCRIPTION_TABLE); idx++) {
|
||||
checksum = checksum + (UINT8) (((UINT8 *)(MigtAcpiTable))[idx]);
|
||||
}
|
||||
MigtAcpiTable->Header.Checksum = (UINT8) (0 - checksum);
|
||||
|
||||
//
|
||||
// Update Migration Action Region GAS address
|
||||
//
|
||||
mAcpiParameter->MigrationActionRegionAddress = Address;
|
||||
|
||||
return Status;
|
||||
}
|
||||
@@ -0,0 +1,101 @@
|
||||
/** @file
|
||||
ACPI Platform Driver Hooks
|
||||
|
||||
@copyright
|
||||
Copyright 1996 - 2020 Intel Corporation. <BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiPlatformLibLocal.h"
|
||||
|
||||
/**
|
||||
Update the MSCT ACPI table
|
||||
|
||||
@param *MsctAcpiTable - The table to be set
|
||||
|
||||
@retval EFI_SUCCESS - Returns Success
|
||||
**/
|
||||
EFI_STATUS
|
||||
PatchMsctAcpiTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
)
|
||||
{
|
||||
UINTN idx;
|
||||
UINT8 checksum;
|
||||
UINT32 MaxPhysicalAddressBit;
|
||||
EFI_CPUID_REGISTER CpuidLeafInfo;
|
||||
EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE *MsctAcpiTable = NULL;
|
||||
UINT32 MaxThreadCapacity;
|
||||
UINT32 MaxSocketCount;
|
||||
EFI_STATUS Status = EFI_SUCCESS;
|
||||
DYNAMIC_SI_LIBARY_PROTOCOL2 *DynamicSiLibraryProtocol2 = NULL;
|
||||
|
||||
Status = gBS->LocateProtocol (&gDynamicSiLibraryProtocol2Guid, NULL, &DynamicSiLibraryProtocol2);
|
||||
if (EFI_ERROR (Status)) {
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
return Status;
|
||||
}
|
||||
|
||||
MsctAcpiTable = (EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE *)Table;
|
||||
|
||||
//
|
||||
// If SNC is enabled set the Maximum number of Proximity domains accordingly
|
||||
//
|
||||
MaxSocketCount = FixedPcdGet32 (PcdMaxCpuSocketCount);
|
||||
|
||||
if (DynamicSiLibraryProtocol2->GetNumOfClusterPerSystem () != 0) {
|
||||
MsctAcpiTable->MaxNumProxDom = MaxSocketCount * DynamicSiLibraryProtocol2->GetNumOfClusterPerSystem () - 1;
|
||||
}
|
||||
|
||||
//
|
||||
// Update Maximum Physical Address
|
||||
// Get the number of address lines; Maximum Physical Address is 2^MaxPhysicalAddressBit - 1.
|
||||
// If CPUID does not support reporting the max physical address, then use a max value of 36 as per SDM 3A, 4.1.4.
|
||||
//
|
||||
AsmCpuid (CPUID_EXTENDED_FUNCTION, &CpuidLeafInfo.RegEax, NULL, NULL, NULL);
|
||||
MaxPhysicalAddressBit = 36;
|
||||
if (CpuidLeafInfo.RegEax >= (UINT32) CPUID_VIR_PHY_ADDRESS_SIZE) {
|
||||
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &CpuidLeafInfo.RegEax, NULL, NULL, NULL);
|
||||
MaxPhysicalAddressBit = (UINT8) CpuidLeafInfo.RegEax;
|
||||
}
|
||||
|
||||
MsctAcpiTable->MaxPhysicalAddress = (LShiftU64 (0x01, MaxPhysicalAddressBit) - 1);
|
||||
|
||||
MaxPhysicalAddressBit = DynamicSiLibraryProtocol2->GetMaxPhysicalAddrBits ();
|
||||
|
||||
MsctAcpiTable->MaxPhysicalAddress = (LShiftU64 (0x01, MaxPhysicalAddressBit) - 1);
|
||||
|
||||
//
|
||||
// First Proximity Domain Information Structure reports characteristics for all proximity domains,
|
||||
// since the characteristics are the same for all proximity domains.
|
||||
//
|
||||
MsctAcpiTable->ProxDomInfoStructure[0].ProxDomRangeLow = 0;
|
||||
MsctAcpiTable->ProxDomInfoStructure[0].ProxDomRangeHigh = MsctAcpiTable->MaxNumProxDom;
|
||||
|
||||
//
|
||||
// Max Number of Threads that the processor can have MaxThreadCapacity
|
||||
//
|
||||
AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, NULL, &MaxThreadCapacity, NULL, NULL);
|
||||
MsctAcpiTable->ProxDomInfoStructure[0].MaxProcessorCapacity = MaxThreadCapacity;
|
||||
|
||||
//
|
||||
// Max Memory capacity per proximity domain
|
||||
//
|
||||
MsctAcpiTable->ProxDomInfoStructure[0].MaxMemoryCapacity = MsctAcpiTable->MaxPhysicalAddress;
|
||||
|
||||
//
|
||||
// Update Checksum
|
||||
//
|
||||
MsctAcpiTable->Header.Checksum = 0;
|
||||
checksum = 0;
|
||||
for(idx = 0; idx < sizeof(EFI_ACPI_MAXIMUM_SYSTEM_CHARACTERISTICS_TABLE); idx++) {
|
||||
checksum = checksum + (UINT8) (((UINT8 *)(MsctAcpiTable))[idx]);
|
||||
}
|
||||
MsctAcpiTable->Header.Checksum = (UINT8) (0 - checksum);
|
||||
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,45 @@
|
||||
/** @file
|
||||
ACPI Platform Driver Hooks
|
||||
|
||||
@copyright
|
||||
Copyright 1996 - 2019 Intel Corporation. <BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiPlatformLibLocal.h"
|
||||
|
||||
/**
|
||||
This function locates the CrystalRidge protocol and JedecNvdimm protocol
|
||||
and calls the update ACPI tables functions defined there to update/build
|
||||
the NVDIMM F/W Interface Table (NFIT). It builds the NFIT table which gets
|
||||
published in ACPI XSDT.
|
||||
|
||||
@param[in,out] Table Pointer to NFIT which will be build in
|
||||
CR Protocol and will be publised in ACPI XSDT.
|
||||
|
||||
@retval EFI_SUCCESS Table successfully updated.
|
||||
@retval EFI_UNSUPPORTED Table not updated.
|
||||
**/
|
||||
EFI_STATUS
|
||||
UpdateNfitTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
)
|
||||
{
|
||||
EFI_NFIT_TABLE_UPDATE_PROTOCOL *NfitTableUpdateProtocol = NULL;
|
||||
EFI_STATUS Status;
|
||||
|
||||
Status = gBS->LocateProtocol (&gEfiNfitTableUpdateProtocolGuid, NULL, &NfitTableUpdateProtocol);
|
||||
|
||||
if (!EFI_ERROR (Status)) {
|
||||
Status = NfitTableUpdateProtocol->UpdateAcpiTable ((UINT64*) Table);
|
||||
} else {
|
||||
DEBUG ((DEBUG_ERROR, "Cannot find NfitTableUpdateProtocol\n"));
|
||||
}
|
||||
DEBUG ((DEBUG_INFO, "NFIT Update Status: 0x%x\n", Status));
|
||||
|
||||
return Status;
|
||||
}
|
||||
@@ -0,0 +1,42 @@
|
||||
/** @file
|
||||
ACPI Platform Driver Hooks
|
||||
|
||||
@copyright
|
||||
Copyright 1996 - 2016 Intel Corporation. <BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
//
|
||||
// Statements that include other files
|
||||
//
|
||||
#include "AcpiPlatformLibLocal.h"
|
||||
|
||||
/**
|
||||
This function locates the CrystalRidge Protocol and calls
|
||||
into one of its interface function (UpdateAcpiPcatTable) to
|
||||
update/build the PCAT (Platform Capability Attribute Table).
|
||||
And this table gets published in ACPI XSDT.
|
||||
|
||||
@param *Table - Pointer to PCAT table which will be
|
||||
build in CR Protocol and will be publised in ACPI
|
||||
XSDT.
|
||||
@retval Status - Return Status
|
||||
**/
|
||||
EFI_STATUS
|
||||
UpdatePcatTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
)
|
||||
{
|
||||
EFI_STATUS Status;
|
||||
DYNAMIC_SI_LIBARY_PROTOCOL2 *DynamicSiLibraryProtocol2 = NULL;
|
||||
|
||||
Status = gBS->LocateProtocol (&gDynamicSiLibraryProtocol2Guid, NULL, &DynamicSiLibraryProtocol2);
|
||||
if (EFI_ERROR (Status)) {
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
return Status;
|
||||
}
|
||||
|
||||
Status = DynamicSiLibraryProtocol2->UpdatePcatTable (Table);
|
||||
return EFI_SUCCESS;
|
||||
}
|
||||
@@ -0,0 +1,267 @@
|
||||
/** @file
|
||||
ACPI Platform Driver Hooks
|
||||
|
||||
@copyright
|
||||
Copyright 2016 - 2020 Intel Corporation. <BR>
|
||||
|
||||
SPDX-License-Identifier: BSD-2-Clause-Patent
|
||||
**/
|
||||
|
||||
#include "AcpiPlatformLibLocal.h"
|
||||
#include <Protocol/SmbiosMemInfo.h>
|
||||
|
||||
extern struct SystemMemoryMapHob *mSystemMemoryMap;
|
||||
|
||||
/******************************************************************************
|
||||
* Definitions.
|
||||
******************************************************************************/
|
||||
//#define PMTTDEBUG_ENABLED 1
|
||||
#if PMTTDEBUG_ENABLED
|
||||
#define PMTTDEBUG(Expr) _DEBUG(Expr)
|
||||
#else
|
||||
#define PMTTDEBUG(Expr)
|
||||
#endif
|
||||
#ifndef NELEMENTS
|
||||
#define NELEMENTS(Array) (sizeof(Array)/sizeof((Array)[0]))
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
// PMTT GUID variables
|
||||
//
|
||||
const EFI_GUID gEfiPmttTypeDieGuid = PMTT_TYPE_DIE_GUID;
|
||||
const EFI_GUID gEfiPmttTypeChannelGuid = PMTT_TYPE_CHANNEL_GUID;
|
||||
const EFI_GUID gEfiPmttTypeSlotGuid = PMTT_TYPE_SLOT_GUID;
|
||||
|
||||
/******************************************************************************
|
||||
* Functions.
|
||||
******************************************************************************/
|
||||
|
||||
EFI_STATUS
|
||||
PatchPlatformMemoryTopologyTable (
|
||||
IN OUT EFI_ACPI_COMMON_HEADER *Table
|
||||
)
|
||||
{
|
||||
UINT8 Socket;
|
||||
UINT8 Die;
|
||||
UINT8 Imc;
|
||||
UINT8 Channel;
|
||||
UINT8 ChannelIndex;
|
||||
UINT8 Dimm;
|
||||
SMBIOS_DIMM_INFO DimmInfo;
|
||||
SMBIOS_MEM_INFO_PROTOCOL *SmbiosInfoProtocol;
|
||||
EFI_STATUS Status;
|
||||
ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE *PmttTable = (ACPI_PLATFORM_MEMORY_TOPOLOGY_TABLE*)Table;
|
||||
UINT8 MaxImc;
|
||||
UINT8 MaxChPerImc;
|
||||
UINT8 DieCnt;
|
||||
|
||||
DYNAMIC_SI_LIBARY_PROTOCOL2 *DynamicSiLibraryProtocol2 = NULL;
|
||||
|
||||
Status = gBS->LocateProtocol (&gDynamicSiLibraryProtocol2Guid, NULL, &DynamicSiLibraryProtocol2);
|
||||
if (EFI_ERROR (Status)) {
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
return Status;
|
||||
}
|
||||
|
||||
MaxImc = DynamicSiLibraryProtocol2->GetMaxImc ();
|
||||
MaxChPerImc = DynamicSiLibraryProtocol2->GetNumChannelPerMc ();
|
||||
|
||||
ASSERT (PmttTable->Header.Signature == ACPI_PMTT_TABLE_SIGNATURE);
|
||||
|
||||
Status = gBS->LocateProtocol (&gSmbiosMemInfoProtocolGuid, NULL, (VOID**)&SmbiosInfoProtocol);
|
||||
if (EFI_ERROR (Status)) {
|
||||
DEBUG ((DEBUG_ERROR, "[ACPI] (PMTT) Cannot locate SmbiosMemInfoProtocol! (%r)\n", Status));
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
SmbiosInfoProtocol = NULL;
|
||||
}
|
||||
|
||||
for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
|
||||
|
||||
PmttTable->Socket[Socket].Type = ACPI_TOP_LEVEL_SOCKET;
|
||||
PmttTable->Socket[Socket].SckIdent = Socket;
|
||||
PmttTable->Socket[Socket].Length = sizeof(PmttTable->Socket[Socket]) - sizeof(ACPI_PMTT_DIE_DEVICE);
|
||||
PmttTable->Socket[Socket].Flag = 0;
|
||||
PmttTable->Socket[Socket].NumOfMemoryDevices = 0;
|
||||
|
||||
if (mSystemMemoryMap->Socket[Socket].SocketEnabled) {
|
||||
PmttTable->Socket[Socket].Flag |= (PMTT_TOP_LEVEL_AGGREGATOR_DEVICE | PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY);
|
||||
PmttTable->NumOfMemoryDevices++;
|
||||
} else {
|
||||
continue;
|
||||
}
|
||||
|
||||
DieCnt = DynamicSiLibraryProtocol2->GetAcpiDieCount (Socket);
|
||||
for (Die = 0; Die < DieCnt; Die++) {
|
||||
|
||||
PmttTable->Socket[Socket].Die[Die].Type = ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE;
|
||||
PmttTable->Socket[Socket].Die[Die].Length = sizeof(PmttTable->Socket[Socket].Die[Die]) - MAX_IMC * sizeof(ACPI_PMTT_IMC_DEVICE);
|
||||
PmttTable->Socket[Socket].Die[Die].Flag = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].Flag |= PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY;
|
||||
PmttTable->Socket[Socket].Die[Die].NumOfMemoryDevices = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].DieId = Die;
|
||||
CopyGuid (&PmttTable->Socket[Socket].Die[Die].TypeUuid, &gEfiPmttTypeDieGuid);
|
||||
|
||||
PmttTable->Socket[Socket].NumOfMemoryDevices++;
|
||||
|
||||
for (Imc = 0; Imc < MaxImc; Imc++) {
|
||||
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Type = ACPI_TOP_LEVEL_IMC;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Length = sizeof(PmttTable->Socket[Socket].Die[Die].Imc[Imc]) - MAX_MC_CH * sizeof(ACPI_PMTT_CHANNEL_DEVICE);
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Flag = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].NumOfMemoryDevices = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].ImcId = Imc;
|
||||
|
||||
if (mSystemMemoryMap->Socket[Socket].imcEnabled[Imc]) {
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Flag |= PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY;
|
||||
PmttTable->Socket[Socket].Die[Die].NumOfMemoryDevices++;
|
||||
} else {
|
||||
continue;
|
||||
}
|
||||
|
||||
for (Channel = 0; Channel < MaxChPerImc; Channel++) {
|
||||
|
||||
ChannelIndex = MEM_IMCCH_TO_SKTCH(Imc, Channel);
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Type = ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Length = sizeof(PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel]) - MAX_DIMM * sizeof(ACPI_PMTT_SLOT_DEVICE);
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Flag = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].NumOfMemoryDevices = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].ChannelId = Channel;
|
||||
CopyGuid (&(PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].TypeUuid), &gEfiPmttTypeChannelGuid);
|
||||
|
||||
if (mSystemMemoryMap->Socket[Socket].ChannelInfo[ChannelIndex].Enabled) {
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Flag |= PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].NumOfMemoryDevices++;
|
||||
} else {
|
||||
continue;
|
||||
}
|
||||
|
||||
for (Dimm = 0; Dimm < MAX_DIMM; Dimm++) {
|
||||
//
|
||||
// Looping through the each DIMM on the IMC.
|
||||
//
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Type = ACPI_TOP_LEVEL_VENDOR_SPECIFIC_DEVICE;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Length = sizeof(PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm]) - sizeof(ACPI_PMTT_DIMM_DEVICE);
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Flag |= PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].NumOfMemoryDevices = 0;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].SlotId = Dimm;
|
||||
CopyGuid (&PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].TypeUuid, &gEfiPmttTypeSlotGuid);
|
||||
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Type = PHYSICAL_COMPONENT_IDENTIFIER_TYPE_DIMM;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Length = sizeof(PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm);
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.NumOfMemoryDevices = 0;
|
||||
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Flag = 0;
|
||||
|
||||
if (!mSystemMemoryMap->Socket[Socket].ChannelInfo[ChannelIndex].DimmInfo[Dimm].Present) {
|
||||
continue;
|
||||
}
|
||||
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Flag |= PMTT_PHYSICAL_ELEMENT_OF_TOPOLOGY;
|
||||
|
||||
if (mSystemMemoryMap->Socket[Socket].ChannelInfo[ChannelIndex].DimmInfo[Dimm].DcpmmPresent) {
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Flag |= PMTT_AEP_DIMM;
|
||||
}
|
||||
//
|
||||
// Get SMBIOS handle for the DIMM. If handle not found use FFFFFFFFh.
|
||||
//
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.SmbiosHandle = (UINT32)-1;
|
||||
if (SmbiosInfoProtocol != NULL) {
|
||||
|
||||
DimmInfo.Socket = Socket;
|
||||
DimmInfo.Imc = Imc;
|
||||
DimmInfo.Channel = Channel;
|
||||
DimmInfo.Dimm = Dimm;
|
||||
Status = SmbiosInfoProtocol->SmbiosGetDimmByLocation (SmbiosInfoProtocol, &DimmInfo);
|
||||
if (!EFI_ERROR (Status)) {
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.SmbiosHandle = DimmInfo.Type17Handle;
|
||||
}
|
||||
}
|
||||
|
||||
if (!mSystemMemoryMap->Socket[Socket].ChannelInfo[ChannelIndex].DimmInfo[Dimm].Enabled) {
|
||||
continue;
|
||||
}
|
||||
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].NumOfMemoryDevices++;
|
||||
PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].NumOfMemoryDevices++;
|
||||
} // for (Dimm...)
|
||||
} // for (Channel...)
|
||||
} // for (Imc...)
|
||||
} // for (Die...)
|
||||
} // for (Skt...)
|
||||
//
|
||||
// Dump the strucutre for debug purpose
|
||||
//
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) Signature: 0x%08X\n", PmttTable->Header.Signature));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) Length: %d\n", PmttTable->Header.Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) Revision: %d\n", PmttTable->Header.Revision));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) Checksum: %d\n", PmttTable->Header.Checksum));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) OemId: '%c%c%c%c%c%c'\n",
|
||||
PmttTable->Header.OemId[0], PmttTable->Header.OemId[1], PmttTable->Header.OemId[2],
|
||||
PmttTable->Header.OemId[3], PmttTable->Header.OemId[4], PmttTable->Header.OemId[5]));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) OemTableId: 0x%08X\n", PmttTable->Header.OemTableId));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) OemRevision: %d\n", PmttTable->Header.OemRevision));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) CreatorId: 0x%08X\n", PmttTable->Header.CreatorId));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) CreatorRevision: %d\n", PmttTable->Header.OemRevision));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) NumOfMemoryDevices: %d\n", PmttTable->NumOfMemoryDevices));
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "\n"));
|
||||
for (Socket = 0; Socket < NELEMENTS (PmttTable->Socket); Socket++) {
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d] Type: 0x%02X\n", Socket, PmttTable->Socket[Socket].Type));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d] Length: %d\n", Socket, PmttTable->Socket[Socket].Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d] Flags: 0x%04X\n", Socket, PmttTable->Socket[Socket].Flag));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d] SocketId: %d\n", Socket, PmttTable->Socket[Socket].SckIdent));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d] NumOfMemoryDevices: %d\n", Socket, PmttTable->Socket[Socket].NumOfMemoryDevices));
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "\n"));
|
||||
for (Die = 0; Die < NELEMENTS(PmttTable->Socket[Socket].Die); Die++) {
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d] Type: 0x%02X\n", Socket, Die, PmttTable->Socket[Socket].Die[Die].Type));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d] Length: %d\n", Socket, Die, PmttTable->Socket[Socket].Die[Die].Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d] Flags: 0x%04X\n", Socket, Die, PmttTable->Socket[Socket].Die[Die].Flag));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d] DieId: %d\n", Socket, Die, PmttTable->Socket[Socket].Die[Die].DieId));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d] TypeUuid: %g\n", Socket, Die, PmttTable->Socket[Socket].Die[Die].TypeUuid));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d] NumOfMemoryDevices: %d\n", Socket, Die, PmttTable->Socket[Socket].Die[Die].NumOfMemoryDevices));
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "\n"));
|
||||
for (Imc = 0; Imc < NELEMENTS(PmttTable->Socket[Socket].Die[Die].Imc); Imc++) {
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d] Type: 0x%02X\n", Socket, Die, Imc, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Type));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d] Length: %d\n", Socket, Die, Imc, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d] Flags: 0x%04X\n", Socket, Die, Imc, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Flag));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d] ImcId: %d\n", Socket, Die, Imc, PmttTable->Socket[Socket].Die[Die].Imc[Imc].ImcId));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d] NumOfMemoryDevices: %d\n", Socket, Die, Imc, PmttTable->Socket[Socket].Die[Die].Imc[Imc].NumOfMemoryDevices));
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "\n"));
|
||||
for (Channel = 0; Channel < NELEMENTS(PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel); Channel++) {
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d] Type: 0x%02X\n", Socket, Die, Imc, Channel, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Type));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d] Length: %d\n", Socket, Die, Imc, Channel, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d] Flags: 0x%04X\n", Socket, Die, Imc, Channel, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Flag));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d] ChannelId: %d\n", Socket, Die, Imc, Channel, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].ChannelId));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d] TypeUuid: %g\n", Socket, Die, Imc, Channel, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].TypeUuid));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d] NumOfMemoryDevices: %d\n", Socket, Die, Imc, Channel, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].NumOfMemoryDevices));
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "\n"));
|
||||
for (Dimm = 0; Dimm < NELEMENTS(PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot); Dimm++) {
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d] Type: 0x%02X\n", Socket, Die, Imc, Channel, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Type));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d] Length: %d\n", Socket, Die, Imc, Channel, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d] Flags: 0x%04X\n", Socket, Die, Imc, Channel, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Flag));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d] SlotId: %d\n", Socket, Die, Imc, Channel, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].SlotId));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d] TypeUuid: %g\n", Socket, Die, Imc, Channel, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].TypeUuid));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d] NumOfMemoryDevices: %d\n", Socket, Die, Imc, Channel, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].NumOfMemoryDevices));
|
||||
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d][%d] Type: 0x%02X\n", Socket, Die, Imc, Channel, Dimm, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Type));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d][%d] Length: %d\n", Socket, Die, Imc, Channel, Dimm, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Length));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d][%d] Flags: 0x%04X\n", Socket, Die, Imc, Channel, Dimm, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.Flag));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d][%d] SmbiosHandle: 0x%08X\n", Socket, Die, Imc, Channel, Dimm, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.SmbiosHandle));
|
||||
PMTTDEBUG ((DEBUG_INFO, "[ACPI] (PMTT) [%d][%d][%d][%d][%d][%d] NumOfMemoryDevices: %d\n", Socket, Die, Imc, Channel, Dimm, Dimm, PmttTable->Socket[Socket].Die[Die].Imc[Imc].Channel[Channel].Slot[Dimm].Dimm.NumOfMemoryDevices));
|
||||
} // for (Dimm...)
|
||||
} // for (Channel...)
|
||||
} // for (Imc...)
|
||||
} // for (Die...)
|
||||
} // for (Skt...)
|
||||
return EFI_SUCCESS;
|
||||
} // PatchPlatformMemoryTopologyTable ()
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -398,6 +398,11 @@
|
||||
##
|
||||
gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE|BOOLEAN|0x0000002C
|
||||
|
||||
## Platform Not support Acpi Table
|
||||
#
|
||||
gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiTable|FALSE|BOOLEAN|0x40000012
|
||||
gPlatformTokenSpaceGuid.PcdPlatformNotSupportAcpiBdatTable|FALSE|BOOLEAN|0x40000013
|
||||
|
||||
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx]
|
||||
## MemoryCheck value for checking memory before boot OS.
|
||||
# To save the boot performance, the default MemoryCheck is set to 0.
|
||||
|
||||
@@ -621,6 +621,7 @@
|
||||
CrcLib|WhitleyOpenBoardPkg/Library/BaseCrcLib/BaseCrcLib.inf
|
||||
PlatformSpecificAcpiTableLib|WhitleyOpenBoardPkg/Library/PlatformSpecificAcpiTableLibNull/PlatformSpecificAcpiTableLibNull.inf
|
||||
BuildAcpiTablesLib|WhitleyOpenBoardPkg/Library/BuildAcpiTablesLib/DxeBuildAcpiTablesLib.inf
|
||||
AcpiPlatformTableLib|WhitleyOpenBoardPkg/Library/AcpiPlatformTableLib/AcpiPlatformLib.inf
|
||||
|
||||
[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
|
||||
FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
|
||||
|
||||
Reference in New Issue
Block a user