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Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch

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Ordinary computers typically have a physical switch or jumper on the
board that allows non-volatile settings to be cleared. Let's implement
the same using DIP switch #1 on block #3, and clear the EFI variable
store if it is set to ON at boot time.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel
2017-11-01 13:23:01 +00:00
parent 563c2efbfa
commit 71096fc4a8
7 changed files with 48 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
Platform/Socionext/DeveloperBox/DeveloperBox.dsc
View File

@@ -381,6 +381,9 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4f524e4c # LNRO
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
# set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0
[PcdsPatchableInModule]
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
@@ -418,6 +421,7 @@
MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf

1
Platform/Socionext/DeveloperBox/DeveloperBox.fdf
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@@ -258,6 +258,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf
INF RuleOverride = FMP_IMAGE_DESC Platform/Socionext/DeveloperBox/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

4
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc
View File

@@ -369,6 +369,9 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x08420000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
# set DIP switch DSW3-PIN1 (GPIO pin PD[0] on the SoC) to clear the varstore
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0
[PcdsPatchableInModule]
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
@@ -406,6 +409,7 @@
MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
<LibraryClasses>
NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf

1
Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf
View File

@@ -248,6 +248,7 @@ READ_LOCK_STATUS = TRUE
INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
INF MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerGpioPei/SynQuacerGpioPei.inf
INF RuleOverride = FMP_IMAGE_DESC Platform/Socionext/SynQuacerEvalBoard/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf

30
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c
View File

@@ -21,8 +21,11 @@
#include <Library/PeiServicesLib.h>
#include <Platform/DramInfo.h>
#include <Ppi/DramInfo.h>
#include <Ppi/EmbeddedGpio.h>
#include <Ppi/MemoryDiscovered.h>
#define CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED MAX_UINT8
STATIC
CONST DRAM_INFO *mDramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase);
@@ -103,10 +106,35 @@ PlatformPeim (
VOID
)
{
EFI_STATUS Status;
EMBEDDED_GPIO_PPI *Gpio;
EFI_STATUS Status;
UINTN Value;
UINT8 Pin;
ASSERT (mDramInfo->NumRegions > 0);
Pin = FixedPcdGet8 (PcdClearSettingsGpioPin);
if (Pin != CLEAR_SETTINGS_GPIO_NOT_IMPLEMENTED) {
Status = PeiServicesLocatePpi (&gEdkiiEmbeddedGpioPpiGuid, 0, NULL,
(VOID **)&Gpio);
ASSERT_EFI_ERROR (Status);
Status = Gpio->Set (Gpio, Pin, GPIO_MODE_INPUT);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: failed to set GPIO as input - %r\n",
__FUNCTION__, Status));
} else {
Status = Gpio->Get (Gpio, Pin, &Value);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: failed to get GPIO state - %r\n",
__FUNCTION__, Status));
} else if (Value > 0) {
DEBUG ((DEBUG_INFO, "%a: clearing NVRAM\n", __FUNCTION__));
PeiServicesSetBootMode (BOOT_WITH_DEFAULT_SETTINGS);
}
}
}
//
// Record the first region into PcdSystemMemoryBase and PcdSystemMemorySize.
// This is the region we will use for UEFI itself.

6
Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf
View File

@@ -25,6 +25,7 @@
[Packages]
ArmPkg/ArmPkg.dec
EmbeddedPkg/EmbeddedPkg.dec
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
Silicon/Socionext/SynQuacer/SynQuacer.dec
@@ -40,11 +41,16 @@
[FixedPcd]
gArmTokenSpaceGuid.PcdFvBaseAddress
gArmTokenSpaceGuid.PcdFvSize
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin
gSynQuacerTokenSpaceGuid.PcdDramInfoBase
[Ppis]
gEdkiiEmbeddedGpioPpiGuid ## CONSUMES
gSynQuacerDramInfoPpiGuid ## PRODUCES
[Pcd]
gArmTokenSpaceGuid.PcdSystemMemoryBase
gArmTokenSpaceGuid.PcdSystemMemorySize
[Depex]
gEdkiiEmbeddedGpioPpiGuid

3
Silicon/Socionext/SynQuacer/SynQuacer.dec
View File

@@ -30,3 +30,6 @@
gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase|0|UINT32|0x00000002
gSynQuacerTokenSpaceGuid.PcdNetsecPhyAddress|0|UINT8|0x00000003
# GPIO pin index [0 .. 31] or MAX_UINT8 for not implemented
gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004