Commit Graph

1044 Commits

Author SHA1 Message Date
Krystian Hebel 8aab755c31 Documentation/drivers/smmstorev2.md: describe capsule update API
This commit adds a description of capsule update commands implemented
in SMMSTORE in previous patches.

Upstream-Status: Submitted [CB:83426]
Change-Id: I94761d18be567e5302d1a836f09f0a7eecb4fb00
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2025-03-26 20:19:02 +02:00
Felix Singer a1532790b9 docs: Add 24.12 release notes
Also drop the 24.11 release notes template.

Change-Id: Ifeb88a1bb4f05183ac9274de9b26970b6155017d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-12-20 05:16:06 +00:00
Felix Singer f6fcff5511 docs/security/vboot: Update supported boards
Change-Id: I9785a0b06f4cb97970be6aadc47bf3f7c37c9f20
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-12-20 04:15:48 +00:00
Angel Pons 91fe658714 drivers/option: Add forms in cbtables
Introduce a mechanism so that coreboot can provide a list of options to
post-coreboot code. The options are grouped together into forms and
have a meaning name and optional help text. This can be used to let
payloads know which options should be displayed in a setup menu,
for instance. Although this system was written to be used with edk2,
it has been designed with flexibility in mind so that other payloads
can also make use of this mechanism. The system currently lacks a way
to describe where to find option values.

This information is stored in a set of data structures specifically
created for this purpose. This format is known as CFR, which means
"coreboot forms representation" or "cursed forms representation".
Although the "forms representation" is borrowed from UEFI, CFR can
be used in non-UEFI scenarios as well.

The data structures are implemented as an extension of cbtables records
to support nesting. It should not break backwards compatibility because
the CFR root record (LB_TAG_CFR_ROOT) size includes all of its children
records. The concept of record nesting is borrowed from the records for
CMOS options. It is not possible to reuse the CMOS records because they
are too closely coupled with CMOS options; using these structures would
needlessly restrict more capable backends to what can be done with CMOS
options, which is undesired.

Because CFR supports variable-length components, directly transforming
options into CFR structures is not a trivial process. Furthermore, CFR
structures need to be written in one go. Because of this, abstractions
exist to generate CFR structures from a set of "setup menu" structures
that are coreboot-specific and could be integrated with the devicetree
at some point. Note that `struct sm_object` is a tagged union. This is
used to have lists of options in an array, as building linked lists of
options at runtime is extremely impractical because options would have
to be added at the end of the linked list to maintain option order. To
avoid mistakes defining `struct sm_object` values, helper macros exist
for supported option types. The macros also provide some type checking
as they initialise specific union members.

It should be possible to extend CFR support for more sophisticated
options like fan curve points. Feedback about this is highly
appreciated.

Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74121
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-12-18 18:16:51 +00:00
Nicholas Chin eeb6f67eec Docs: Convert bare URLs into hyperlinks
Format bare URLs as links so that they are rendered as hyperlinks
instead of plain text.

Change-Id: I234d395cddd58f3d3dfb4b4ddccb6efc70d4dd9e
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85433
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-12-14 06:23:13 +00:00
Nicolas Kochlowski 78270ef3f1 Documentation/tutorial/managing_local_additions.md: Add symlink info
Add information about how the symlink target can be used
to develop and test additions to the coreboot tree from
site-local.

Change-Id: I75f9e9575005e9ee2f255848a21c5e57c30e9e72
Signed-off-by: Nicolas Kochlowski <nickkochlowski@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ana Carolina Cabral
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-12-03 14:06:46 +00:00
Nicholas Chin 7f54139a81 Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax
Fix the syntax [1] for the footnote about the onboard memory
configuration so that it renders properly in the generated html.
This also fixes a "Unknown target name" error when building with
newer versions of Sphinx (tested with 8.1.3).

[1] https://myst-parser.readthedocs.io/en/latest/syntax/typography.html#footnotes

Change-Id: I07a85b854a181794f82d8e6a739063d66378d2c7
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85412
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-12-01 05:43:25 +00:00
Michał Zieliński f30d11ccd7 mb/hp: Add HP Compaq 8300 Elite SFF
* Add initial board commit based on HP 8200 SFF and HP Z220 SFF.
* Add documentation.

Tested on HP 8300 SFF.

Change-Id: Ib5322acc0210f000b53954e2925549358f86d5c8
Signed-off-by: Michał Zieliński <michal.zielinski@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67666
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
2024-11-20 22:14:18 +00:00
Maximilian Brune a9e5ab7bb0 Documentation/acronyms.md: Add some acronyms
These acronyms have been found while looking at the datasheet of the
JH7110 RISC-V SOC.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I82104b88e7723b73810f20d5f4dffe6ed8a9ab78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83847
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-18 01:23:14 +00:00
Xue Yao 478be8a228 Documentation: Update Protectli fw6b documentations
Update documentations:
- ME cleaner has been tested on the fw6b.
- More observations on the stock firmware is documented.
- Compatible boards are listed along with the original manufacturer.

Signed-off-by: Xue Yao <xueyao@xyte.ch>
Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63016
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-11-07 04:21:52 +00:00
Maxim Polyakov c1caa33a2d mb/asrock: Add Asrock Industrial IMB-1222 motherboard
ASRock IMB-1222 Intel Comet Lake-S Q470E industrial thin mini-ITX
motherboard [1].

Working:
- Dual Channel DDR4 2933/2666/2400 MHz;
- Intel UHD Graphics (VGA Option ROM, libgfxinit, GOP driver);
- DP (both), HDMI;
- PCIe x16 Slot (Gen3);
- SATA ports;
- USB 2.0 ports;
- USB 3.2 ports;
- M.2 Key-E 2230 slot for Wireless (PCIe x1, USB 2.0 and CNVi);
- M.2 Key-B 3042/3052 slot for 4G/5G modem (PCIe x1);
- M.2 Key-M 2242/2260/2280 for SSD/NVMe (PCIE x4, SATA3);
- LAN1 Intel I225LM/I225V, 10/100/1000/2500 Mbps;
- LAN2 Intel I219LM, 10/100/1000 Mbps;
- Realtek ALC887 HD Audio (line-out, mic-in);
- COM 1/2/3/4 ports;
- onboard speaker;
- HWM/FANs control (fintek f81966);
- S3 suspend and wake;
- TPM;
- disabling ME with me_cleaner [2];

Payload:
- Linux as payload;
- LinuxBoot;
- SeaBIOS;
- edk2 [3].

Bootable OS:
- Ubuntu 22.04 (Linux 6.5.0-15-generic);
- Ubuntu 24.04 (Linux 6.8.0-41-generic);
- Microsoft Windows 10 Pro (10.0.19045.4780, 22H2 2022);
- Andoid 13, Bliss OS x86_64 (16.9.7, Linux 6.1.112-gloria-xanmod1).

Unknown/untested:
- USB3.0 in M.2 Key-B 3042/3052 slot;
- eDP/LVDS;
- PCIe riser cards;
- SPDIF.

There is no schematic/boardview, reverse engineering only.
This port is based on system76/bonw14 because it has a similar topology.

[1] https://web.archive.org/web/20220924171403/https://
www.asrockind.com/en-gb/IMB-1222

[2] XutaxKamay's me_cleaner fork,
https://github.com/XutaxKamay/me_cleaner, v1.2-9-gf20532d

[3] MrChromebox's edk2 fork, https://github.com/mrchromebox/edk2
uefipayload_2408 branch

Change-Id: Id2b4c903546f9174b5e7dd26e54a0c5aaa09e1f8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83107
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-07 03:18:00 +00:00
Maciej Pijanowski d28fedf4f2 mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here.

Works:
- Serial adapter from daughter board (COM1 connector)
- USB ports front and back
- USB-C port (charging, data)
- HDMI
- Ethernet
- SATA
- NVMe
- internal speaker
- TPM2.0
- PCIe x8 port (x8 riser tested, x4 not)

Does not work:
- front audio jacks

Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80609
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-05 20:34:19 +00:00
Nicholas Chin 6d8bb8cf29 Docs: Turn warnings into errors
Use the -W (--fail-on-warning) flag of sphinx-build to tell it to exit
with an error if any warnings are generated. This is intended to fail
the coreboot-docs-gerrit build to help catch issues.

To allow all warnings to be output in the same build, use the
--keep-going flag so that the author is able to see all issues and
address them after a single build. Note that this behavior is enabled by
default as of Sphinx 8.1 and this option may be removed in the future.
It is added here for compatibility with older versions of Sphinx,
including the doc.coreboot.org container which uses 7.2.6.

Change-Id: I3aa564b79d4d4125a3800023b1b805bf4a50b10a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-10-27 23:51:11 +00:00
Nicholas Chin d95d9f8ce8 Documentation: Remove ditaa support
Ditaa is a utility to convert ascii block diagrams into bitmap graphics.
The latest sphinx-contrib-ditaa extension has not been updated since
2022 [1] and does not declare whether it is safe for parallel reading,
causing sphinx to issue a warning as we use the `-j auto` flag to
parallelize the build. It doesn't seem like anyone ever used it in the
docs aside from a now abandoned patch [2], so just remove it.

[1] https://pypi.org/project/sphinxcontrib-ditaa/
[2] https://review.coreboot.org/c/coreboot/+/37643

Change-Id: I460ce24aab203cbb416888787fc6e2c613d306b3
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84887
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-27 23:51:03 +00:00
Nicholas Chin b6f3ee3f8f util/util_readme: Use HTML comments in generated output
Util_readme adds comments to the top of the generated Doc/util.md file
to indicate that it is generated and should not be edited directly.
These comments are not intended to show up in the rendered HTML output.
Since Markdown does not have a native way of adding comments, the
`[comment text]: #` syntax is often used to mark the line as a comment.
This takes advantage of the fact that references (often used throughout
the docs to list long URLs at the end of the document and reference them
in inline links) aren't rendered. However, MyST parser detects these as
a duplicate reference and issues a warning, since both lines use "//" as
the comment text.

Address this by using HTML comments, since Markdown also allows raw HTML
to be used. This seems like a cleaner option compared to repurposing
references and appears to have better compatibility with various
Markdown readers, which may be useful if someone wants to read the
documentation outside of doc.coreboot.org.

While we are here, regenerate Documentation/util.md and util/README.md

Change-Id: Ibd4f61009c01c7b64594d88c5d86e472f0ccaa6c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-10-27 23:50:57 +00:00
Nicholas Chin 10d22313f7 Docs: Address remaining documents not included in toctrees
Sphinx outputs "document isn't included in any toctree" warnings for a
few files in the Documentation tree, so address this by adding them to
toctrees or explicitly marking them as excluded.

- mb/starlabs/common/building.md: Add to the Star Labs toctree in
  mainboard/index.md
- RFC/intel-gpio-cleanup.md: Mark as orphan to explicitly exclude it
  from the docs.
- drivers/dt_entries.md: This was already accessible through an inline
  link in drivers/index.md, but links do not add items to toctrees. Add
  a hidden toctree listing dt_entries.md to define its heirarchy in the
  documentation while preserving the inline link instead of moving the
  link to a single item list like a normal toctree would. The content of
  this document did not fit the existing toctree in drivers/index.md,
  which appears to list drivers, while dt_entries discusses connecting
  those drivers to the devicetree.

Change-Id: I5fd6851a3adf6c91d81298fc61f773dae6eeca19
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-10-27 23:50:29 +00:00
Shuo Liu 495b705137 configs/builder: Update PBP path for Gen6 Xeon-SP boards
Gen6 Xeon-SP boards needs to be provided with platform boot policy
blob.

Change-Id: I22b944ab6bcb2b9d0797833c06410bdc523e2709
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-10-23 10:30:26 +00:00
Martin Roth 7c57f9aec6 Documentation: Update the code of conduct
This change reiterates that the coreboot leadership may revoke a user's
privileges. This does not change anything, as it already says "The
community organizers may take any action they deem appropriate, up to
and including a temporary ban or permanent expulsion from the community
without warning".

Also add a note that the discussions are private. If someone wants to
make the issue public, the coreboot leadership can't stop them, but the
board believes in handling these issues privately.

Finally, add a note that if there's an issue with someone on the
arbitration board, issues may be taken directly to the leadership board.

Change-Id: I5e2010a16f31f892bd1761b56b96ea773877dea0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2024-10-14 15:29:46 +00:00
Nicholas Sudsgaard 520c6cbfb9 Doc/soc/amd/family17h: Fix URL to AGESA Interface Specification
The original URL now points to "AMD Documentation Hub" and not the
document.

Change-Id: Icc42943340132843df2387cc1203178a0774a387
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-10-14 15:29:28 +00:00
Shuo Liu edf390dee5 Documentation/soc/intel/xeon_sp: Add targeted feature list
Add targeted feature list for Xeon 6 coreboot. The listed features
are targeted to be supported by Xeon 6 coreboot design, while some
specific items might need fixes and improvements per community
feedback.

Change-Id: Ibecd63dfca10712223ccdd943109ba28ed668200
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84701
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-14 15:28:09 +00:00
Shuo Liu f2bc295a9c Documentation/soc/intel/xeon_sp: Format community preview guide
Commit 5e0d370610 ("Documentation/soc/intel/xeon_sp: Update doc to
use real FSP headers") had some unresolved review comments for
formats after it had been submitted. Take care of these comments in
this follow-up.

Change-Id: I7b33bed56fdd86d7b4ab5bfefcd3abc4a3ba4ce9
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-07 21:03:27 +00:00
Patrick Georgi 52e5e219e2 Documentation: Remove myself from various roles
I'm not doing that stuff anymore so this updates the documentation
to reflect reality.

Change-Id: I2feac471274ccfb756ca5b029ec86f2161dc2bfc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-10-06 12:03:08 +00:00
Sean Rhodes 55de4d9ab4 mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variant
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 24.04

No known issues.

https://starlabs.systems/pages/starfighter-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03 09:31:33 +00:00
Shuo Liu 5e0d370610 Documentation/soc/intel/xeon_sp: Update doc to use real FSP headers
Change-Id: I4a8b01a661a92630d41837a168e17a0fa3c50f04
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-26 15:10:19 +00:00
Jincheng Li e8bff7c010 Documentation/soc/intel/xeon_sp: Update Xeon 6 test config
Change-Id: Ia54af1495a0146be3e5c3e74a0dcfef6785d6371
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84331
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-23 08:37:40 +00:00