Add CONFIG_ENABLE_EMMC Kconfig option (default y) to allow building
firmware without eMMC support for VP2440e hardware variants that lack
the eMMC controller. When disabled, ScsEmmcEnabled is cleared in FSP-S
UPD and the PCH eMMC device is disabled in ACPI, preventing spurious
initialization errors in firmware logs. SMBIOS product name reflects
the variant ("VP2440" vs "VP2440e"). Adds config.protectli_vp2440_no_emmc
defconfig and vp2440_noemmc/vp2440e build targets to build.sh.
Upstream-Status: Inappropriate [Dasharo downstream]
Signed-off-by: Wiktor Mowinski <wiktor.mowinski@3mdeb.com>
The button sits on a multi-function pin of the IT8613E.
Enabled the chip's GPIO block in devicetree.cb, muxed
the pin to GP12 (away from PCIRST1#), and turned on
its internal pull-up to make the signal go back to 1
after the button is released.
Upstream-Status: Inappropriate [Dasharo downstream]
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
New FD blobs have changed SPA setting such that:
- SATA is disabled
- Lane reversal is enabled
- 2x2 or 1x2 + 2x1 bifurcation is configured
This way, the SSD always lands on root port 1 and gets 2 lanes, and
subsequent devices on lanes 2,3 of SPA get allocated either an x1 or x2
link depending on board.
Upstream-Status: Pending
Change-Id: Ibd007334d09872baf7781ad2887212f4f847fc9b
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
The option controls setting `ScsEmmcEnabled` and `ScsEmmcHs400Enabled` in FSPs.
`ScsEmmcHs400Enabled` can be set in devicetree.cb as it's read from the file created by sconfig.
`ScsEmmcEnabled` must be changed in the device config struct read using
`pcidev_on_root` in `mainboard_silicon_init_params()` in ramstage,
because `platform_fsp_silicon_init_params_cb()` sets it using
`is_devfn_enabled(PCH_DEVFN_EMMC)` after mainboard_silicon_init_params
was already called. Setting it directly in FSPS_UPD won't work as
it would be replaced with what `is_devfn_enabled` returns.
`is_devfn_enabled` returns true if in devicetree.cb `device pci 1a.0` is `on`
(PCH_DEVFN_EMMC for cometlake is at PCHDEV_SLOT 0x1A,
device 0 according to src/soc/intel/cannonlage/include/soc/pci_devs.h).
Upstream-Status: Pending
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Commit 7c7feca258 ("CBFS verification: support Top Swap redundancy")
forced reset of metadata cache before processing every region to make it
possible to process slots A and B in a single invocation of cbfstool
when Top Swap (TS) redundancy is enabled. The slots use separate
bootblock copies each with its own metadata anchor, so cache cannot be
blindly reused.
This change invalidates the cache only when a transition from a TS to a
non-TS (or vice versa) region is detected, which is achieved by tracking
what is currently in the cache.
Additionally, make the function fail if TOPSWAP region is not found.
Upstream-Status: Backport [CB:92025]
Change-Id: I37da5585ceffdaa243c6b77471637d2457134768
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/92025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit 7c7feca258 ("CBFS verification: support Top Swap redundancy")
added an optional `type` parameter to `_cbfs_unverified_area_alloc()` to
match `_cbfs_alloc()` and permit uniform use of both functions, but did
it via copy&paste. Properly extract the duplicated part to its own
function.
Upstream-Status: Backport [CB:92028]
Change-Id: I6383fcb0ee9e8e4714b38972b471718cbada8cbf
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/92028
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:89691 incorrectly updated the line which was meant to check
specifically for "COREBOOT", thus accidentally permitting creation of
images with "COREBOOT_TS" but no "COREBOOT".
Upstream-Status: Backport [CB:92026]
Change-Id: I0a2daa9fab29a3dd52683aabca299ad2c26d1302
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/92026
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The verification happens only when CMOS options backend is in use and
SMM queries an option (this implicitly loads `cmos.layout` from CBFS).
CB:89691 has added an exception for SMM since apparently nobody is
using CBFS verification and CMOS options backend at the same time, but
the exception introduced a security risk which this change resolves by
permitting linking to vboot library in SMM.
Upstream-Status: Backport [CB:92024]
Change-Id: If3e5c92cb3e8bca8ea7600343f676dd895f02d41
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/92024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similarly to CB:29395, which has added toolchain for POSTCAR, this is
done for the purpose of making it possible to link vboot2 library in
SMM.
Until now SMM has been using options for ramstage, so using that as a
default and updating the uses in src/cpu/x86/smm/Makefile.mk
Upstream-Status: Backport [CB:92023]
Change-Id: I20f2378eaf69b11b09a3d85d305e17110cf3c7ee
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/92023
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is the root port that the NVMe disk uses after updating the descriptors.
Upstream-Status: Pending
Change-Id: Id5e8b2a6e953f64d2a60fb1cf3caa8dcdd71d238
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is the root port that the NVMe disk uses after updating the descriptors.
Upstream-Status: Pending
Change-Id: I5b64cf27d3dac5cf1bf5c2c6d682528e94a6628e
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This is the root port that the NVMe disk uses after updating the descriptors.
Upstream-Status: Pending
Change-Id: I634e4d311d9599847430488270102314f9241a94
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Customer has requested disabling the capability.
Fixes compatibility with certain Samsung NVMe SSDs.
Upstream-Status: Pending
Change-Id: I997c372d1e17a954f6d28f55c9cc55a50ceb82df
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested with an ARC A310 GPU:
Memory at 500000000 (64-bit, prefetchable) [size=4G]
Upstream-Status: Pending
Change-Id: Ie4d02ed15f1561ad05405b5167796483fd70c1a4
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Filip Gołaś
Wiktor Mowinski
Michał Kopeć
Sergii Dmytruk
Michał Kopeć