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68 Commits

Author SHA1 Message Date
Johann C. Rode 4eb524ee9d spd/ddr4: Add three more parts 
This patch adds three more parts that are used in Lenovo Thinkpads:

SKHynix H5AN4G6NAFR-UHC
SKHynix H5ANAG6NAMR-UHC
Micron MT40A512M16LY-075:H

The settings (MT/s, timing, organization, etc.) have been obtained from
schematics and datasheets.

Change-Id: Ie0958a4a845f072daee3379731f558584dca5da6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2025-12-02 01:54:30 +00:00
Johann C. Rode e4a809d441 spd/ddr4: Double packageBusWidth of dual die package parts to 16 
This fixes an error I made in my previous commit 8a83b86254 (spd/ddr4:
add parts), CB:90032. The package bus width for all the dual die parts
is indeed 16 rather than 8. This has been validated when porting
coreboot to the Lenovo Thinkpad X280 that uses soldered-on DDP RAM
(Samsung K4AAG165WB-MCRC).

Change-Id: I8baa7c979074584e65772315e66e787cef3202e4
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2025-12-02 01:54:18 +00:00
John Su 80cf2008a9 spd/lp5: Add SPD for MT62F1G32D2DS-031RF WT:C 
Add MT62F1G32D2DS-031RF WT:C in the memory_parts.json and re-generate
the SPD.

BUG=b:459934066
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ib65f24347ddae2808720f8e3c73652a82de94311
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90019
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2025-11-29 20:03:21 +00:00
Luca Lai 10802bac16 spd/lp5: Modify SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV 
Modify ranksPerChannel and diesPerPackage attributes for
MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV.

TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I1069fac58d099d58f76fe268973081f49842f16d
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2025-11-25 04:44:11 +00:00
Johann C. Rode 8a83b86254 spd/ddr4: add parts 
This patch adds parts used on Lenovo Thinkpads:

Micron MT40A512M16HA-083E:A
Micron MT40A1G16HBA-083E:A
Samsung K4A8G165WB-BCPB
Micron MT40A512M16JY-083E:B
Micron MT40A1G16WBU-083E:B
Samsung K4A8G165WC-BCRC
Samsung K4AAG165WB-MCRC
SKHynix H5AN8G6NAFR-UHC
SKHynix H5AN8G6NAMR-UHC
Micron MT40A512M6LY-075:E
Micron MT40A256M16GE-083E
Samsung K4A4G165WE-BCRC

The SPD data (timing, configuration, etc.) has been extracted from datasheets and laptop schematics. When there has been conflicting data between these data sources, slower (safer) values were picked.

Change-Id: Ied92619130feaa160d01f75bc38230ab6a024ace
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90032
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2025-11-20 13:16:07 +00:00
Daniel Peng d4e8af407c spd/lp4x: Add CXMT CXDB5CBAM-MA-B memory 
Generate initial SPD matched for CXMT CXDB5CBAM-MA-B.

BUG=b:451917928
TEST=1. make -C util/spd_tools
     2. util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Ib071aacd8aae0f22ee3d17544166b39d41f3f476
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89921
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2025-11-06 16:28:14 +00:00
Luca Lai f4af55a008 spd/lp5: Add SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV 
Add  MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV in the
memory_parts.json and re-generate the SPD.

TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I014a847de2d5d53a7895460912c30b45959d3fbc
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
 2025-11-06 13:17:08 +00:00
Hualin Wei 886bd1d186 spd/lp5: Add Samsung K3KLALA0EM-MGCU memory part 
Add Samsung memory part K3KLALA0EM-MGCU in lp5 list.

BUG=438785495
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I4cac57363fdedf9f216b8b01fb5ea091a511ebf2
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89064
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2025-09-24 14:49:31 +00:00
Appukuttan V K f4110cebf6 spd/lp5: Add SPD for H58GE6AK8BX104 
Add  H58GE6AK8BX104 in the memory_parts.json and re-generate
the SPD.

BUG=b:445211686
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I4bf1d0fc3325ec2d4247a0263a44a81934a3a90e
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2025-09-22 15:52:41 +00:00
Varun Upadhyay d1967d927a spd/lp5: Add SPD for MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C 
Add  MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C in the
memory_parts.json and re-generate the SPD.

TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I0db533908fbea2bc04a55191960aaeec8461f47d
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
 2025-09-17 14:09:41 +00:00
Shon Wang 16318a32ce spd/lp5x: Generate initial SPD for MT62F512M32D1DS-023 WT:E 
Generate initial SPD for MT62F512M32D1DS-023 WT:E

BUG=b:438402880
BRANCH=firmware-nissa-15217.B
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I9c67dadf75b15fc1e0392566be60a776e1ee8a35
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2025-09-02 17:07:07 +00:00
Tony Huang eb749f2416 spd/lp5: Add SPD for MT62F2G32D4DS-023 WT:C 
Add MT62F2G32D4DS-023 WT:C in the memory_parts.json and re-generate the
SPD.

BUG=b:427327667
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I8f244c2f91d66ffcbc1ec2642304f77b522da09f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
 2025-06-28 16:24:28 +00:00
Hualin Wei 912161e52d spd/lp4x: Modify parameters of SPD for NT6AP1024F32BL-J1 
According to the latest SPD parameters provided by the manufacturer,
combined with the document 8Gb_LPDDR4X_B_Die_component_Datasheet(S).pdf
we correct channelsPerDie, diesPerPackage, ranksPerChannel of SPD
for Nanya NT6AP1024F32BL-J1; merged the parameters into the BIOS and
flashed it into the machine. The machine can boot and read the normal
size of memory.

BUG=b.422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x
     Use the dmidecode -t memory command to read the size of memory.

Output results：
awasuki-rev2  # dmidecode -t memory
# dmidecode 3.4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.

Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
	Location: System Board Or Motherboard
	Use: System Memory
	Error Correction Type: None
	Maximum Capacity: 64 GB
	Error Information Handle: Not Provided
	Number Of Devices: 4

Handle 0x000B, DMI type 17, 40 bytes
Memory Device
	Array Handle: 0x000A
	Error Information Handle: Not Provided
	Total Width: 32 bits
	Data Width: 32 bits
	Size: 8 GB
	Form Factor: Unknown
	Set: None
	Locator: Channel-0-DIMM-0
	Bank Locator: BANK 0
	Type: LPDDR4
	Type Detail: Synchronous
	Speed: 2933 MT/s
	Manufacturer: Unknown (b03)
	Serial Number: 00000000
	Asset Tag: Not Specified
	Part Number: NT6AP1024F32BL-J1
	Rank: 2
	Configured Memory Speed: 2933 MT/s
	Minimum Voltage: 0.6 V
	Maximum Voltage: 0.6 V
	Configured Voltage: 0.6 V

Change-Id: I35823ce87b5d8d67894528e4a8781dd91247eb6c
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88146
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2025-06-24 04:24:34 +00:00
Tony Huang e2ac46bcc7 spd/lp5: Add SPD for hynix H58G66CK8BX147 
Add H58G66CK8BX147 in the memory_parts.json and re-generate the SPD.

BUG=b:425545256
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Iab55914d5cc2b188a122d4a1ee4468d0aa759938
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88120
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2025-06-20 02:19:53 +00:00
Shon Wang 57b12d2171 spd/lp4x: Generate initial SPD for B3221XM3BDGVI 
Generate initial SPD for Kingston B3221XM3BDGVI

BUG=b:420797833
BRANCH=firmware-brya-14505.B
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Id411ace4a6d535fcbe5be5317e0ec7fd0052b82f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87881
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2025-06-18 17:35:15 +00:00
Hualin Wei 4ef1258436 spd/lp4x: Add Nanya memory part 
Add Nanya memory part NT6AP1024T32BL-J1 in lp4 list.

BUG=b:422906387
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Ie40c591872fe5d6a0251ca53fb60f3bf8d5c4e84
Signed-off-by: Hualin Wei <weihualin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88004
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
 2025-06-12 02:55:43 +00:00
Zhongtian Wu ac2bd75817 spd/lp5: Add SPD for K3KL9L90EM-MGCU 
Add K3KL9L90EM-MGCU in the memory_parts.json and re-generate the SPD

Samsung:K3KL9L90EM-MGCU

BUG=b:416632273
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I693d52714a3d1846dec1f990ba7d9f23ec5f219f
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
 2025-05-10 22:47:56 +00:00
Rui Zhou 430ab9257b spd/lp5: Add SPD for K3KL8L80EM-MGCU 
Add K3KL8L80DM-MGCU in the memory_parts.json
and re-generate the SPD

Samsung:K3KL8L80EM-MGCU

BUG=b:412237636
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I34c8d8e1fc7b8aa107bc181f51b5dc2ff287aa4c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87395
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2025-04-22 01:47:40 +00:00
Wisley Chen c6754fe0af spd/lp4x: Add Nanya memory part 
Add Nanya memory part NT6AP512T32BL-J1 in lp4 list.

BUG=b:401424949
TEST=util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: I953c09c7d8d2cdd670187c5285ebedfcc66aa021
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
 2025-03-10 15:18:02 +00:00
Roger Wang 9992a98c67 spd/lp5: Add Hynix memory part 
Add Micron memory part H58G56CK8BX146 to LP5 global list.
And Regenerate the SPD files for the SoC. The specification
is attached in issue tracker.

BUG=b:367841051
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I2a003aad32bca9ae5438973ecf0d7872481fee20
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2024-11-30 05:03:59 +00:00
Amanda Huang 2626bcf5f8 spd/lp5: Add SPD for MT62F2G32D4DS-020 WT:F 
Add MT62F2G32D4DS-020 WT:F in the memory_parts.json and re-generate
the SPD

BUG=b:373394046
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: I592cebf972df1e54555561b243eed42af83342e3
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
 2024-10-17 10:05:13 +00:00
Subrata Banik d0d41f28d3 util/spd_tools: Add Intel Panther Lake (PTL) platform 
This patch add support for PTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for fatcat variants.

BUG=b:347669091
TEST=Able to generate SPD for LP5 DRAM part.

Change-Id: I55c3f49439fb1ad961c6866f03594431e54279b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83822
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
 2024-08-09 09:24:18 +00:00
Leo Chou c96f3c24fd spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T 
This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips.

Generatd SPD data with:
util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

BRANCH=None
BUG=344482259

Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2024-06-07 18:36:42 +00:00
Kun Liu aa65c8ed95 spd/lp5: Add SPDs for MT62F1G32D2DS-023 WT:C and K3KL8L80DM-MGCU 
Add MT62F1G32D2DS-023 WT:C and K3KL8L80DM-MGCU
in the memory_parts.json and re-generate the SPD

Micron:MT62F1G32D2DS-023 WT:C
Samsung:K3KL8L80DM-MGCU

BUG=b:337730271
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Change-Id: Ic5c3ed46829330f83e144cf8d18be6fa808431aa
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2024-06-07 15:59:38 +00:00
Daniel Peng 9a01263952 spd/lp4x: Add SPD for CXDB4CBAM-ML-A in parts_spd_manifest.generated.txt 
Generate initial SPD matched for CXMT CXDB4CBAM-ML-A.

BUG=b:304932936
TEST=make -C util/spd_tools
     util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x

Change-Id: Ia33a94a1784f865b4776ad9107e25e87420f944f
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78891
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2023-11-13 06:16:55 +00:00