Commit Graph
39 Commits
Author SHA1 Message Date
Michał Żygowski 4bc79fddc6 vc/amd/opensil/turin_poc/opensil: Bump submodule for BRHD support
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2026-06-12 11:57:08 +02:00
Michał Żygowski 2747cac191 vc/amd/opensil/phoenix_poc/opensil: Use 3mdeb fork
Temporarily use 3mdeb fork to fix build issues and other bugs.

Change-Id: I4de3f001d335ebf1621f30bb1aa875a7d22c4168
Upstream-Status: Inappropriate [temporary submodule chnage]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2026-04-08 18:05:40 +02:00
Alicja Michalska a033bf5842 vc/amd/opensil: Add Phoenix OpenSIL POC directory structure
Based on genoa_poc, this patch adds directory structure for Phoenix
OpenSIL as well as git submodule needed to build it.

Subsequent patches will begin adjusting this directory to Phoenix (Zen4)
silicon.

Upstream-Status: Backport [CB:91480]
Change-Id: I04de276c1567c20d1e852efe220efa8131f53843
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
2026-04-08 18:05:39 +02:00
Michał Kopeć c08dadaca6 3rdparty/dasharo-blobs: add submodule
Change-Id: I7ed25d7f43396330079bb51ab9fc156957efd2b6
Upstream-Status: Inappropriate [Dasharo downstream]
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2026-04-08 17:40:45 +02:00
Michał Żygowski a5cdc9a1bc vendorcode/amd/opensil: Add Turin OpenSIL
Add Turin OpenSIL driver and submodule.

Change-Id: Idd6d4e78a055926061de330da620c943b42a50a7
Upstream-Status: Backport [CB:88711]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2026-04-08 17:39:43 +02:00
Michał Żygowski fc91f944ed soc/amd/turin_poc: Fill in amdfwtool configuration
Pass the eSPI configuration to the amdfwtool to	be filled in EFS.

Update the Turin SOC fw.cfg file with the blobs from
openSIL/amd_firmwares repository on GitHub. Create a new submodule
to source these blobs into the build.

Unfortunately these blobs are rather not suitable for production CPUs.
See this issue: https://github.com/openSIL/amd_firmwares/issues/1

TEST=Build image for Gigabyte MZ33-AR1.

Change-Id: Ic30fad7a4d95dc20f05d3ce94a23dc39b28eb746
Upstream-Status: Backport [CB:88710]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2026-04-08 17:39:43 +02:00
Martin Roth 85da3954d0 .gitmodules: Ignore changes make by what-jenkins-does
When running `make what-jenkins-does`, the intel-sec-tools and gowsid
submodules are left with some new files, marking them as dirty.
This changes fixes that.

Change-Id: Ice98c1a61201cbf63580835966b78f053d7853a2
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87380
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2025-07-17 20:38:35 +00:00
Michał Żygowski b14ec5fbab 3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER
Signing is performed with test keys by default, set
CONFIG_SIGNING_KEYS_DIR to a non-empty value to use other keys.

Depending on the version of the Talos II firmware this alone might not
allow booting because coreboot replaces only part of the stock firmware
and its newer versions enable secure boot by default (not to be confused
with SecureBoot in EFI).  The signing performed in this commit is still
a prerequisite and might as well be done on its own.  Fixing operation
with newer stock firmware will be done in a follow-up change.

Change-Id: Id88baef5ecb1f8ffd74a7f464bbbaaaea0ca643d
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-09-06 13:55:50 +00:00
Martin Roth 28c669e216 3rdparty: Remove chromeec submodule
The chromeec submodule is the largest submodule being pulled into the
coreboot tree, at over 400MB. The main branch also contains the majority
of these commits, so restricting it to a single branch still fetches
over 350MB.

Because there is only a single mainboard directory that enables the
build of the chromeec codebase by default, most people are fetching this
repo for no reason.

Based on this, we're going to change the way that the chromeec submodule
is used, fetching it the way we currently fetch external payloads. This
gives us 2 large advantages:
1) Only builds that actually need the chromeec repo will pull it down.
2) Each board that wants to build the chromeec codebase can use a
different commit, unlike submodules which all use the same "current"
commit.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I357c4c9b506dd3817a308232446144ae889bc220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-07-26 04:36:52 +00:00
Martin Roth bbac6b9f8a .gitmodules: Use https to fetch modules
Instead of using a relative path for the submodules, specify the sub-
module URLs as pointing at coreboot.org, using https.

While the relative path works well for coreboot itself, when the repo
is forked and fetched from from anywhere other than review.coreboot.org,
this file either needs to be modified, or all the submodules need to be
checked out as well.

Change-Id: Ie4f95c70a7f194d1073dc561c9f33dcc108060cc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-15 11:48:04 +00:00
Martin Roth f9bc2c4699 vc/amd/opensil/genoa_poc/openSIL: Add openSIL code as submodule
This is a RW mirror of AMD's openSIL for Genoa with additions from
Arthur Heymans.

- origin/openSIL/main from
https://github.com/openSIL/openSIL.git

- origin/ArthurHeymans/64b_public from
https://github.com/ArthurHeymans/openSIL.git

The current main branch starts with Arthur's branch and adds 5 commits
from the AMD's openSIL repo.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8917edf3a6a8493ffa9230902cafcc6234d3d571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-07 08:37:42 +00:00
Maximilian Brune c5f16c9f0d Revert ".gitmodules: Fix submodule revision to v0.1 tag"
This reverts commit 59a1a30ae1.

git submodule updates currently break, since apparently you can't use
git tags in the .gitmodules file.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibbc2bee21a723bd6d602ca435cada1dc0da03091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-16 05:18:27 +00:00
Maximilian Brune 59a1a30ae1 .gitmodules: Fix submodule revision to v0.1 tag
The goswid tool gets a rework and this shouldn't break coreboot builds. Therefore, a v0.1 tag was created to tie coreboot to a known working commit of goswid.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9d14f7653465c6b9e72dd3661e991d13b76c24c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-01-11 18:58:43 +00:00
Maximilian Brune 1d7a9debf2 Add SBOM (Software Bill of Materials) Generation
Firmware is typically delivered as one large binary image that gets
flashed. Since this final image consists of binaries and data from
a vast number of different people and companies, it's hard to
determine what all the small parts included in it are. The goal of
the software bill of materials (SBOM) is to take a firmware image
and make it easy to find out what it consists of and where those
pieces came from. Basically, this answers the question, who supplied
the code that's running on my system right now? For example, buyers
of a system can use an SBOM to perform an automated vulnerability
check or license analysis, both of which can be used to evaluate
risk in a product. Furthermore, one can quickly check to see if the
firmware is subject to a new vulnerability included in one of the
software parts (with the specified version) of the firmware.
Further reference:
https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/

- Add Makefile.inc to generate and build coswid tags
- Add templates for most payloads, coreboot, intel-microcode,
  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
  intel ME and compiler (gcc,clang,other)
- Add Kconfig entries to optionally supply a path to CoSWID tags
  instead of using the default CoSWID tags
- Add CBFS entry called SBOM to each build via Makefile.inc
- Add goswid utility tool to generate SBOM data

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-22 14:48:46 +00:00
Jakub Czapiga c91b55a201 tests: update CMocka to stable-1.1
CMocka stable-1.1 has some convenience bugfixes like vprint buffer
increase or leftover values log fix (funtion names display correctly
now.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I20ebd15324a21c17cccd2976ae9c3f86b040426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-19 13:00:36 +00:00
Werner Zeh bc1445392f .gitmodules: Update intel-microcode submodule to track branch=main
The 3rdparty submodule 'intel-microcode' has changed the branch from
'master' to 'main'. As we do not set any specific branch name in our
config, it defaults to 'master' which makes
"git submodule update --remote --rebase 3rdparty/intel-microcode"
to fail.

This patch adds the branch name in .gitmodules to match the upstream
name.

Change-Id: I7b6d7921a21af4eb3bcc7ce4e5a8ea21c38c89a3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55304
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
2021-06-09 17:20:50 +00:00
Balaji Manigandan B 8aef56ab3b .gitmodules: update vboot submodule to track branch=main
vboot has been updated to track main branch, however the
.gitmodules defaults to master branch following the
coreboot default. This impacts the rebase of submodule
git submodule update --remote --rebase 3rdparty/vboot/

With this change the rebase to latest commit is successful

Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Change-Id: I7713aecdec43a5d5623ef81803ac0fc02ce14070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52664
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:33:07 +00:00
Eugene D Myers 61a77d6fcc 3rdparty: Add STM as a submodule
The patch incorporates the STM build as a part of the coreboot
build.  A separate patch lists and documents the options that
the developer can use.  In most cases the default options will
suffice.

Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796
Signed-off-by: Eugene D Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2020-09-30 10:17:03 +00:00
Philipp Deppenwiese 404a42bb3a 3rdparty: Add submodule intel-sec-tools
Project: https://github.com/9elements/converged-security-suite
License: BSD-3

Tooling for Intel platform security features

Change-Id: I7421b30eb38e64cf6b77b7e1c485c5700728997b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09 13:08:25 +00:00
Julius Werner bc1cb38ce1 Add qc_blobs repository
This patch adds a separate blobs repository for Qualcomm blobs,
analogous to the existing AMD blobs. Qualcomm's binary licenses allow
files to be redistributed and used by anyone, but they explicitly
require the user to agree to the license terms when just *downloading*
the binary (even if they're not using them to build any firmware). Some
community members do not like to have to agree to licenses for files
they're not actually using, so we are keeping these files separate from
the main blobs repository and adding an extra Kconfig to make sure the
user is aware of and must explicitly agree to this before downloading
these files.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I247746c1b633343064c9f32ef1556000475d6c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 08:57:03 +00:00
Jan Dabros 0cbe320ac8 submodules: Add new submodule 3rdparty/cmocka
Cmocka unit testing framework is used for writing and building coreboot
unit tests. This repo will be checked-in only when building some test
targets.

Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I3cdfd32f5bba795d5834ebeae1afff0f7006a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-26 16:20:49 +00:00
Marshall Dawson d9ccaefabe submodules: Add 3rdparty/amd_blobs
This is currently an empty repo.  The intention for amd_blobs may be
found in Documentation/soc/amd/amdblobs_license.md.  A subsequent
patch will make the repo's init and checkout optional based on a
Kconfig symbol.

Change-Id: Ia93fb2711beaea4cb1c8e5d71dc3a9e0facc5485
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-31 12:28:38 +00:00
Marty E. Plummer 1e02d73c73 3rdparty/ffs: add open-power ffs utils
These tools are used to manipulate open-power specific partitioning and
ecc algorithms.

Change-Id: I0657f76aab75190244d0e81c2b1a525e50af484d
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35007
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-25 07:37:11 +00:00
zaolin 15110f12cb Add intel-microcode submodule repository
Change-Id: Icc5ac0a8033e371ecf2b4b28ba45dab961e86b3f
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-06-18 10:42:17 +00:00
zaolin 29035f3c36 3rdparty/opensbi: Add submodule
* Add opensbi for RISC-v

Change-Id: I1a6baa6b6c05095ff5545492aabf7408a23af181
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-24 08:46:25 +00:00