Pass AMD GOP EFI driver and VBIOS file to EDK2 build system to
be integrated in the DXE FV. The PciPlatformDriver will fetch
the VBIOS from FV for given PCI device ID and vendor ID passed
in the VGA_BIOS_ID Konfig option as PCDs.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add USB controller tuning settings and OC pin map based on registers
dumped from vendor BIOS.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This reverts commit 515d5ba0cd.
Upstream-Status: Inappropriate [revert of non-upstream commit]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Update the initialization of FCH IP blocks in Phoenix openSIL.
The submodule is also bumped and contains missing initialization
of FCH USB.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Re-generate defconfigs after rebase so that GH Action checks pass.
Upstream-Status: Inappropriate [custom configs]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Until dasharo-25.12 becomes the main dasharo branch, the upstream
status hook will always fail to find common base with origin/dasharo
branch. Avoid this by setting the base tag we started this branch from.
Upstream-Status: Inappropriate [pre-commit configuration]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Code developed for AMD boards had lint issues. Those will be fixed
when they will be submitted upstream.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Fix compilation errors due to being out of sync with upstream and
rebase mistakes.
Upstream-Status: Inappropriate [rebase mistakes]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Split the IBBS structure further to avoid flex-array-member-not-at-end
errors during compilation. IBBS has a lot of variable length fields
and the compilation fails if these fields are not at the end of the
structure.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The COREBOOT toolchain has been dropped in EDK2 paylaod builds
in CB:84353. The GCC toolchain is used, which breaks the paths
to the EDK2 build artifacts.
Upstream-Status: Inappropriate [custom script]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The root port enables have been dropped in CB:79918. The devicetree
change has been lost after rebase.
Upstream-Status: Backport [CB:79918]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Use common AMD_FWM_POSITION Kconfig option to place the apu/amdfw
CBFS file. It also fixes the build issue where the apu/amdfw
could not fit into COREBOOT region at the end of build.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Due to the changes for newer SOCs to PCI IRQ routing and ROM Armor,
the generic code stopped working on binaryPI. Make necessary changes
to make the common code usable again.
Upstream-Status: Inappropriate [custom changes to PI to make SPI work]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Select AZALIA_USE_LEGACY_VERB_TABLE so that the old verb tables
compile properly.
Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Hook up Energy Efficient Turbo to devicetree so it can be configured.
The default value of 0 will ensure this doesn't change existing boards.
Change-Id: I58a9877371ec66e71cee15aced2413a282416b5c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86855
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upstream-Status: Backport [CB:86855]
Add EnableTcssCovTypeA and MappingPchXhciUsbA to repurpose the
integrated USB Type-C subsystem (TCSS) ports to USB3.2 Gen2x1 Type-A.
For example, to enable port 1 to be configured as USB Type-A, add the
following code in overridetree.cb:
register "enabletcsscovtypea[1]" = "true"
register "mappingpchxhciusba[1]" = "2"
AP log:
[SPEW ] EnableTcssCovTypeA[0]= 0x00000000
[SPEW ] MappingPchXhciUsbA[0]= 0x00000000
[SPEW ] EnableTcssCovTypeA[1]= 0x00000001
[SPEW ] MappingPchXhciUsbA[1]= 0x00000002
Reference document:
742076_ADL_TypeA_Repurpose_TCSS_Ports_USB3p2_Gen2x1_TWP_Rev1p2.pdf
BUG=b:400809281
TEST=Able to build and boot google/Riven
Change-Id: I3684fdf23706cec86c6da2b409aa4fbb33f4ec2e
Signed-off-by: Lawrence <lawrence.chang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86781
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upstream-Status: Backport [CB:86781]
It doesn't make sense to use CONFIG_DIMM_SPD_SIZE to determine the
amount of data to read from the SPD, then override that value.
Clean up the mess and simply set the SPD length fror the spd_block
struct to CONFIG_DIMM_SPD_SIZE.
Change-Id: Ifec6cf1f6d7c931131460ea72440aa236590d0b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88523
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upstream-Status: Backport [CB:88523]
Using stable commit on our fork fixes the build with newer
coreboot-sdk.
Upstream-Status: Inappropriate [custom configs]
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Michał Żygowski
Sean Rhodes
Lawrence
Matt DeVillier