mirror of
https://github.com/Dasharo/coreboot.git
synced 2026-06-13 10:16:48 -07:00
mb/emulation/qemu-q35: don't select CONFIG_UNKNOWN_TSC_RATE
This option signifies missing implementation of tsc_freq_mhz() which results in tsc_freq_mhz() from src/arch/x86/timestamp.c returning zero. That zero in turn gets put into TIMESTAMP CBMEM table requiring payloads and user-space tools to figure out the frequency on their own. Implement tsc_freq_mhz() to query timer frequency in coreboot, so it gets reported downstream. Change-Id: I88d1206c13f15a9f20c07b65dcec42ec614f7e6a Upstream-Status: Pending Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
This commit is contained in:
@@ -6,7 +6,6 @@ config CPU_QEMU_X86
|
||||
select HAVE_X86_64_SUPPORT
|
||||
select UDELAY_TSC
|
||||
select TSC_MONOTONIC_TIMER
|
||||
select UNKNOWN_TSC_RATE
|
||||
select NEED_SMALL_2MB_PAGE_TABLES # QEMU doesn't support 1GB pages
|
||||
select IDT_IN_EVERY_STAGE
|
||||
|
||||
|
||||
@@ -18,9 +18,11 @@ ramstage-y += cpu.c
|
||||
|
||||
all-y += ../qemu-i440fx/fw_cfg.c
|
||||
all-y += ../qemu-i440fx/bootmode.c
|
||||
all-y += timer.c
|
||||
|
||||
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
|
||||
|
||||
smm-y += ../qemu-i440fx/rom_media.c
|
||||
smm-y += memmap.c
|
||||
smm-y += smihandler.c
|
||||
smm-y += timer.c
|
||||
|
||||
@@ -0,0 +1,9 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <cpu/x86/tsc.h>
|
||||
|
||||
unsigned long tsc_freq_mhz(void)
|
||||
{
|
||||
/* ACPI's Power Management Timer frequency is fixed at 3.579545 MHz. */
|
||||
return 3579545 / 1000000;
|
||||
}
|
||||
Reference in New Issue
Block a user