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mb/novacustom/nuc_box/var/nuc_box/ramstage.c: Disable clock/power gating on 2nd M.2

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Needed for PCI2USB card to be detected after D3.

Upstream-Status: Pending
Change-Id: Icbc81b65df4cc1a6a00faa599fc7286aa17ea745
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
This commit is contained in:
Michał Kopeć
2026-06-12 10:30:02 +02:00
parent 4bacfe77f5
commit 519898c221
1 changed files with 5 additions and 0 deletions
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src/mainboard/novacustom/nuc_box/variants/nuc_box/ramstage.c
+5
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@@ -15,4 +15,9 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
// XXX: Enabling C10 reporting causes system to constantly enter and
// exit opportunistic suspend when idle.
params->PchEspiHostC10ReportEnable = 1;
// Disable PCIe power gating on the RP that does not have a clock request
// connected. Otherwise, the connected device will fail after exiting D3.
params->PciePowerGating[9] = false;
params->PcieClockGating[9] = false;
}