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vc/amd/opensil/turin_poc: Hook up SATA settings from devicetree

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Some SATA settings should be board specific. Add relevant SATA settings
to chip config, so the mainboards may set them per the board design.

TEST=SATA ports working on Gigabyte MZ33-AR1 in EDK2 payload, Linux
and Windows.

Upstream-Status: Pending
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Michał Żygowski
2026-03-30 10:53:22 +02:00
parent 3bfc1f12c0
commit 0b9dfd03ff
3 changed files with 47 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mainboard/gigabyte/mz33-ar1/devicetree.cb
+8
View File
@@ -23,6 +23,14 @@ chip soc/amd/turin_poc
register "usb.usb3_force_gen1.port0" = "3"
register "usb.usb3_force_gen1.port1" = "3"
# Shutdown all unused SATA0 and SATA1 ports
register "sata.shutdown_ports[0].raw" = "0xff"
register "sata.shutdown_ports[1].raw" = "0xff"
# Enable all SATA2 and SATA3 ports as eSATA
register "sata.enable_esata[2].raw" = "0xff"
register "sata.enable_esata[3].raw" = "0xff"
# eSPI configuration
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN,
src/soc/amd/turin_poc/chip.h
+23
View File
@@ -54,6 +54,28 @@ struct soc_usb_config {
struct usb31_phy_settings s1_usb31_phy[2];
};
union sata_ports {
struct {
uint8_t port0 : 1;
uint8_t port1 : 1;
uint8_t port2 : 1;
uint8_t port3 : 1;
uint8_t port4 : 1;
uint8_t port5 : 1;
uint8_t port6 : 1;
uint8_t port7 : 1;
};
uint8_t raw;
};
struct soc_sata_config {
union sata_ports shutdown_ports[4];
union sata_ports enable_esata[4];
union sata_ports rx_polarity[4];
bool sgpio0_enable[4];
bool sgpio1_enable[4];
};
struct soc_amd_turin_poc_config {
struct soc_amd_common_config common_config;
@@ -61,6 +83,7 @@ struct soc_amd_turin_poc_config {
struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
struct soc_usb_config usb;
struct soc_sata_config sata;
};
#endif /* __TURIN_POC_CHIP_H__ */
src/vendorcode/amd/opensil/turin_poc/ramstage.c
+16 -13
View File
@@ -200,26 +200,29 @@ static void configure_usb(void)
static void configure_sata(void)
{
FCHSATA_INPUT_BLK *fch_sata_data = SilFindStructure(SilId_FchSata, 0);
FCHSATA_INPUT_BLK *fch_sata_defaults = FchSataGetInputBlk();
struct device *sata[NUM_SATA_CONTROLLERS] = {
DEV_PTR(sata_2_0),
DEV_PTR(sata_2_1),
const struct soc_amd_turin_poc_config *soc_config = config_of_soc();
const struct soc_sata_config *sata = &soc_config->sata;
struct device *sata_devs[NUM_SATA_CONTROLLERS] = {
DEV_PTR(sata_7_0),
DEV_PTR(sata_7_1)
DEV_PTR(sata_7_1),
DEV_PTR(sata_2_0),
DEV_PTR(sata_2_1)
};
for (int i = 0; i < NUM_SATA_CONTROLLERS; i++) {
fch_sata_data[i] = fch_sata_defaults[i];
fch_sata_data[i].SataAhciSsid = (sata[i])->subsystem_vendor |
((uint32_t)((sata[i])->subsystem_device) << 16);
fch_sata_data[i].SataEnable = is_dev_enabled(sata_devs[i]);
fch_sata_data[i].SataAhciSsid = (sata_devs[i])->subsystem_vendor |
((uint32_t)((sata_devs[i])->subsystem_device) << 16);
fch_sata_data[i].SataSetMaxGen2 = false;
fch_sata_data[i].SataMsiEnable = true;
fch_sata_data[i].SataEspPort = 0xFF;
fch_sata_data[i].SataRasSupport = true;
fch_sata_data[i].SataDevSlpPort1Num = 1;
fch_sata_data[i].SataMsiEnable = true;
fch_sata_data[i].SataControllerAutoShutdown = true;
fch_sata_data[i].SataRxPolarity = 0xFF;
fch_sata_data[i].SataStaggeredSpinupEnable = true;
fch_sata_data[i].SataRxPolarity = sata->rx_polarity[i].raw;
fch_sata_data[i].SataPortPower = sata->shutdown_ports[i].raw;
fch_sata_data[i].SataEspPort = sata->enable_esata[i].raw;
fch_sata_data[i].SataSgpio0 = sata->sgpio0_enable[i];
fch_sata_data[i].SataSgpio1 = sata->sgpio1_enable[i];
}
}