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tests: cover Q/P instance rotation across a branch
The VU's Q and P scalars are double-buffered, and microVU keeps both buffers live in one host vector. When a DIV or an EFU op's latency expires mid-block the current instance flips, but every compiled block is entered assuming instance #0 — so a branch out of that block has to physically swap the two lanes first. Nothing in the suite had ever branched with a Q or P value in flight, so that swap was unreached. A dropped swap is silent: the target block reads the previous quotient, which is an ordinary float that propagates through the rest of the microprogram. Each case therefore seeds the stale buffer with a distinct sentinel and asserts the absolute post-branch value — a JIT-vs-interp diff alone would also pass if the swap were dropped on both sides. Also covers mVUendProgram's division-flag transfer, which only runs when the program ends inside the FDIV flag latency. Every other Q test drains the pipe with VWAITQ first, so that path had never run either. STATUS is opted out of the cross-engine diff there: the console captures already settled that the sticky D/I bits accumulate, which microVU does and the shared interpreter does not (vu_sticky_console_conformance_tests.cpp). Mutation-checked: neutralising the Q swap fails exactly the three Q cases, the P swap exactly the P case, and dropping the end-program mVUdivSet exactly the two flag cases.
This commit is contained in:
Brian Degenhardt
@@ -88,6 +88,7 @@ add_pcsx2_test(recompiler_tests
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vu_madda_acc_lane_tests.cpp
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vu_broadcast_lane_tests.cpp
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vu_minmax_order_tests.cpp
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vu_pq_boundary_tests.cpp
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vu_overflow_hack_tests.cpp
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vu_mac_flag_pack_tests.cpp
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ee_vu0_cfc2_ctc2_tests.cpp
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@@ -0,0 +1,259 @@
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// SPDX-FileCopyrightText: 2026 yaps2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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// Q/P pipeline state across a BLOCK BOUNDARY — branches and end-of-program.
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//
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// The behavioural model this suite exists for:
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//
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// The VU's Q and P scalars are double-buffered. While a DIV/SQRT/RSQRT (Q) or
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// an EFU op (P) is in flight, the architectural value a reader sees and the
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// slot the producer will land in are two different registers. microVU tracks
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// which of the two is "current" per compiled instruction as mVU.q / mVU.p, and
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// keeps both live in one host vector — qmmPQ lane 0 = Q, lane 1 = pending_q,
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// lane 2 = P, lane 3 = pending_p.
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//
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// Every compiled block, however, is entered assuming instance #0. So when a
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// producer's latency expires mid-block, the instance flips, and any branch out
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// of that block must physically swap the two lanes before the jump — otherwise
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// the target block reads the stale buffer and the whole program computes with
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// the PREVIOUS quotient. That swap (mVUsetupBranch, microVU_Branch-arm64.inl)
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// had no test coverage at all: nothing in the suite had ever branched with a
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// Q or P value in flight.
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//
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// The failure mode is silent and plausible: a stale Q is a real float that
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// propagates through the rest of the microprogram. So each test seeds the
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// pre-branch Q/P with a distinctive sentinel and asserts the ABSOLUTE
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// post-branch value, not just JIT-vs-interp agreement — a diff alone would
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// also pass if the swap were dropped on both sides, and a sentinel-free test
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// would pass if the two buffers happened to hold the same number.
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//
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// The end-of-program half covers the other boundary: mVUendProgram's
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// division-flag transfer, which only runs when the program ends while the
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// DIV's flag latency is still outstanding. That is the case the older
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// Vu0Qpipe tests deliberately avoid (they drain with VWAITQ first), so it too
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// was unreached.
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#include "harness/VuTestHarness.h"
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#include "VU.h"
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#include <gtest/gtest.h>
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#include <bit>
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namespace recompiler_tests {
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using namespace vu;
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namespace {
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inline VuOp LowerOnly(u32 lower) { return VuOp{lower, VNOP_U()}; }
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inline VuOp UpperOnly(u32 upper) { return IBit(VuOp{VLitZero(), upper}); }
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// I-bit set so the zero lower word is the VI[REG_I] immediate rather than
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// decoding as `LQ vf0` — the canonical NOP-pair idiom.
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inline VuOp Nop() { return IBit(VuOp{VLitZero(), VNOP_U()}); }
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// DIV/SQRT latency is 7 cycles (microVU_Lower-arm64.inl, mVUanalyzeFDIV);
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// ESADD's EFU latency is 11. Padding by exactly the latency puts the
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// instance flip immediately before the branch, which is the state under test.
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constexpr int kDivLatency = 7;
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constexpr int kEsaddLatency = 11;
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// Sentinels: what a dropped lane swap would leave behind. Chosen far from
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// every computed result so a stale read is unmistakable in the failure text.
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constexpr float kStaleQ = 1000.0f;
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constexpr float kStaleP = 500.0f;
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void PushNops(std::vector<VuOp>& prog, int count)
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{
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for (int i = 0; i < count; i++)
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prog.push_back(Nop());
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}
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} // namespace
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// =========================================================================
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// Q instance across a branch — mVUsetupBranch's lane-0/1 swap
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// =========================================================================
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TEST(VuPqBoundary, QInstanceSurvivesUnconditionalBranch)
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{
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// vf1.x / vf2.x = 6/2 = 3. The quotient lands in the pending buffer, the
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// instance flips as its latency expires, and the branch must carry it into
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// lane 0 for the target block to read.
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VuTestHarness h(0);
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h.SetQ(std::bit_cast<u32>(kStaleQ));
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h.SetVf(vf::vf1, 6.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf2, 2.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf6, 10.0f, 10.0f, 10.0f, 10.0f); // addend on the taken side
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h.SetVf(vf::vf7, -50.0f, -50.0f, -50.0f, -50.0f); // addend on the skipped pair
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std::vector<VuOp> prog;
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prog.push_back(LowerOnly(VDIV_L(vf::vf1, /*fsf=*/0, vf::vf2, /*ftf=*/0)));
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PushNops(prog, kDivLatency);
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prog.push_back(LowerOnly(VB_L(+2))); // branch over the poison pair
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prog.push_back(Nop()); // delay slot
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prog.push_back(UpperOnly(VADDq_U(mask::xyzw, vf::vf5, vf::vf7))); // skipped
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prog.push_back(UpperOnly(VADDq_U(mask::xyzw, vf::vf5, vf::vf6))); // target
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prog.push_back(EBitNopPair());
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h.LoadProgram(std::move(prog));
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h.Run();
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// 10 + 3 == 13. A dropped lane swap reads the seeded Q instead: 10 + 1000.
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// Landing on the skipped pair instead would give -50 + 3.
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EXPECT_FLOAT_EQ(h.GetVfJit(vf::vf5, 'x'), 13.0f)
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<< "target block read the wrong Q buffer across the branch";
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EXPECT_FLOAT_EQ(std::bit_cast<float>(h.GetViJit(REG_Q)), 3.0f);
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}
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TEST(VuPqBoundary, QInstanceSurvivesConditionalBranchTaken)
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{
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VuTestHarness h(0);
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h.SetQ(std::bit_cast<u32>(kStaleQ));
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h.SetVf(vf::vf1, 9.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf2, 4.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf6, 1.0f, 1.0f, 1.0f, 1.0f);
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h.SetVf(vf::vf7, -50.0f, -50.0f, -50.0f, -50.0f);
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h.SetVi(vi::vi1, 0); // IBEQ vi1, vi0 => taken
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std::vector<VuOp> prog;
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prog.push_back(LowerOnly(VDIV_L(vf::vf1, 0, vf::vf2, 0)));
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PushNops(prog, kDivLatency);
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prog.push_back(LowerOnly(VIBEQ_L(vi::vi1, vi::vi0, +2)));
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prog.push_back(Nop());
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prog.push_back(UpperOnly(VADDq_U(mask::xyzw, vf::vf5, vf::vf7))); // not-taken side
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prog.push_back(UpperOnly(VADDq_U(mask::xyzw, vf::vf5, vf::vf6))); // taken target
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prog.push_back(EBitNopPair());
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h.LoadProgram(std::move(prog));
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h.Run();
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EXPECT_FLOAT_EQ(h.GetVfJit(vf::vf5, 'x'), 3.25f); // 1 + 9/4
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EXPECT_FLOAT_EQ(std::bit_cast<float>(h.GetViJit(REG_Q)), 2.25f);
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}
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TEST(VuPqBoundary, QInstanceSurvivesConditionalBranchNotTaken)
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{
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// The not-taken side of a conditional branch is a separate emit path
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// (condBranch compiles the fall-through inline and patches the taken
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// target), so it needs its own case: the swap must have happened before
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// EITHER successor runs.
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VuTestHarness h(0);
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h.SetQ(std::bit_cast<u32>(kStaleQ));
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h.SetVf(vf::vf1, 9.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf2, 4.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf6, 1.0f, 1.0f, 1.0f, 1.0f);
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h.SetVf(vf::vf7, -50.0f, -50.0f, -50.0f, -50.0f);
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h.SetVi(vi::vi1, 1); // IBEQ vi1, vi0 => not taken
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std::vector<VuOp> prog;
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prog.push_back(LowerOnly(VDIV_L(vf::vf1, 0, vf::vf2, 0)));
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PushNops(prog, kDivLatency);
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prog.push_back(LowerOnly(VIBEQ_L(vi::vi1, vi::vi0, +4)));
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prog.push_back(Nop());
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prog.push_back(UpperOnly(VADDq_U(mask::xyzw, vf::vf5, vf::vf6))); // not-taken side
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prog.push_back(EBitNopPair()); // ends the not-taken path
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prog.push_back(Nop()); // its E-bit delay slot
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prog.push_back(UpperOnly(VADDq_U(mask::xyzw, vf::vf5, vf::vf7))); // taken target
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prog.push_back(EBitNopPair());
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h.LoadProgram(std::move(prog));
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h.Run();
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EXPECT_FLOAT_EQ(h.GetVfJit(vf::vf5, 'x'), 3.25f);
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EXPECT_FLOAT_EQ(std::bit_cast<float>(h.GetViJit(REG_Q)), 2.25f);
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}
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// =========================================================================
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// P instance across a branch — mVUsetupBranch's lane-2/3 swap. VU1 only:
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// VU0 has no EFU, so P never goes in flight there.
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// =========================================================================
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TEST(VuPqBoundary, PInstanceSurvivesBranchOnVu1)
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{
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// ESADD sums the squares of xyz into P: 3² + 4² + 0² = 25.
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VuTestHarness h(1);
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h.SetP(std::bit_cast<u32>(kStaleP));
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h.SetVf(vf::vf1, 3.0f, 4.0f, 0.0f, 99.0f);
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h.SetVf(vf::vf7, -1.0f, -1.0f, -1.0f, -1.0f);
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std::vector<VuOp> prog;
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prog.push_back(LowerOnly(VESADD_L(vf::vf1)));
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PushNops(prog, kEsaddLatency);
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prog.push_back(LowerOnly(VB_L(+2)));
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prog.push_back(Nop());
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prog.push_back(LowerOnly(VMOVE_L(mask::xyzw, vf::vf5, vf::vf7))); // skipped
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prog.push_back(LowerOnly(VMFP_L(mask::xyzw, vf::vf5))); // target: vf5 = P
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prog.push_back(EBitNopPair());
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h.LoadProgram(std::move(prog));
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h.Run();
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EXPECT_FLOAT_EQ(h.GetVfJit(vf::vf5, 'x'), 25.0f)
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<< "target block read the wrong P buffer across the branch";
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EXPECT_FLOAT_EQ(std::bit_cast<float>(h.GetViJit(REG_P)), 25.0f);
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}
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// =========================================================================
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// End-of-program division-flag transfer
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//
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// A DIV raises its invalid/divide-by-zero bits into a side latch, and they
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// reach the architectural STATUS flag only when the instruction 7 cycles
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// downstream commits them. If the program ENDS inside that window there is
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// no such instruction, so mVUendProgram runs the transfer itself. Programs
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// that drain the pipe with VWAITQ first (every other Q test in the suite)
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// never reach it.
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//
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// STATUS is opted out of the cross-engine diff here, not because the answer
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// is unknown but because it is already settled the other way round: the
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// console captures show the sticky D/I bits accumulate, which microVU does
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// and the shared interpreter does not (see
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// vu_sticky_console_conformance_tests.cpp, kMicroDivergences). So the JIT is
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// the side worth asserting, and its cause bit is the observable that proves
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// the end-of-program transfer ran at all.
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// =========================================================================
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TEST(VuPqBoundary, DivByZeroFlagReachesStatusWhenProgramEndsInsideLatency)
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{
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// 1.0 / 0.0 — divide-by-zero, STATUS bit 0x20 (D).
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VuTestHarness h(0);
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h.IgnoreViInDiff(REG_STATUS_FLAG);
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h.SetVf(vf::vf1, 1.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf2, 0.0f, 0.0f, 0.0f, 0.0f);
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h.LoadProgram({
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LowerOnly(VDIV_L(vf::vf1, 0, vf::vf2, 0)),
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EBitNopPair(),
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});
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h.Run();
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EXPECT_NE(h.GetViJit(REG_STATUS_FLAG) & 0x20u, 0u)
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<< "mVUendProgram must fold the pending divide-by-zero flag into STATUS "
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"when the program ends before the FDIV flag latency elapses";
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// The quotient itself still has to be committed on the way out.
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EXPECT_EQ(h.GetViJit(REG_Q), 0x7F7FFFFFu);
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}
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TEST(VuPqBoundary, DivInvalidFlagReachesStatusWhenProgramEndsInsideLatency)
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{
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// 0.0 / 0.0 — invalid operation, STATUS bit 0x10 (I). Distinct latch bit
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// from the case above, so it catches a transfer that hard-codes one of them.
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VuTestHarness h(0);
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h.IgnoreViInDiff(REG_STATUS_FLAG);
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h.SetVf(vf::vf1, 0.0f, 0.0f, 0.0f, 0.0f);
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h.SetVf(vf::vf2, 0.0f, 0.0f, 0.0f, 0.0f);
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h.LoadProgram({
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LowerOnly(VDIV_L(vf::vf1, 0, vf::vf2, 0)),
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EBitNopPair(),
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});
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h.Run();
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EXPECT_NE(h.GetViJit(REG_STATUS_FLAG) & 0x10u, 0u)
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<< "mVUendProgram must fold the pending invalid-operation flag into "
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"STATUS when the program ends before the FDIV flag latency elapses";
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EXPECT_EQ(h.GetViJit(REG_Q), 0x7F7FFFFFu);
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}
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} // namespace recompiler_tests
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