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Common: Switch pmovzx/sx to auto SSE/AVX

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This commit is contained in:
TellowKrinkle
2025-08-24 20:16:24 -05:00
committed by TellowKrinkle
parent 7eeb6c7aca
commit d9fc763f82
3 changed files with 49 additions and 23 deletions
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common/emitter/implement/simd_moremovs.h
+7 -7
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@@ -119,36 +119,36 @@ namespace x86Emitter
//
struct xImplSimd_PMove
{
u16 OpcodeBase;
SIMDInstructionInfo info;
// [SSE-4.1] Zero/Sign-extend the low byte values in src into word integers
// and store them in dest.
void BW(const xRegisterSSE& to, const xRegisterSSE& from) const;
void BW(const xRegisterSSE& to, const xIndirect64& from) const;
void BW(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low byte values in src into dword integers
// and store them in dest.
void BD(const xRegisterSSE& to, const xRegisterSSE& from) const;
void BD(const xRegisterSSE& to, const xIndirect32& from) const;
void BD(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low byte values in src into qword integers
// and store them in dest.
void BQ(const xRegisterSSE& to, const xRegisterSSE& from) const;
void BQ(const xRegisterSSE& to, const xIndirect16& from) const;
void BQ(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low word values in src into dword integers
// and store them in dest.
void WD(const xRegisterSSE& to, const xRegisterSSE& from) const;
void WD(const xRegisterSSE& to, const xIndirect64& from) const;
void WD(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low word values in src into qword integers
// and store them in dest.
void WQ(const xRegisterSSE& to, const xRegisterSSE& from) const;
void WQ(const xRegisterSSE& to, const xIndirect32& from) const;
void WQ(const xRegisterSSE& to, const xIndirectVoid& from) const;
// [SSE-4.1] Zero/Sign-extend the low dword values in src into qword integers
// and store them in dest.
void DQ(const xRegisterSSE& to, const xRegisterSSE& from) const;
void DQ(const xRegisterSSE& to, const xIndirect64& from) const;
void DQ(const xRegisterSSE& to, const xIndirectVoid& from) const;
};
} // namespace x86Emitter
common/emitter/simd.cpp
+16 -16
View File
@@ -628,9 +628,9 @@ namespace x86Emitter
const xImplSimd_PInsert xPINSR;
const SimdImpl_PExtract xPEXTR;
static SIMDInstructionInfo nextop(SIMDInstructionInfo op)
static SIMDInstructionInfo nextop(SIMDInstructionInfo op, u32 offset = 1)
{
op.opcode++;
op.opcode += offset;
return op;
}
@@ -698,23 +698,23 @@ namespace x86Emitter
EmitSIMD(IsAligned(src, dst) ? aligned_store : op.unaligned_store, src, src, dst);
}
void xImplSimd_PMove::BW(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase); }
void xImplSimd_PMove::BW(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase); }
void xImplSimd_PMove::BW(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(info, dst, dst, src); }
void xImplSimd_PMove::BW(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(info, dst, dst, src); }
void xImplSimd_PMove::BD(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x100); }
void xImplSimd_PMove::BD(const xRegisterSSE& to, const xIndirect32& from) const { OpWriteSSE(0x66, OpcodeBase + 0x100); }
void xImplSimd_PMove::BD(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info), dst, dst, src); }
void xImplSimd_PMove::BD(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info), dst, dst, src); }
void xImplSimd_PMove::BQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x200); }
void xImplSimd_PMove::BQ(const xRegisterSSE& to, const xIndirect16& from) const { OpWriteSSE(0x66, OpcodeBase + 0x200); }
void xImplSimd_PMove::BQ(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 2), dst, dst, src); }
void xImplSimd_PMove::BQ(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 2), dst, dst, src); }
void xImplSimd_PMove::WD(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x300); }
void xImplSimd_PMove::WD(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase + 0x300); }
void xImplSimd_PMove::WD(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 3), dst, dst, src); }
void xImplSimd_PMove::WD(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 3), dst, dst, src); }
void xImplSimd_PMove::WQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x400); }
void xImplSimd_PMove::WQ(const xRegisterSSE& to, const xIndirect32& from) const { OpWriteSSE(0x66, OpcodeBase + 0x400); }
void xImplSimd_PMove::WQ(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 4), dst, dst, src); }
void xImplSimd_PMove::WQ(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 4), dst, dst, src); }
void xImplSimd_PMove::DQ(const xRegisterSSE& to, const xRegisterSSE& from) const { OpWriteSSE(0x66, OpcodeBase + 0x500); }
void xImplSimd_PMove::DQ(const xRegisterSSE& to, const xIndirect64& from) const { OpWriteSSE(0x66, OpcodeBase + 0x500); }
void xImplSimd_PMove::DQ(const xRegisterSSE& dst, const xRegisterSSE& src) const { EmitSIMD(nextop(info, 5), dst, dst, src); }
void xImplSimd_PMove::DQ(const xRegisterSSE& dst, const xIndirectVoid& src) const { EmitSIMD(nextop(info, 5), dst, dst, src); }
const xImplSimd_MoveSSE xMOVAPS = {
@@ -773,8 +773,8 @@ namespace x86Emitter
{SIMDInstructionInfo(0x15).p66().d().m0f38(), SIMDInstructionInfo(0x4b).d().p66().m0f3a()}, // VPD
};
const xImplSimd_PMove xPMOVSX = {0x2038};
const xImplSimd_PMove xPMOVZX = {0x3038};
const xImplSimd_PMove xPMOVSX = {SIMDInstructionInfo(0x20).p66().m0f38().mov()};
const xImplSimd_PMove xPMOVZX = {SIMDInstructionInfo(0x30).p66().m0f38().mov()};
// [SSE-3]
const xImplSimd_DestRegSSE xMOVSLDUP = {0xf3, 0x12};
tests/ctest/common/x86emitter/codegen_tests_main.cpp
+26
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@@ -370,6 +370,19 @@ TEST(CodegenTests, SSETest)
CODEGEN_TEST(xPBLEND.W(xmm0, xmm1, 0x55), "66 0f 3a 0e c1 55");
CODEGEN_TEST(xPBLEND.VB(xmm1, xmm2), "66 0f 38 10 ca");
CODEGEN_TEST(xPMOVSX.BW(xmm0, ptr[rax]), "66 0f 38 20 00");
CODEGEN_TEST(xPMOVZX.BW(xmm4, ptr[r8]), "66 41 0f 38 30 20");
CODEGEN_TEST(xPMOVSX.BD(xmm3, xmm4), "66 0f 38 21 dc");
CODEGEN_TEST(xPMOVZX.BD(xmm8, xmm3), "66 44 0f 38 31 c3");
CODEGEN_TEST(xPMOVSX.BQ(xmm2, xmm8), "66 41 0f 38 22 d0");
CODEGEN_TEST(xPMOVZX.BQ(xmm8, ptr[rax]), "66 44 0f 38 32 00");
CODEGEN_TEST(xPMOVSX.WD(xmm4, xmm6), "66 0f 38 23 e6");
CODEGEN_TEST(xPMOVZX.WD(xmm6, xmm9), "66 41 0f 38 33 f1");
CODEGEN_TEST(xPMOVSX.WQ(xmm2, ptr[rcx]), "66 0f 38 24 11");
CODEGEN_TEST(xPMOVZX.WQ(xmm5, xmm7), "66 0f 38 34 ef");
CODEGEN_TEST(xPMOVSX.DQ(xmm2, xmm3), "66 0f 38 25 d3");
CODEGEN_TEST(xPMOVZX.DQ(xmm4, xmm9), "66 41 0f 38 35 e1");
CODEGEN_TEST(xMOVD(eax, xmm1), "66 0f 7e c8");
CODEGEN_TEST(xMOVD(eax, xmm10), "66 44 0f 7e d0");
CODEGEN_TEST(xMOVD(rax, xmm1), "66 48 0f 7e c8");
@@ -611,6 +624,19 @@ TEST(CodegenTests, AVXTest)
CODEGEN_TEST(xPBLEND.W(xmm0, xmm1, 0x55), "c4 e3 79 0e c1 55");
CODEGEN_TEST(xPBLEND.VB(xmm1, xmm2), "c4 e3 71 4c ca 00");
CODEGEN_TEST(xPMOVSX.BW(xmm0, ptr[rax]), "c4 e2 79 20 00");
CODEGEN_TEST(xPMOVZX.BW(xmm4, ptr[r8]), "c4 c2 79 30 20");
CODEGEN_TEST(xPMOVSX.BD(xmm3, xmm4), "c4 e2 79 21 dc");
CODEGEN_TEST(xPMOVZX.BD(xmm8, xmm3), "c4 62 79 31 c3");
CODEGEN_TEST(xPMOVSX.BQ(xmm2, xmm8), "c4 c2 79 22 d0");
CODEGEN_TEST(xPMOVZX.BQ(xmm8, ptr[rax]), "c4 62 79 32 00");
CODEGEN_TEST(xPMOVSX.WD(xmm4, xmm6), "c4 e2 79 23 e6");
CODEGEN_TEST(xPMOVZX.WD(xmm6, xmm9), "c4 c2 79 33 f1");
CODEGEN_TEST(xPMOVSX.WQ(xmm2, ptr[rcx]), "c4 e2 79 24 11");
CODEGEN_TEST(xPMOVZX.WQ(xmm5, xmm7), "c4 e2 79 34 ef");
CODEGEN_TEST(xPMOVSX.DQ(xmm2, xmm3), "c4 e2 79 25 d3");
CODEGEN_TEST(xPMOVZX.DQ(xmm4, xmm9), "c4 c2 79 35 e1");
CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");