mirror of
https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
Android: remove the on-device JIT test tree superseded by the in-tree gates
platforms/android/.../cpp/tests/ held ~11,900 lines of EE, microVU, VIF, patch and ARM64 codegen tests, none of which any build compiled. Only the 35-line android_test_stubs.cpp was in the Android CMake, supplying no-op definitions so native-lib's JNI entry points stayed linkable. The tests drive the pre-transplant arm64/mac backend through EE_Test*, mVU0_Test* and mVU1_Test* hooks. Those fourteen symbols exist nowhere in this core, so the suite cannot compile against it. The stub file asked for exactly one thing - "restore the real tests once a compatible test backend is reconciled into this core" - and that reconciliation is what tests/ctest/core/recompilers now provides, alongside pcsx2-vurunner, pcsx2-eerunner and the DiffJitVsInterp harness. Also drops the surface that fed it: six JNI entry points, the ReportTestResults JNI callback, six NativeApp declarations, TestResult.kt and six mutableStateOf holders in MainActivityRuntime that nothing ever read. MainActivityRuntime called runEeJitTests/runEeSeqTests/runVifTests unconditionally during Android init, so every launch made three JNI round trips that only logged "recompiler self-tests are disabled in this build".
This commit is contained in:
Brian Degenhardt
@@ -80,10 +80,6 @@ set(ARMSX2_EMUCORE_LIBRARY_NAME "emucore_4k" CACHE STRING "Android emucore share
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add_library(${ARMSX2_EMUCORE_LIBRARY_NAME} SHARED
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native-lib.cpp
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# Recompiler/VIF/patch unit tests are compiled out: they call the arm64/mac
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# backend test hooks (EE_Test*/mVU0_Test*) not present in this core, plus a
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# gtest scaffold. No-op stubs keep native-lib's dev-only "run tests" JNIs linkable.
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tests/android_test_stubs.cpp
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)
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target_link_libraries(${ARMSX2_EMUCORE_LIBRARY_NAME} PRIVATE
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@@ -6,12 +6,6 @@
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#include <stdio.h>
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#include <mutex>
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#include "PrecompiledHeader.h"
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#include "tests/arm64/run_tests.h"
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#include "tests/core/run_patch_tests.h"
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#include "tests/mvu/run_mvu_tests.h"
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#include "tests/ee/run_ee_tests.h"
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#include "tests/ee/run_ee_seq_tests.h"
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#include "tests/vif/run_vif_tests.h"
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#include "common/StringUtil.h"
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#include "common/FileSystem.h"
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#include "common/ZipHelpers.h"
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@@ -2348,20 +2342,6 @@ bool FileSystem::CreateFileViaJava(const char* path)
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return ok;
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}
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void ReportTestResults(const char* label, int passed, int total)
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{
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auto* env = static_cast<JNIEnv*>(SDL_GetAndroidJNIEnv());
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if (!env) return;
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jclass clazz = env->FindClass("kr/co/iefriends/pcsx2/NativeApp");
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if (!clazz) return;
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jmethodID mid = env->GetStaticMethodID(clazz, "onTestResults", "(Ljava/lang/String;II)V");
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if (!mid) { env->DeleteLocalRef(clazz); return; }
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jstring jlabel = env->NewStringUTF(label);
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env->CallStaticVoidMethod(clazz, mid, jlabel, (jint)passed, (jint)total);
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env->DeleteLocalRef(jlabel);
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env->DeleteLocalRef(clazz);
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}
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extern "C"
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JNIEXPORT jboolean JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runVMThread(JNIEnv *env, jclass clazz,
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@@ -4025,19 +4005,6 @@ Java_kr_co_iefriends_pcsx2_NativeApp_gameIniCommitWrite(JNIEnv*, jclass) {
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return ok ? JNI_TRUE : JNI_FALSE;
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}
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extern "C" JNIEXPORT void JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runCodegenTests(JNIEnv*, jclass) { RunArmCodegenTests(); }
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extern "C" JNIEXPORT void JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runPatchTests(JNIEnv*, jclass) { RunPatchTests(); }
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extern "C" JNIEXPORT void JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runVuJitTests(JNIEnv*, jclass) { RunVuJitTests(); }
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extern "C" JNIEXPORT void JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runEeJitTests(JNIEnv*, jclass) { RunEeJitTests(); }
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extern "C" JNIEXPORT void JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runVifTests(JNIEnv*, jclass) { RunVifTests(); }
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extern "C" JNIEXPORT void JNICALL
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Java_kr_co_iefriends_pcsx2_NativeApp_runEeSeqTests(JNIEnv*, jclass) { RunEeSeqTests(); }
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// ---------------------------------------------------------------------------
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// PS2 disc serial probe via ISO9660 directory walk.
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//
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@@ -1,35 +0,0 @@
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// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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//
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// Monorepo Android build: the recompiler/VIF/patch unit-test harnesses under
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// tests/ are compiled OUT of the emucore target because they depend on the
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// arm64/mac recompiler backend's test hooks (EE_Test*/mVU0_Test*) that are not
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// part of this core, plus a gtest scaffold. native-lib.cpp still exposes the
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// dev-only "run tests" JNI entry points, so we provide no-op definitions here
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// to keep the library linkable. Restore the real tests once a compatible test
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// backend is reconciled into this core.
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#include "tests/arm64/run_tests.h"
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#include "tests/core/run_patch_tests.h"
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#include "tests/mvu/run_mvu_tests.h"
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#include "tests/ee/run_ee_tests.h"
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#include "tests/ee/run_ee_seq_tests.h"
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#include "tests/vif/run_vif_tests.h"
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#include <android/log.h>
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namespace
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{
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void LogTestsDisabled(const char* which)
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{
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__android_log_print(ANDROID_LOG_INFO, "ARMSX2",
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"%s: recompiler self-tests are disabled in this build", which);
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}
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} // namespace
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void RunArmCodegenTests() { LogTestsDisabled("RunArmCodegenTests"); }
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void RunPatchTests() { LogTestsDisabled("RunPatchTests"); }
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void RunVuJitTests() { LogTestsDisabled("RunVuJitTests"); }
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void RunEeJitTests() { LogTestsDisabled("RunEeJitTests"); }
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void RunEeSeqTests() { LogTestsDisabled("RunEeSeqTests"); }
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void RunVifTests() { LogTestsDisabled("RunVifTests"); }
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@@ -1,49 +0,0 @@
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// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#include "codegen_tests.h"
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#include <gtest/gtest.h>
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#include <cstdio>
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#include <cstring>
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using namespace vixl::aarch64;
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thread_local const char* currentArmTest;
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// Plain heap-allocated buffer — no executable permissions needed.
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// We write ARM64 instructions into it and inspect the bytes; we never execute them.
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void runArmCodegenTest(
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void (*exec)(MacroAssembler& armAsm),
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const char* description,
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const char* expected)
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{
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if (!expected)
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return;
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currentArmTest = description;
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// 4096 bytes is enough for any single-instruction or short multi-instruction test.
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// Static to avoid blowing the stack; protected by gtest's serial test execution.
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static vixl::byte code[4096];
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memset(code, 0xd4, sizeof(code)); // 0xd4200000 prefix == BRK; helps spot runaway code
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MacroAssembler masm(code, sizeof(code));
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exec(masm);
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masm.FinalizeCode();
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const size_t size = masm.GetSizeOfCodeGenerated();
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// Format emitted bytes as lowercase hex separated by spaces ("e0 03 01 aa")
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char str[4096 * 3] = {};
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char* p = str;
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const auto* bytes = reinterpret_cast<const uint8_t*>(code);
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for (size_t i = 0; i < size; i++)
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{
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sprintf(p, "%02x ", bytes[i]);
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p += 3;
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}
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if (p != str)
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*--p = '\0'; // strip trailing space
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EXPECT_STRCASEEQ(expected, str) << "Unexpected codegen from " << description;
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}
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@@ -1,23 +0,0 @@
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// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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#pragma once
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#include "common/Pcsx2Defs.h"
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#include "vixl/aarch64/macro-assembler-aarch64.h"
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void runArmCodegenTest(
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void (*exec)(vixl::aarch64::MacroAssembler& armAsm),
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const char* description,
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const char* expected);
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// Lambda receives a MacroAssembler& named armAsm — matches production call sites
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// (production uses armAsm->Xxx, test uses armAsm.Xxx — identical operands).
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#define ARM_CODEGEN_TEST(command, expected) \
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runArmCodegenTest( \
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[](vixl::aarch64::MacroAssembler& armAsm) { \
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using namespace vixl::aarch64; \
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command; \
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}, \
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#command, \
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expected)
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@@ -1,215 +0,0 @@
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// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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// ARM64 (vixl MacroAssembler) codegen tests.
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//
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// Each test verifies the exact byte sequence emitted for a given
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// armAsm.Xxx() call. Expected bytes are little-endian A64 encodings.
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//
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// Call-site convention: production code writes "armAsm->Xxx(...)".
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// tests write "armAsm.Xxx(...)" — same operands.
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#include "codegen_tests.h"
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#include <gtest/gtest.h>
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using namespace vixl::aarch64;
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// ---------------------------------------------------------------------------
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// Integer register moves
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, MOVTest)
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{
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// MOV Xd, Xn => ORR Xd, XZR, Xn (sf=1, opc=01, 01010, shift=0, N=0)
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ARM_CODEGEN_TEST(armAsm.Mov(x0, x1), "e0 03 01 aa");
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ARM_CODEGEN_TEST(armAsm.Mov(x1, x0), "e1 03 00 aa");
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ARM_CODEGEN_TEST(armAsm.Mov(x2, x3), "e2 03 03 aa");
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ARM_CODEGEN_TEST(armAsm.Mov(x19, x20), "f3 03 14 aa");
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// MOV Wd, Wn => ORR Wd, WZR, Wn (sf=0)
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ARM_CODEGEN_TEST(armAsm.Mov(w0, w1), "e0 03 01 2a");
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ARM_CODEGEN_TEST(armAsm.Mov(w2, w3), "e2 03 03 2a");
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}
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// ---------------------------------------------------------------------------
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// Integer arithmetic — register form
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, ArithRegTest)
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{
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// ADD x0, x1, x2 (shifted register, shift=LSL, amount=0)
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ARM_CODEGEN_TEST(armAsm.Add(x0, x1, x2), "20 00 02 8b");
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// ADD w0, w1, w2
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ARM_CODEGEN_TEST(armAsm.Add(w0, w1, w2), "20 00 02 0b");
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// SUB x0, x1, x2
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ARM_CODEGEN_TEST(armAsm.Sub(x0, x1, x2), "20 00 02 cb");
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// SUB w0, w1, w2
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ARM_CODEGEN_TEST(armAsm.Sub(w0, w1, w2), "20 00 02 4b");
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// AND x0, x1, x2
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ARM_CODEGEN_TEST(armAsm.And(x0, x1, x2), "20 00 02 8a");
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// ORR x0, x1, x2
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ARM_CODEGEN_TEST(armAsm.Orr(x0, x1, x2), "20 00 02 aa");
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// EOR x0, x1, x2
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ARM_CODEGEN_TEST(armAsm.Eor(x0, x1, x2), "20 00 02 ca");
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// SUBS (sets flags) — SUBS x0, x1, x2
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ARM_CODEGEN_TEST(armAsm.Subs(x0, x1, x2), "20 00 02 eb");
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// CMP x1, x2 => SUBS xzr, x1, x2
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ARM_CODEGEN_TEST(armAsm.Cmp(x1, x2), "3f 00 02 eb");
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}
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// ---------------------------------------------------------------------------
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// Integer arithmetic — immediate form
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, ArithImmTest)
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{
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// ADD x0, x1, #4 (imm12=4, shift=0)
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ARM_CODEGEN_TEST(armAsm.Add(x0, x1, 4), "20 10 00 91");
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// ADD x0, x1, #1
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ARM_CODEGEN_TEST(armAsm.Add(x0, x1, 1), "20 04 00 91");
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// SUB x0, x1, #4
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ARM_CODEGEN_TEST(armAsm.Sub(x0, x1, 4), "20 10 00 d1");
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// SUB x0, x1, #1
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ARM_CODEGEN_TEST(armAsm.Sub(x0, x1, 1), "20 04 00 d1");
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// ADD w0, w1, #4
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ARM_CODEGEN_TEST(armAsm.Add(w0, w1, 4), "20 10 00 11");
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}
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// ---------------------------------------------------------------------------
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// Move immediate
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, MovImmTest)
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{
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// MOVZ x0, #0 => 00 00 80 d2
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ARM_CODEGEN_TEST(armAsm.Mov(x0, uint64_t{0}), "00 00 80 d2");
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// MOVZ x0, #1 => 20 00 80 d2
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ARM_CODEGEN_TEST(armAsm.Mov(x0, uint64_t{1}), "20 00 80 d2");
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// MOVZ x0, #0x1234 => 80 46 82 d2
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ARM_CODEGEN_TEST(armAsm.Mov(x0, uint64_t{0x1234}), "80 46 82 d2");
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// MOVZ x0, #0xffff => e0 ff 9f d2
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ARM_CODEGEN_TEST(armAsm.Mov(x0, uint64_t{0xffff}), "e0 ff 9f d2");
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}
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// ---------------------------------------------------------------------------
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// Shift — immediate
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, ShiftImmTest)
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{
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// LSL x0, x1, #4 => UBFM x0, x1, #60, #59
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ARM_CODEGEN_TEST(armAsm.Lsl(x0, x1, 4), "20 ec 7c d3");
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// LSR x0, x1, #4 => UBFM x0, x1, #4, #63
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ARM_CODEGEN_TEST(armAsm.Lsr(x0, x1, 4), "20 fc 44 d3");
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// ASR x0, x1, #4 => SBFM x0, x1, #4, #63
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ARM_CODEGEN_TEST(armAsm.Asr(x0, x1, 4), "20 fc 44 93");
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// LSL w0, w1, #4 => UBFM w0, w1, #28, #27 (32-bit form)
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ARM_CODEGEN_TEST(armAsm.Lsl(w0, w1, 4), "20 6c 1c 53");
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}
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// ---------------------------------------------------------------------------
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// Load / Store (unsigned offset)
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, LoadStoreTest)
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{
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// LDR x0, [x1] — 64-bit, offset=0
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ARM_CODEGEN_TEST(armAsm.Ldr(x0, MemOperand(x1)), "20 00 40 f9");
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// STR x0, [x1]
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ARM_CODEGEN_TEST(armAsm.Str(x0, MemOperand(x1)), "20 00 00 f9");
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// LDR w0, [x1] — 32-bit
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ARM_CODEGEN_TEST(armAsm.Ldr(w0, MemOperand(x1)), "20 00 40 b9");
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// STR w0, [x1]
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ARM_CODEGEN_TEST(armAsm.Str(w0, MemOperand(x1)), "20 00 00 b9");
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// LDR x0, [x1, #8] — imm12 = 8/8 = 1
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ARM_CODEGEN_TEST(armAsm.Ldr(x0, MemOperand(x1, 8)), "20 04 40 f9");
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// LDR w0, [x1, #4] — imm12 = 4/4 = 1
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ARM_CODEGEN_TEST(armAsm.Ldr(w0, MemOperand(x1, 4)), "20 04 40 b9");
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// LDR x0, [x1, x2] — register offset
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ARM_CODEGEN_TEST(armAsm.Ldr(x0, MemOperand(x1, x2)), "20 68 62 f8");
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}
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// ---------------------------------------------------------------------------
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// Load / Store pair
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, LoadStorePairTest)
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{
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// STP x0, x1, [x2, #-16]! (pre-index, typical prologue)
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ARM_CODEGEN_TEST(armAsm.Stp(x0, x1, MemOperand(x2, -16, PreIndex)), "40 04 bf a9");
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// LDP x0, x1, [x2], #16 (post-index, typical epilogue)
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ARM_CODEGEN_TEST(armAsm.Ldp(x0, x1, MemOperand(x2, 16, PostIndex)), "40 04 c1 a8");
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}
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// ---------------------------------------------------------------------------
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// Misc / control flow
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, MiscTest)
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{
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// RET (branch to x30)
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ARM_CODEGEN_TEST(armAsm.Ret(), "c0 03 5f d6");
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// NOP
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ARM_CODEGEN_TEST(armAsm.Nop(), "1f 20 03 d5");
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// BLR x0
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ARM_CODEGEN_TEST(armAsm.Blr(x0), "00 00 3f d6");
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// BR x0
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ARM_CODEGEN_TEST(armAsm.Br(x0), "00 00 1f d6");
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}
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// ---------------------------------------------------------------------------
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// NEON — vector operations
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// ---------------------------------------------------------------------------
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TEST(ArmCodegenTests, VectorTest)
|
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{
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// MOV v0.16B, v1.16B => ORR v0.16B, v1.16B, v1.16B (Q=1, size=10, opcode=00011)
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ARM_CODEGEN_TEST(armAsm.Mov(v0.V16B(), v1.V16B()), "20 1c a1 4e");
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// ADD v0.4S, v1.4S, v2.4S (integer add, Q=1, size=10, opcode=10000)
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ARM_CODEGEN_TEST(armAsm.Add(v0.V4S(), v1.V4S(), v2.V4S()), "20 84 a2 4e");
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// AND v0.16B, v1.16B, v2.16B (Q=1, size=00, opcode=00011, U=0)
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ARM_CODEGEN_TEST(armAsm.And(v0.V16B(), v1.V16B(), v2.V16B()), "20 1c 22 4e");
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// EOR v0.16B, v1.16B, v2.16B (Q=1, size=00, opcode=00011, U=1)
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ARM_CODEGEN_TEST(armAsm.Eor(v0.V16B(), v1.V16B(), v2.V16B()), "20 1c 22 6e");
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// ORR v0.16B, v1.16B, v2.16B (Q=1, size=10, opcode=00011, U=0)
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ARM_CODEGEN_TEST(armAsm.Orr(v0.V16B(), v1.V16B(), v2.V16B()), "20 1c a2 4e");
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// FADD v0.4S, v1.4S, v2.4S (Q=1, sz=0, opcode=11010)
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ARM_CODEGEN_TEST(armAsm.Fadd(v0.V4S(), v1.V4S(), v2.V4S()), "20 d4 22 4e");
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|
||||
// FMUL v0.4S, v1.4S, v2.4S (Q=1, sz=0, opcode=11011)
|
||||
ARM_CODEGEN_TEST(armAsm.Fmul(v0.V4S(), v1.V4S(), v2.V4S()), "20 dc 22 6e");
|
||||
|
||||
// FSUB v0.4S, v1.4S, v2.4S (Q=1, sz=0, opcode=11010, U=1)
|
||||
ARM_CODEGEN_TEST(armAsm.Fsub(v0.V4S(), v1.V4S(), v2.V4S()), "20 d4 a2 4e");
|
||||
|
||||
// FDIV v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Fdiv(v0.V4S(), v1.V4S(), v2.V4S()), "20 fc 22 6e");
|
||||
|
||||
// DUP v0.4S, w1 (scalar GPR to all lanes)
|
||||
ARM_CODEGEN_TEST(armAsm.Dup(v0.V4S(), w1), "20 0c 04 4e");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// NEON — shuffle / permute
|
||||
// ---------------------------------------------------------------------------
|
||||
TEST(ArmCodegenTests, VectorShuffleTest)
|
||||
{
|
||||
// ZIP1 v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Zip1(v0.V4S(), v1.V4S(), v2.V4S()), "20 38 82 4e");
|
||||
// ZIP2 v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Zip2(v0.V4S(), v1.V4S(), v2.V4S()), "20 78 82 4e");
|
||||
// UZP1 v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Uzp1(v0.V4S(), v1.V4S(), v2.V4S()), "20 18 82 4e");
|
||||
// UZP2 v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Uzp2(v0.V4S(), v1.V4S(), v2.V4S()), "20 58 82 4e");
|
||||
// TRN1 v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Trn1(v0.V4S(), v1.V4S(), v2.V4S()), "20 28 82 4e");
|
||||
// TRN2 v0.4S, v1.4S, v2.4S
|
||||
ARM_CODEGEN_TEST(armAsm.Trn2(v0.V4S(), v1.V4S(), v2.V4S()), "20 68 82 4e");
|
||||
}
|
||||
|
||||
// ---------------------------------------------------------------------------
|
||||
// NEON — conversion
|
||||
// ---------------------------------------------------------------------------
|
||||
TEST(ArmCodegenTests, VectorCvtTest)
|
||||
{
|
||||
// SCVTF v0.4S, v1.4S (signed int to float, 4 lanes)
|
||||
ARM_CODEGEN_TEST(armAsm.Scvtf(v0.V4S(), v1.V4S()), "20 d8 21 4e");
|
||||
// FCVTZS v0.4S, v1.4S (float to signed int, round-toward-zero)
|
||||
ARM_CODEGEN_TEST(armAsm.Fcvtzs(v0.V4S(), v1.V4S()), "20 b8 a1 4e");
|
||||
}
|
||||
@@ -1,153 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
|
||||
#include "run_tests.h"
|
||||
#include "../test_bridge.h"
|
||||
|
||||
#include "vixl/aarch64/macro-assembler-aarch64.h"
|
||||
|
||||
#include <android/log.h>
|
||||
#include <cstdint>
|
||||
#include <cstdio>
|
||||
#include <cstring>
|
||||
|
||||
using namespace vixl::aarch64;
|
||||
|
||||
#define TAG "ARM64CodegenTest"
|
||||
#define LOGI(...) __android_log_print(ANDROID_LOG_INFO, TAG, __VA_ARGS__)
|
||||
#define LOGE(...) __android_log_print(ANDROID_LOG_ERROR, TAG, __VA_ARGS__)
|
||||
|
||||
static int s_pass;
|
||||
static int s_fail;
|
||||
|
||||
static void runTest(void (*exec)(MacroAssembler&), const char* desc, const char* expected)
|
||||
{
|
||||
static vixl::byte code[4096];
|
||||
memset(code, 0, sizeof(code));
|
||||
|
||||
MacroAssembler masm(code, sizeof(code));
|
||||
exec(masm);
|
||||
masm.FinalizeCode();
|
||||
|
||||
const size_t size = masm.GetSizeOfCodeGenerated();
|
||||
|
||||
char str[4096 * 3] = {};
|
||||
char* p = str;
|
||||
for (size_t i = 0; i < size; i++)
|
||||
{
|
||||
sprintf(p, "%02x ", reinterpret_cast<const uint8_t*>(code)[i]);
|
||||
p += 3;
|
||||
}
|
||||
if (p != str)
|
||||
*--p = '\0';
|
||||
|
||||
if (strcasecmp(expected, str) == 0)
|
||||
{
|
||||
s_pass++;
|
||||
LOGI("PASS %s", desc);
|
||||
}
|
||||
else
|
||||
{
|
||||
s_fail++;
|
||||
LOGE("FAIL %s", desc);
|
||||
LOGE(" expected: %s", expected);
|
||||
LOGE(" got: %s", str);
|
||||
}
|
||||
}
|
||||
|
||||
#define T(cmd, expected) \
|
||||
runTest([](MacroAssembler& armAsm) { using namespace vixl::aarch64; cmd; }, #cmd, expected)
|
||||
|
||||
void RunArmCodegenTests()
|
||||
{
|
||||
s_pass = 0;
|
||||
s_fail = 0;
|
||||
LOGI("=== ARM64 Codegen Tests ===");
|
||||
|
||||
// --- Integer register moves ---
|
||||
T(armAsm.Mov(x0, x1), "e0 03 01 aa");
|
||||
T(armAsm.Mov(x1, x0), "e1 03 00 aa");
|
||||
T(armAsm.Mov(w0, w1), "e0 03 01 2a");
|
||||
T(armAsm.Mov(w2, w3), "e2 03 03 2a");
|
||||
|
||||
// --- Integer arithmetic (register) ---
|
||||
T(armAsm.Add(x0, x1, x2), "20 00 02 8b");
|
||||
T(armAsm.Add(w0, w1, w2), "20 00 02 0b");
|
||||
T(armAsm.Sub(x0, x1, x2), "20 00 02 cb");
|
||||
T(armAsm.Sub(w0, w1, w2), "20 00 02 4b");
|
||||
T(armAsm.And(x0, x1, x2), "20 00 02 8a");
|
||||
T(armAsm.Orr(x0, x1, x2), "20 00 02 aa");
|
||||
T(armAsm.Eor(x0, x1, x2), "20 00 02 ca");
|
||||
T(armAsm.Subs(x0, x1, x2), "20 00 02 eb");
|
||||
T(armAsm.Cmp(x1, x2), "3f 00 02 eb");
|
||||
|
||||
// --- Integer arithmetic (immediate) ---
|
||||
T(armAsm.Add(x0, x1, 1), "20 04 00 91");
|
||||
T(armAsm.Add(x0, x1, 4), "20 10 00 91");
|
||||
T(armAsm.Sub(x0, x1, 1), "20 04 00 d1");
|
||||
T(armAsm.Sub(x0, x1, 4), "20 10 00 d1");
|
||||
T(armAsm.Add(w0, w1, 4), "20 10 00 11");
|
||||
|
||||
// --- Move immediate ---
|
||||
T(armAsm.Mov(x0, uint64_t{0}), "00 00 80 d2");
|
||||
T(armAsm.Mov(x0, uint64_t{1}), "20 00 80 d2");
|
||||
T(armAsm.Mov(x0, uint64_t{0x1234}), "80 46 82 d2");
|
||||
T(armAsm.Mov(x0, uint64_t{0xffff}), "e0 ff 9f d2");
|
||||
|
||||
// --- Shifts (immediate) ---
|
||||
T(armAsm.Lsl(x0, x1, 4), "20 ec 7c d3");
|
||||
T(armAsm.Lsr(x0, x1, 4), "20 fc 44 d3");
|
||||
T(armAsm.Asr(x0, x1, 4), "20 fc 44 93");
|
||||
T(armAsm.Lsl(w0, w1, 4), "20 6c 1c 53");
|
||||
|
||||
// --- Load / Store ---
|
||||
T(armAsm.Ldr(x0, MemOperand(x1)), "20 00 40 f9");
|
||||
T(armAsm.Str(x0, MemOperand(x1)), "20 00 00 f9");
|
||||
T(armAsm.Ldr(w0, MemOperand(x1)), "20 00 40 b9");
|
||||
T(armAsm.Str(w0, MemOperand(x1)), "20 00 00 b9");
|
||||
T(armAsm.Ldr(x0, MemOperand(x1, 8)), "20 04 40 f9");
|
||||
T(armAsm.Ldr(w0, MemOperand(x1, 4)), "20 04 40 b9");
|
||||
T(armAsm.Ldr(x0, MemOperand(x1, x2)), "20 68 62 f8");
|
||||
|
||||
// --- Load / Store pair ---
|
||||
T(armAsm.Stp(x0, x1, MemOperand(x2, -16, PreIndex)), "40 04 bf a9");
|
||||
T(armAsm.Ldp(x0, x1, MemOperand(x2, 16, PostIndex)), "40 04 c1 a8");
|
||||
|
||||
// --- Misc ---
|
||||
T(armAsm.Ret(), "c0 03 5f d6");
|
||||
T(armAsm.Nop(), "1f 20 03 d5");
|
||||
T(armAsm.Blr(x0), "00 00 3f d6");
|
||||
T(armAsm.Br(x0), "00 00 1f d6");
|
||||
|
||||
// --- NEON vector ---
|
||||
T(armAsm.Mov(v0.V16B(), v1.V16B()), "20 1c a1 4e");
|
||||
T(armAsm.Add(v0.V4S(), v1.V4S(), v2.V4S()), "20 84 a2 4e");
|
||||
T(armAsm.And(v0.V16B(), v1.V16B(), v2.V16B()), "20 1c 22 4e");
|
||||
T(armAsm.Eor(v0.V16B(), v1.V16B(), v2.V16B()), "20 1c 22 6e");
|
||||
T(armAsm.Orr(v0.V16B(), v1.V16B(), v2.V16B()), "20 1c a2 4e");
|
||||
T(armAsm.Fadd(v0.V4S(), v1.V4S(), v2.V4S()), "20 d4 22 4e");
|
||||
T(armAsm.Fmul(v0.V4S(), v1.V4S(), v2.V4S()), "20 dc 22 6e");
|
||||
T(armAsm.Fsub(v0.V4S(), v1.V4S(), v2.V4S()), "20 d4 a2 4e");
|
||||
T(armAsm.Fdiv(v0.V4S(), v1.V4S(), v2.V4S()), "20 fc 22 6e");
|
||||
T(armAsm.Dup(v0.V4S(), w1), "20 0c 04 4e");
|
||||
|
||||
// --- NEON shuffle ---
|
||||
T(armAsm.Zip1(v0.V4S(), v1.V4S(), v2.V4S()), "20 38 82 4e");
|
||||
T(armAsm.Zip2(v0.V4S(), v1.V4S(), v2.V4S()), "20 78 82 4e");
|
||||
T(armAsm.Uzp1(v0.V4S(), v1.V4S(), v2.V4S()), "20 18 82 4e");
|
||||
T(armAsm.Uzp2(v0.V4S(), v1.V4S(), v2.V4S()), "20 58 82 4e");
|
||||
T(armAsm.Trn1(v0.V4S(), v1.V4S(), v2.V4S()), "20 28 82 4e");
|
||||
T(armAsm.Trn2(v0.V4S(), v1.V4S(), v2.V4S()), "20 68 82 4e");
|
||||
|
||||
// --- NEON conversion ---
|
||||
T(armAsm.Scvtf(v0.V4S(), v1.V4S()), "20 d8 21 4e");
|
||||
T(armAsm.Fcvtzs(v0.V4S(), v1.V4S()), "20 b8 a1 4e");
|
||||
|
||||
LOGI("=== Results: %d passed, %d failed ===", s_pass, s_fail);
|
||||
ReportTestResults("CodegenTests", s_pass, s_pass + s_fail);
|
||||
}
|
||||
|
||||
#undef T
|
||||
#undef LOGI
|
||||
#undef LOGE
|
||||
#undef TAG
|
||||
@@ -1,8 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
|
||||
#pragma once
|
||||
|
||||
// Runs all ARM64 codegen tests and prints PASS/FAIL to Android logcat.
|
||||
// Tag: ARM64CodegenTest
|
||||
void RunArmCodegenTests();
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
|
||||
#pragma once
|
||||
|
||||
/// Run Patch::ApplyPatches tests and print PASS/FAIL to logcat (tag: PatchTests).
|
||||
void RunPatchTests();
|
||||
@@ -1,28 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
#pragma once
|
||||
|
||||
#include "common/Pcsx2Defs.h"
|
||||
|
||||
// Test helper API for the R5900 (EE) interpreter.
|
||||
// Implementations live in Interpreter.cpp so they can access internal state
|
||||
// without exposing static symbols.
|
||||
|
||||
/// Virtual address in EE main RAM where test programs are loaded.
|
||||
static constexpr u32 EE_TEST_PC = 0x00100000u;
|
||||
/// Virtual address used as a scratch data region by load/store tests.
|
||||
static constexpr u32 EE_TEST_DATA = 0x00200000u;
|
||||
|
||||
/// Initialise EE for testing. Allocates SysMemory and sets up VTLB if not
|
||||
/// already done. Safe to call once before a batch of tests.
|
||||
void EE_TestInit();
|
||||
|
||||
/// Called after all tests complete; clears test-mode flag.
|
||||
void EE_TestShutdown();
|
||||
|
||||
/// Write `count` u32 words into EE main RAM at EE_TEST_PC.
|
||||
void EE_TestWriteProg(const u32* words, u32 count);
|
||||
|
||||
/// Execute up to maxInstrs instructions starting at EE_TEST_PC.
|
||||
/// Stops early when a halt instruction (BEQ $0,$0,-1 = 0x1000FFFF) is reached.
|
||||
void EE_TestExec(u32 maxInstrs = 100000u);
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
#pragma once
|
||||
|
||||
/// Run EE interpreter multi-instruction sequence tests and print PASS/FAIL to
|
||||
/// logcat (tag: EeSeqTests).
|
||||
void RunEeSeqTests();
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
#pragma once
|
||||
|
||||
/// Run R5900 EE interpreter instruction tests and print PASS/FAIL to logcat
|
||||
/// (tag: EeJitTests).
|
||||
void RunEeJitTests();
|
||||
@@ -1,39 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
#pragma once
|
||||
|
||||
#include "common/Pcsx2Defs.h"
|
||||
|
||||
// Test helper API for microVU0 / microVU1 JIT tests.
|
||||
// Implementations live in microVU.cpp so they can access internal types
|
||||
// without causing duplicate-symbol errors from the .inl includes.
|
||||
|
||||
/// (Re-)initialise microVU0 and allocate the JIT cache. Safe to call
|
||||
/// repeatedly; performs a close before each init.
|
||||
void mVU0_TestInit();
|
||||
|
||||
/// Release the microVU0 JIT cache.
|
||||
void mVU0_TestShutdown();
|
||||
|
||||
/// Copy `count` u32 words into VU0.Micro and invalidate the JIT program
|
||||
/// cache so the next Execute call recompiles the new program.
|
||||
void mVU0_TestWriteProg(const u32* words, u32 count);
|
||||
|
||||
/// Execute the microVU0 JIT from byte offset `startPC` (pass 0 for the
|
||||
/// start of the program) for up to `cycles` cycles.
|
||||
void mVU0_TestExec(u32 startPC, u32 cycles);
|
||||
|
||||
/// (Re-)initialise microVU1 and allocate the JIT cache. Safe to call
|
||||
/// repeatedly; performs a close before each init.
|
||||
void mVU1_TestInit();
|
||||
|
||||
/// Release the microVU1 JIT cache.
|
||||
void mVU1_TestShutdown();
|
||||
|
||||
/// Copy `count` u32 words into VU1.Micro and invalidate the JIT program
|
||||
/// cache so the next Execute call recompiles the new program.
|
||||
void mVU1_TestWriteProg(const u32* words, u32 count);
|
||||
|
||||
/// Execute the microVU1 JIT from byte offset `startPC` (pass 0 for the
|
||||
/// start of the program) for up to `cycles` cycles.
|
||||
void mVU1_TestExec(u32 startPC, u32 cycles);
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
|
||||
#pragma once
|
||||
|
||||
/// Run microVU JIT integer-instruction tests and print PASS/FAIL to logcat (tag: VuJitTests).
|
||||
void RunVuJitTests();
|
||||
@@ -1,8 +0,0 @@
|
||||
// SPDX-FileCopyrightText: 2002-2026 PCSX2 Dev Team
|
||||
// SPDX-License-Identifier: GPL-3.0+
|
||||
#pragma once
|
||||
|
||||
/// Report test-suite results back to NativeApp.onTestResults(label, pass, total) via JNI.
|
||||
/// Defined in native-lib.cpp. Safe to call from any thread that has a JNI env available
|
||||
/// through SDL_GetAndroidJNIEnv().
|
||||
void ReportTestResults(const char* label, int pass, int total);
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user