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Core: Use ARCH_ARM64 instead of _M_ARM64

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fast_float assumes that _M_ARM64 means compiling for Windows
This commit is contained in:
TellowKrinkle
2026-03-20 11:13:53 -04:00
committed by Ty
parent 5e5ea642b0
commit 81a20150f2
36 changed files with 112 additions and 106 deletions
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CMakeLists.txt
+1 -1
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@@ -81,7 +81,7 @@ No support will be provided, continue at your own risk.
*********************************************************")
endif()
if(_M_ARM64)
if(ARCH_ARM64)
message(WARNING "
*************** UNSUPPORTED CONFIGURATION ***************
Apple Silicon support in PCSX2 is INCOMPLETE. There are
cmake/BuildParameters.cmake
+9 -4
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@@ -84,7 +84,7 @@ if("${CMAKE_HOST_SYSTEM_PROCESSOR}" STREQUAL "x86_64" OR "${CMAKE_HOST_SYSTEM_PR
option(DISABLE_ADVANCE_SIMD "Disable advance use of SIMD (SSE2+ & AVX)" OFF)
list(APPEND PCSX2_DEFS _M_X86=1)
set(_M_X86 TRUE)
set(ARCH_X86 TRUE)
if(DISABLE_ADVANCE_SIMD)
message(STATUS "Building for x86-64 (Multi-ISA).")
else()
@@ -113,9 +113,14 @@ if("${CMAKE_HOST_SYSTEM_PROCESSOR}" STREQUAL "x86_64" OR "${CMAKE_HOST_SYSTEM_PR
elseif("${CMAKE_HOST_SYSTEM_PROCESSOR}" STREQUAL "arm64" OR "${CMAKE_HOST_SYSTEM_PROCESSOR}" STREQUAL "aarch64" OR
"${CMAKE_OSX_ARCHITECTURES}" STREQUAL "arm64")
message(STATUS "Building for Apple Silicon (ARM64).")
list(APPEND PCSX2_DEFS _M_ARM64=1)
set(_M_ARM64 TRUE)
add_compile_options("-march=armv8.4-a" "-mcpu=apple-m1")
set(ARCH_ARM64 TRUE)
if(APPLE)
# Min spec is an M1
add_compile_options("-march=armv8.4-a" "-mcpu=apple-m1")
else()
# Require atomic rmw instructions
add_compile_options("-march=armv8.1-a")
endif()
# If we're running on Linux, we need to detect the page/cache line size.
# It could be a virtual machine with 4K pages, or 16K with Asahi.
cmake/SearchForStuff.cmake
+2 -2
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@@ -132,9 +132,9 @@ add_subdirectory(3rdparty/demangler EXCLUDE_FROM_ALL)
add_subdirectory(3rdparty/ccc EXCLUDE_FROM_ALL)
# Architecture-specific.
if(_M_X86)
if(ARCH_X86)
add_subdirectory(3rdparty/zydis EXCLUDE_FROM_ALL)
elseif(_M_ARM64)
elseif(ARCH_ARM64)
add_subdirectory(3rdparty/vixl EXCLUDE_FROM_ALL)
endif()
common/CMakeLists.txt
+1 -1
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@@ -85,7 +85,7 @@ target_sources(common PRIVATE
YAML.h
)
if(_M_X86)
if(ARCH_X86)
target_sources(common PRIVATE
emitter/bmi.cpp
emitter/fpu.cpp
common/Darwin/DarwinMisc.cpp
+10 -10
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@@ -338,7 +338,7 @@ void* HostSys::Mmap(void* base, size_t size, const PageProtectionMode& mode)
if (mode.IsNone())
return nullptr;
#ifdef __aarch64__
#ifdef ARCH_ARM64
// We can't allocate executable memory with mach_vm_allocate() on Apple Silicon.
// Instead, we need to use MAP_JIT with mmap(), which does not support fixed mappings.
if (mode.CanExecute())
@@ -441,7 +441,7 @@ void HostSys::UnmapSharedMemory(void* baseaddr, size_t size)
pxFailRel("Failed to unmap shared memory");
}
#ifdef _M_ARM64
#ifdef ARCH_ARM64
void HostSys::FlushInstructionCache(void* address, u32 size)
{
@@ -518,7 +518,7 @@ bool SharedMemoryMappingArea::Unmap(void* map_base, size_t map_size)
return true;
}
#ifdef _M_ARM64
#ifdef ARCH_ARM64
static thread_local int s_code_write_depth = 0;
@@ -570,7 +570,7 @@ void HostSys::EndCodeWrite()
}
}
#endif // _M_ARM64
#endif // ARCH_ARM64
#define USE_MACH_EXCEPTION_PORTS
@@ -589,11 +589,11 @@ namespace PageFaultHandler
#ifdef USE_MACH_EXCEPTION_PORTS
#if defined(_M_X86)
#if defined(ARCH_X86)
#define THREAD_STATE64_COUNT x86_THREAD_STATE64_COUNT
#define THREAD_STATE64 x86_THREAD_STATE64
#define thread_state64_t x86_thread_state64_t
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
#define THREAD_STATE64_COUNT ARM_THREAD_STATE64_COUNT
#define THREAD_STATE64 ARM_THREAD_STATE64
#define thread_state64_t arm_thread_state64_t
@@ -669,7 +669,7 @@ void PageFaultHandler::SignalHandler(mach_port_t port)
{
s_in_exception_handler = true;
#ifdef _M_ARM64
#ifdef ARCH_ARM64
result = HandlePageFault(reinterpret_cast<void*>(state->__pc), reinterpret_cast<void*>(msg_in.code[1]), (msg_in.code[0] & 2) != 0);
#else
result = HandlePageFault(reinterpret_cast<void*>(state->__rip), reinterpret_cast<void*>(msg_in.code[1]), (msg_in.code[0] & 2) != 0);
@@ -774,12 +774,12 @@ bool PageFaultHandler::Install(Error* error)
void PageFaultHandler::SignalHandler(int sig, siginfo_t* info, void* ctx)
{
#if defined(_M_X86)
#if defined(ARCH_X86)
void* const exception_address =
reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext->__es.__faultvaddr);
void* const exception_pc = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext->__ss.__rip);
const bool is_write = (static_cast<ucontext_t*>(ctx)->uc_mcontext->__es.__err & 2) != 0;
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
void* const exception_address = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext->__es.__far);
void* const exception_pc = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext->__ss.__pc);
const bool is_write = IsStoreInstruction(exception_pc);
@@ -825,7 +825,7 @@ bool PageFaultHandler::Install(Error* error)
return false;
}
#ifdef _M_ARM64
#ifdef ARCH_ARM64
if (sigaction(SIGSEGV, &sa, nullptr) != 0)
{
Error::SetErrno(error, "sigaction() for SIGSEGV failed: ", errno);
common/Darwin/DarwinThreads.cpp
+2 -2
View File
@@ -34,9 +34,9 @@ __forceinline void Threading::SpinWait()
{
// If this doesn't compile you can just comment it out (it only serves as a
// performance hint and isn't required).
#if defined(_M_X86)
#if defined(ARCH_X86)
__asm__("pause");
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
__asm__ __volatile__("isb");
#endif
}
common/FPControl.h
+2 -2
View File
@@ -20,7 +20,7 @@ enum class FPRoundMode : u8
struct FPControlRegister
{
#ifdef _M_X86
#ifdef ARCH_X86
u32 bitmask;
static constexpr u32 EXCEPTION_MASK = (0x3Fu << 7);
@@ -101,7 +101,7 @@ struct FPControlRegister
__fi constexpr bool operator==(const FPControlRegister& rhs) const { return bitmask == rhs.bitmask; }
__fi constexpr bool operator!=(const FPControlRegister& rhs) const { return bitmask != rhs.bitmask; }
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
u64 bitmask;
static constexpr u64 FZ_BIT = (0x1ULL << 24);
common/FastJmp.cpp
+3 -3
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@@ -4,7 +4,7 @@
#include "FastJmp.h"
// Win32 uses Fastjmp.asm, because MSVC doesn't support inline asm.
#if !defined(_WIN32) || defined(_M_ARM64)
#if !defined(_WIN32) || defined(ARCH_ARM64)
#if defined(__APPLE__)
#define PREFIX "_"
@@ -12,7 +12,7 @@
#define PREFIX ""
#endif
#if defined(_M_X86)
#if defined(ARCH_X86)
asm(
"\t.global " PREFIX "fastjmp_set\n"
@@ -46,7 +46,7 @@ asm(
jmp *%rdx
)");
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
asm(
"\t.global " PREFIX "fastjmp_set\n"
common/FastJmp.h
+1 -1
View File
@@ -10,7 +10,7 @@ struct fastjmp_buf
{
#if defined(_WIN32)
static constexpr std::size_t BUF_SIZE = 240;
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
static constexpr std::size_t BUF_SIZE = 168;
#else
static constexpr std::size_t BUF_SIZE = 64;
common/HostSys.cpp
+3 -3
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@@ -13,7 +13,7 @@ static u32 PAUSE_TIME = 0;
static void MultiPause()
{
#ifdef _M_X86
#ifdef ARCH_X86
_mm_pause();
_mm_pause();
_mm_pause();
@@ -22,7 +22,7 @@ static void MultiPause()
_mm_pause();
_mm_pause();
_mm_pause();
#elif defined(_M_ARM64) && defined(_MSC_VER)
#elif defined(ARCH_ARM64) && defined(_MSC_VER)
__isb(_ARM64_BARRIER_SY);
__isb(_ARM64_BARRIER_SY);
__isb(_ARM64_BARRIER_SY);
@@ -31,7 +31,7 @@ static void MultiPause()
__isb(_ARM64_BARRIER_SY);
__isb(_ARM64_BARRIER_SY);
__isb(_ARM64_BARRIER_SY);
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
__asm__ __volatile__("isb");
__asm__ __volatile__("isb");
__asm__ __volatile__("isb");
common/HostSys.h
+2 -2
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@@ -107,7 +107,7 @@ namespace HostSys
extern void UnmapSharedMemory(void* baseaddr, size_t size);
/// JIT write protect for Apple Silicon. Needs to be called prior to writing to any RWX pages.
#if !defined(__APPLE__) || !defined(_M_ARM64)
#if !defined(__APPLE__) || !defined(ARCH_ARM64)
// clang-format -off
[[maybe_unused]] __fi static void BeginCodeWrite() {}
[[maybe_unused]] __fi static void EndCodeWrite() {}
@@ -119,7 +119,7 @@ namespace HostSys
/// Flushes the instruction cache on the host for the specified range.
/// Only needed on ARM64, X86 has coherent D/I cache.
#ifdef _M_X86
#ifdef ARCH_X86
[[maybe_unused]] __fi static void FlushInstructionCache(void* address, u32 size) {}
#else
void FlushInstructionCache(void* address, u32 size);
common/Linux/LnxHostSys.cpp
+7 -7
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@@ -243,7 +243,7 @@ namespace PageFaultHandler
static bool s_installed = false;
} // namespace PageFaultHandler
#ifdef _M_ARM64
#ifdef ARCH_ARM64
void HostSys::FlushInstructionCache(void* address, u32 size)
{
@@ -285,7 +285,7 @@ void HostSys::FlushInstructionCache(void* address, u32 size)
}
}
#endif // _M_ARM64
#endif // ARCH_ARM64
namespace PageFaultHandler
{
@@ -297,21 +297,21 @@ void PageFaultHandler::SignalHandler(int sig, siginfo_t* info, void* ctx)
#if defined(__linux__)
void* const exception_address = reinterpret_cast<void*>(info->si_addr);
#if defined(_M_X86)
#if defined(ARCH_X86)
void* const exception_pc = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext.gregs[REG_RIP]);
const bool is_write = (static_cast<ucontext_t*>(ctx)->uc_mcontext.gregs[REG_ERR] & 2) != 0;
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
void* const exception_pc = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext.pc);
const bool is_write = IsStoreInstruction(exception_pc);
#endif
#elif defined(__FreeBSD__)
#if defined(_M_X86)
#if defined(ARCH_X86)
void* const exception_address = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext.mc_addr);
void* const exception_pc = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext.mc_rip);
const bool is_write = (static_cast<ucontext_t*>(ctx)->uc_mcontext.mc_err & 2) != 0;
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
void* const exception_address = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext->__es.__far);
void* const exception_pc = reinterpret_cast<void*>(static_cast<ucontext_t*>(ctx)->uc_mcontext->__ss.__pc);
const bool is_write = IsStoreInstruction(exception_pc);
@@ -358,7 +358,7 @@ bool PageFaultHandler::Install(Error* error)
return false;
}
#ifdef _M_ARM64
#ifdef ARCH_ARM64
// We can get SIGBUS on ARM64.
if (sigaction(SIGBUS, &sa, nullptr) != 0)
{
common/Linux/LnxThreads.cpp
+2 -2
View File
@@ -41,9 +41,9 @@ __forceinline void Threading::SpinWait()
{
// If this doesn't compile you can just comment it out (it only serves as a
// performance hint and isn't required).
#if defined(_M_X86)
#if defined(ARCH_X86)
__asm__("pause");
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
__asm__ __volatile__("isb");
#endif
}
common/Pcsx2Defs.h
+10 -2
View File
@@ -23,12 +23,20 @@ static constexpr bool IsDebugBuild = true;
static constexpr bool IsDebugBuild = false;
#endif
#if defined(_M_ARM64) || defined(__aarch64__)
#define ARCH_ARM64
#elif defined(_M_X86) || defined(__x86_64__) || defined(__i386__)
#define ARCH_X86
#else
#error Unsupported Platform
#endif
// Defines the memory page size for the target platform at compilation.
#if defined(OVERRIDE_HOST_PAGE_SIZE)
static constexpr unsigned int __pagesize = OVERRIDE_HOST_PAGE_SIZE;
static constexpr unsigned int __pagemask = __pagesize - 1;
static constexpr unsigned int __pageshift = std::bit_width(__pagemask);
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
// Apple Silicon uses 16KB pages and 128 byte cache lines.
static constexpr unsigned int __pagesize = 0x4000;
static constexpr unsigned int __pageshift = 14;
@@ -41,7 +49,7 @@ static constexpr bool IsDebugBuild = false;
#endif
#if defined(OVERRIDE_HOST_CACHE_LINE_SIZE)
static constexpr unsigned int __cachelinesize = OVERRIDE_HOST_CACHE_LINE_SIZE;
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
static constexpr unsigned int __cachelinesize = 128;
#else
static constexpr unsigned int __cachelinesize = 64;
common/Perf.cpp
+2 -2
View File
@@ -138,9 +138,9 @@ namespace Perf
pxAssertRel(perf_marker != MAP_FAILED, "Map perf marker");
JITDUMP_HEADER jh = {};
#if defined(_M_X86)
#if defined(ARCH_X86)
jh.elf_mach = EM_X86_64;
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
jh.elf_mach = EM_AARCH64;
#else
#error Unhandled architecture.
common/SingleRegisterTypes.h
+2 -2
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@@ -15,7 +15,7 @@
#include <cstring>
#if defined(_M_X86)
#if defined(ARCH_X86)
// Can't stick them in structs because it breaks calling convention things, yay
using r128 = __m128i;
@@ -102,7 +102,7 @@ using r128 = __m128i;
_mm_store_ps((float*)&dest, _mm_setzero_ps());
}
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
using r128 = uint32x4_t;
common/StringUtil.h
-9
View File
@@ -14,16 +14,7 @@
#include <string_view>
#include <vector>
// Work around us defining _M_ARM64 but fast_float thinking that it means MSVC.
#if defined(_M_ARM64) && !defined(_WIN32)
#define HAD_M_ARM64 _M_ARM64
#undef _M_ARM64
#endif
#include "fast_float/fast_float.h"
#if defined(HAD_M_ARM64) && !defined(_WIN32)
#define _M_ARM64 HAD_M_ARM64
#undef HAD_M_ARM64
#endif
// Older versions of libstdc++ are missing support for from_chars() with floats, and was only recently
// merged in libc++. So, just fall back to stringstream (yuck!) on everywhere except MSVC.
common/VectorIntrin.h
+4 -2
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@@ -5,7 +5,9 @@
#pragma once
#if defined(_M_X86)
#include "common/Pcsx2Defs.h"
#if defined(ARCH_X86)
#ifdef _MSC_VER
#include <intrin.h>
@@ -35,7 +37,7 @@
#include <smmintrin.h>
#include <immintrin.h>
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
#include <arm_neon.h>
#endif
common/Windows/WinHostSys.cpp
+3 -3
View File
@@ -128,7 +128,7 @@ size_t HostSys::GetRuntimeCacheLineSize()
return max_line_size;
}
#ifdef _M_ARM64
#ifdef ARCH_ARM64
void HostSys::FlushInstructionCache(void* address, u32 size)
{
@@ -338,9 +338,9 @@ LONG PageFaultHandler::ExceptionHandler(PEXCEPTION_POINTERS exi)
if (exi->ExceptionRecord->ExceptionCode != EXCEPTION_ACCESS_VIOLATION)
return EXCEPTION_CONTINUE_SEARCH;
#if defined(_M_X86)
#if defined(ARCH_X86)
void* const exception_pc = reinterpret_cast<void*>(exi->ContextRecord->Rip);
#elif defined(_M_ARM64)
#elif defined(ARCH_ARM64)
void* const exception_pc = reinterpret_cast<void*>(exi->ContextRecord->Pc);
#else
void* const exception_pc = nullptr;
common/Windows/WinThreads.cpp
+4 -4
View File
@@ -20,7 +20,7 @@ __fi void Threading::Timeslice()
// improve performance and reduce cpu power consumption.
__fi void Threading::SpinWait()
{
#ifdef _M_X86
#ifdef ARCH_X86
_mm_pause();
#else
YieldProcessor();
@@ -107,7 +107,7 @@ Threading::ThreadHandle& Threading::ThreadHandle::operator=(const ThreadHandle&
u64 Threading::ThreadHandle::GetCPUTime() const
{
#ifndef _M_ARM64
#ifndef ARCH_ARM64
u64 ret = 0;
if (m_native_handle)
QueryThreadCycleTime((HANDLE)m_native_handle, &ret);
@@ -208,7 +208,7 @@ Threading::ThreadHandle& Threading::Thread::operator=(Thread&& thread)
u64 Threading::GetThreadCpuTime()
{
#ifndef _M_ARM64
#ifndef ARCH_ARM64
u64 ret = 0;
QueryThreadCycleTime(GetCurrentThread(), &ret);
return ret;
@@ -225,7 +225,7 @@ u64 Threading::GetThreadCpuTime()
u64 Threading::GetThreadTicksPerSecond()
{
#ifndef _M_ARM64
#ifndef ARCH_ARM64
// On x86, despite what the MS documentation says, this basically appears to be rdtsc.
// So, the frequency is our base clock speed (and stable regardless of power management).
static u64 frequency = 0;

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