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COP2: pre-clamp Fs on the MADDA broadcast row
NASCAR Thunder 2002 drew every car as a shredded wireframe under the EE recompiler; the EE interpreter drew them correctly, and VU0, VU1 and IOP were all identical to the JIT, so the fault was EE-side COP2 macro code. COP2_MADDA_BC multiplied Fs straight from its register. x86 specifies cFs for mVU_MADDAx/y/z/w, and the reason is that the PS2 VU has no infinities: an exponent-FF word is an ordinary large number, so against a zero broadcast lane the architectural answer is clamped(Fs) * 0 = 0. Taken unclamped it is the host's Inf * 0 = NaN, which the post-op result clamp then folds to +/-FLT_MAX. A transform accumulating that into ACC scatters the geometry it was positioning. The pre-clamp mirrors COP2_MADD_BC's existing clampFs. MSUBAx/y/z/w pass false: x86 gives them clampType 0, so their unclamped Fs is a shared, by-design divergence, not an arm64 defect. The game symptom needed the whole (lane x dest mask) grid to be right as well, so the test sweeps that for both halves of the family before pinning the clamp corner. recompiler_tests 1706/1706.
This commit is contained in:
Brian Degenhardt
+23
-10
@@ -2137,13 +2137,26 @@ COP2_MADDA_OP(MADDA, Fadd)
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COP2_MADDA_OP(MSUBA, Fsub)
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// MADDA/MSUBA broadcast variants: ACC = ACC ± VF[fs] * VF[ft].bc
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#define COP2_MADDA_BC(name, addOp, bc) \
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//
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// MADDAx/y/z/w pre-clamp Fs before the multiply (clampFs=true), matching
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// mVU_MADDAx/y/z/w's cFs (microVU_Upper.inl). The PS2 VU has no infinities, so
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// an exp-FF Fs is an ordinary large number: against a zero broadcast lane it
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// must give clamped(Fs)*0 = 0, not the host's Inf*0 = NaN that the post-op
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// result clamp then folds to ±FLT_MAX. MSUBAx/y/z/w pass false because x86
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// gives them clampType 0 — that Fs divergence is shared and by design.
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#define COP2_MADDA_BC(name, addOp, bc, clampFs) \
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void recCOP2_V##name() \
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{ \
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setupMacroOp_arm64(0x110); \
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const a64::VRegister fs = cop2GetVF(_Fs_cop2); \
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a64::VRegister mulA = fs; \
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if (clampFs) \
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{ \
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cop2ClampInto(RQSCRATCH, fs); \
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mulA = RQSCRATCH; \
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} \
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cop2LoadBroadcast(RQSCRATCH2, _Ft_cop2, bc); \
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armAsm->Fmul(RQSCRATCH.V4S(), fs.V4S(), RQSCRATCH2.V4S()); \
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armAsm->Fmul(RQSCRATCH.V4S(), mulA.V4S(), RQSCRATCH2.V4S()); \
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const a64::VRegister acc = cop2GetACC(); \
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const a64::VRegister rdA = (_XYZW_cop2 == 0xF) ? acc : RQSCRATCH; \
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armAsm->addOp(rdA.V4S(), acc.V4S(), RQSCRATCH.V4S()); \
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@@ -2153,15 +2166,15 @@ COP2_MADDA_OP(MSUBA, Fsub)
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endMacroOp_arm64(0x110); \
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}
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COP2_MADDA_BC(MADDAx, Fadd, 0)
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COP2_MADDA_BC(MADDAy, Fadd, 1)
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COP2_MADDA_BC(MADDAz, Fadd, 2)
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COP2_MADDA_BC(MADDAw, Fadd, 3)
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COP2_MADDA_BC(MADDAx, Fadd, 0, true)
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COP2_MADDA_BC(MADDAy, Fadd, 1, true)
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COP2_MADDA_BC(MADDAz, Fadd, 2, true)
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COP2_MADDA_BC(MADDAw, Fadd, 3, true)
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COP2_MADDA_BC(MSUBAx, Fsub, 0)
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COP2_MADDA_BC(MSUBAy, Fsub, 1)
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COP2_MADDA_BC(MSUBAz, Fsub, 2)
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COP2_MADDA_BC(MSUBAw, Fsub, 3)
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COP2_MADDA_BC(MSUBAx, Fsub, 0, false)
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COP2_MADDA_BC(MSUBAy, Fsub, 1, false)
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COP2_MADDA_BC(MSUBAz, Fsub, 2, false)
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COP2_MADDA_BC(MSUBAw, Fsub, 3, false)
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// MADDAq/MSUBAq
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#define COP2_MADDA_Q(name, addOp) \
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@@ -73,6 +73,7 @@ add_pcsx2_test(recompiler_tests
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vtlb_get_guest_address_tests.cpp
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vif_unpack_dynarec_tests.cpp
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ee_vu0_cop2_maxmini_conv_tests.cpp
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ee_vu0_cop2_madda_bc_tests.cpp
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vu0_harness_validation_tests.cpp
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vu0_alu_upper_tests.cpp
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vu0_alu_lower_tests.cpp
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@@ -0,0 +1,200 @@
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// SPDX-FileCopyrightText: 2026 yaps2 Dev Team
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// SPDX-License-Identifier: GPL-3.0+
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// COP2 macro-mode broadcast MADDA/MSUBA: ACC = ACC +/- VF[fs] * VF[ft].bc
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//
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// These are SPECIAL2 indices 0x08-0x0F, emitted by COP2_MADDA_BC in
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// iCOP2-arm64.cpp. They are the backbone of an EE-side 4x4 transform — the
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// MULAx/MADDAy/MADDAz/MADDAw chain that accumulates a matrix-vector product —
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// so a wrong answer here shows up as displaced geometry rather than anything
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// that trips an assert.
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//
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// The whole family shares one emitter macro parameterized only by the
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// broadcast lane, which makes it easy to assume the four lanes are
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// interchangeable. They are not: the dest-mask write-back and the ACC operand
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// fetch interact with the lane, and a sweep over (lane x dest mask) is the
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// only thing that pins every combination the macro can generate.
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//
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// The oracle is the VU0 interpreter via EeRecTestHarness's JIT-vs-interpreter
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// diff, which CLAUDE.md records as a zero-known-bug baseline.
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#include "harness/EeRecTestHarness.h"
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#include "VU.h"
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#include "VUmicro.h"
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#include "Config.h"
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#include <gtest/gtest.h>
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namespace recompiler_tests {
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using namespace mips;
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using namespace mips::ee;
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using namespace vu;
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namespace {
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// COP2 SPECIAL2 is reached with funct 0x3C-0x3F; the recCOP2SPECIAL2t index is
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// (code & 3) | ((code >> 4) & 0x7C), i.e. the low two bits of funct plus the
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// FD/SA field shifted up by two. So an index maps back to
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// funct = 0x3C | (idx & 3) and sa = idx >> 2.
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constexpr u32 COP2_SPEC2(u32 mask_xyzw, u32 idx, u32 fs, u32 ft)
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{
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return COP2_FMAC(mask_xyzw, /*fd/sa*/ idx >> 2, fs, ft, 0x3Cu | (idx & 3u));
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}
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// SPECIAL2 row 1: 0x08-0x0B = MADDAx/y/z/w, 0x0C-0x0F = MSUBAx/y/z/w.
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constexpr u32 VMADDAx_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x08, fs, ft); }
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constexpr u32 VMADDAy_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x09, fs, ft); }
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constexpr u32 VMADDAz_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x0A, fs, ft); }
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constexpr u32 VMADDAw_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x0B, fs, ft); }
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constexpr u32 VMSUBAx_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x0C, fs, ft); }
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constexpr u32 VMSUBAy_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x0D, fs, ft); }
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constexpr u32 VMSUBAz_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x0E, fs, ft); }
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constexpr u32 VMSUBAw_C2(u32 m, u32 fs, u32 ft) { return COP2_SPEC2(m, 0x0F, fs, ft); }
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struct BcOp
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{
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const char* name;
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u32 (*encode)(u32 m, u32 fs, u32 ft);
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char lane;
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};
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const BcOp kMaddaOps[] = {
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{"VMADDAx", VMADDAx_C2, 'x'}, {"VMADDAy", VMADDAy_C2, 'y'},
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{"VMADDAz", VMADDAz_C2, 'z'}, {"VMADDAw", VMADDAw_C2, 'w'},
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};
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const BcOp kMsubaOps[] = {
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{"VMSUBAx", VMSUBAx_C2, 'x'}, {"VMSUBAy", VMSUBAy_C2, 'y'},
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{"VMSUBAz", VMSUBAz_C2, 'z'}, {"VMSUBAw", VMSUBAw_C2, 'w'},
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};
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// Run one op at one dest mask and report the JIT-vs-interpreter ACC diff.
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void CheckOneCase(const BcOp& op, u32 mask,
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const float (&fs)[4], const float (&ft)[4], const float (&acc)[4])
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{
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EeRecTestHarness h;
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h.EnableVu0Capture();
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h.EnableCop1();
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h.SeedVu0Vf(1, fs[0], fs[1], fs[2], fs[3]);
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h.SeedVu0Vf(2, ft[0], ft[1], ft[2], ft[3]);
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h.SeedVu0Acc(acc[0], acc[1], acc[2], acc[3]);
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h.LoadProgram({op.encode(mask, /*fs*/1, /*ft*/2)});
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h.Run();
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for (char l : {'x', 'y', 'z', 'w'})
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{
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EXPECT_EQ(h.GetVu0AccBitsJit(l), h.GetVu0AccBitsInterp(l))
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<< op.name << " dest mask 0x" << std::hex << mask << std::dec
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<< " ACC." << l << ": JIT and interpreter disagree";
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}
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}
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const float kFs[4] = {1.5f, -2.25f, 3.75f, -4.5f};
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const float kFt[4] = {5.5f, 6.25f, -7.75f, 8.5f};
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const float kAcc[4] = {100.0f, -200.0f, 300.0f, -400.0f};
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} // namespace
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// Every broadcast lane against every dest mask. The x/y/z lanes and the full
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// 0xF mask are the well-trodden paths; the partial masks are where the
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// write-back picks a different shape (single-lane insert vs BSL merge vs
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// in-place full overwrite).
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TEST(EeVu0Cop2MaddaBc, EveryLaneEveryDestMaskMatchesInterp)
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{
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for (const BcOp* ops : {kMaddaOps, kMsubaOps})
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for (int i = 0; i < 4; i++)
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{
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const BcOp& op = ops[i];
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for (u32 mask = 0; mask <= 0xF; mask++)
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{
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SCOPED_TRACE(::testing::Message()
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<< op.name << " mask=0x" << std::hex << mask);
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CheckOneCase(op, mask, kFs, kFt, kAcc);
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}
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}
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}
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// The transform shape the EE actually runs: seed ACC via MULAx, accumulate
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// y/z, then finish with the w lane. This is the sequence NASCAR Thunder 2002
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// uses to place car geometry, and it exercises MADDAw with an ACC that a
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// previous macro op just produced rather than one seeded from memory.
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TEST(EeVu0Cop2MaddaBc, MatrixVectorChainFullMaskMatchesInterp)
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{
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EeRecTestHarness h;
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h.EnableVu0Capture();
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h.EnableCop1();
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// Four matrix rows in vf1..vf4, the vector in vf5.
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h.SeedVu0Vf(1, 1.0f, 2.0f, 3.0f, 4.0f);
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h.SeedVu0Vf(2, 5.0f, 6.0f, 7.0f, 8.0f);
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h.SeedVu0Vf(3, 9.0f, 10.0f, 11.0f, 12.0f);
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h.SeedVu0Vf(4, 13.0f, 14.0f, 15.0f, 16.0f);
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h.SeedVu0Vf(5, 0.5f, -1.5f, 2.5f, 1.0f);
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h.SeedVu0Acc(0.0f, 0.0f, 0.0f, 0.0f);
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h.LoadProgram({
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COP2_SPEC2(0xF, 0x18, /*fs*/1, /*ft*/5), // VMULAx ACC = vf1 * vf5.x
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VMADDAy_C2(0xF, /*fs*/2, /*ft*/5), // ACC += vf2 * vf5.y
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VMADDAz_C2(0xF, /*fs*/3, /*ft*/5), // ACC += vf3 * vf5.z
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VMADDAw_C2(0xF, /*fs*/4, /*ft*/5), // ACC += vf4 * vf5.w
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});
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h.Run();
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for (char l : {'x', 'y', 'z', 'w'})
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{
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EXPECT_EQ(h.GetVu0AccBitsJit(l), h.GetVu0AccBitsInterp(l))
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<< "matrix-vector chain ACC." << l;
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}
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}
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// The PS2 VU has no infinities or NaNs: an exponent-0xFF word is an ordinary,
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// very large number. x86 mVU therefore specifies cFs for the whole MADDA
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// broadcast row (mVU_MADDAx/y/z/w in microVU_Upper.inl), clamping Fs to
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// +/-FLT_MAX *before* the multiply. Without that pre-clamp an exp-FF Fs against
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// a zero broadcast lane multiplies as host Inf * 0 = NaN, and the post-op
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// result clamp then folds the NaN to +/-FLT_MAX instead of the architectural 0.
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//
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// A zero in the broadcast lane is exactly what a homogeneous transform feeds
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// the w-lane variant, which is why this shows up in one lane of a family whose
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// four members share an emitter.
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//
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// MSUBAx/y/z/w are deliberately excluded: x86 gives them clampType 0, so their
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// unclamped Fs is a shared, by-design divergence rather than an arm64 defect.
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TEST(EeVu0Cop2MaddaBc, ExpFfFsAgainstZeroBroadcastMatchesInterp)
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{
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constexpr u32 kExpFfPos = 0x7FFFFFFFu; // largest positive exp-FF word
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constexpr u32 kExpFfNeg = 0xFFFFFFFFu;
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constexpr u32 kPosInf = 0x7F800000u;
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for (const BcOp& op : kMaddaOps)
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{
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for (u32 fsBits : {kExpFfPos, kExpFfNeg, kPosInf})
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{
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SCOPED_TRACE(::testing::Message()
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<< op.name << " fs=0x" << std::hex << fsBits);
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EeRecTestHarness h;
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h.EnableVu0Capture();
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h.EnableCop1();
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// Every Fs lane is exp-FF, so whichever lanes the dest mask keeps
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// exercise the missing pre-clamp.
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h.SeedVu0VfBits(1, fsBits, fsBits, fsBits, fsBits);
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// Ft is zero in every lane, so any broadcast lane multiplies by 0.
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h.SeedVu0Vf(2, 0.0f, 0.0f, 0.0f, 0.0f);
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h.SeedVu0Acc(1.0f, 2.0f, 3.0f, 4.0f);
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h.LoadProgram({op.encode(/*mask*/0xF, /*fs*/1, /*ft*/2)});
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h.Run();
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for (char l : {'x', 'y', 'z', 'w'})
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{
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EXPECT_EQ(h.GetVu0AccBitsJit(l), h.GetVu0AccBitsInterp(l))
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<< op.name << " ACC." << l
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<< ": exp-FF Fs against a zero broadcast";
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}
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}
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}
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}
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} // namespace recompiler_tests
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