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Common: Switch movss/d to auto SSE/AVX

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This commit is contained in:
TellowKrinkle
2025-08-24 20:16:24 -05:00
committed by TellowKrinkle
parent 88515d58ab
commit 3599438e57
3 changed files with 40 additions and 13 deletions
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common/emitter/instructions.h
+8 -6
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@@ -459,13 +459,15 @@ namespace x86Emitter
extern void xMOVQZX(const xRegisterSSE& dst, const xIndirectVoid& src);
extern void xMOVQZX(const xRegisterSSE& dst, const xRegisterSSE& src);
extern void xMOVSS(const xRegisterSSE& to, const xRegisterSSE& from);
extern void xMOVSS(const xIndirectVoid& to, const xRegisterSSE& from);
extern void xMOVSD(const xRegisterSSE& to, const xRegisterSSE& from);
extern void xMOVSD(const xIndirectVoid& to, const xRegisterSSE& from);
extern void xMOVSS(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2);
static void xMOVSS(const xRegisterSSE& dst, const xRegisterSSE& src) { xMOVSS(dst, dst, src); }
extern void xMOVSS(const xIndirectVoid& dst, const xRegisterSSE& src);
extern void xMOVSD(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2);
static void xMOVSD(const xRegisterSSE& dst, const xRegisterSSE& src) { xMOVSD(dst, dst, src); }
extern void xMOVSD(const xIndirectVoid& dst, const xRegisterSSE& src);
extern void xMOVSSZX(const xRegisterSSE& to, const xIndirectVoid& from);
extern void xMOVSDZX(const xRegisterSSE& to, const xIndirectVoid& from);
extern void xMOVSSZX(const xRegisterSSE& dst, const xIndirectVoid& src);
extern void xMOVSDZX(const xRegisterSSE& dst, const xIndirectVoid& src);
extern void xMOVNTDQA(const xRegisterSSE& to, const xIndirectVoid& from);
extern void xMOVNTDQA(const xIndirectVoid& to, const xRegisterSSE& from);
common/emitter/simd.cpp
+16 -7
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@@ -809,16 +809,25 @@ namespace x86Emitter
//
#define IMPLEMENT_xMOVS(ssd, prefix) \
__fi void xMOV##ssd(const xRegisterSSE& to, const xRegisterSSE& from) \
__fi void xMOV##ssd(const xRegisterSSE& dst, const xRegisterSSE& src1, const xRegisterSSE& src2) \
{ \
if (to != from) \
xOpWrite0F(prefix, 0x10, to, from); \
if (src1 == src2) \
return xMOVAPS(dst, src1); \
SIMDInstructionInfo op = SIMDInstructionInfo(0x10).prefix(); \
const xRegisterSSE* psrc = &src2; \
const xRegisterSSE* pdst = &dst; \
if (x86Emitter::use_avx && src2.IsExtended() && !dst.IsExtended()) \
{ \
op.opcode = 0x11; \
std::swap(psrc, pdst); \
} \
EmitSIMD(op, *pdst, src1, *psrc); \
} \
__fi void xMOV##ssd##ZX(const xRegisterSSE& to, const xIndirectVoid& from) { xOpWrite0F(prefix, 0x10, to, from); } \
__fi void xMOV##ssd(const xIndirectVoid& to, const xRegisterSSE& from) { xOpWrite0F(prefix, 0x11, from, to); }
__fi void xMOV##ssd##ZX(const xRegisterSSE& dst, const xIndirectVoid& src) { EmitSIMD(SIMDInstructionInfo(0x10).prefix().mov(), dst, dst, src); } \
__fi void xMOV##ssd (const xIndirectVoid& dst, const xRegisterSSE& src) { EmitSIMD(SIMDInstructionInfo(0x11).prefix().mov(), src, src, dst); }
IMPLEMENT_xMOVS(SS, 0xf3)
IMPLEMENT_xMOVS(SD, 0xf2)
IMPLEMENT_xMOVS(SS, pf3)
IMPLEMENT_xMOVS(SD, pf2)
//////////////////////////////////////////////////////////////////////////////////////////
// Non-temporal movs only support a register as a target (ie, load form only, no stores)
tests/ctest/common/x86emitter/codegen_tests_main.cpp
+16
View File
@@ -401,6 +401,14 @@ TEST(CodegenTests, SSETest)
CODEGEN_TEST(xMOVDZX(xmm9, ptr[r9]), "66 45 0f 6e 09");
CODEGEN_TEST(xMOVQZX(xmm9, xmm4), "f3 44 0f 7e cc");
CODEGEN_TEST(xMOVQZX(xmm9, ptr[r8]), "f3 45 0f 7e 08");
CODEGEN_TEST(xMOVSS(xmm1, xmm1), "");
CODEGEN_TEST(xMOVSS(xmm1, xmm4), "f3 0f 10 cc");
CODEGEN_TEST(xMOVSS(ptr[rax], xmm8), "f3 44 0f 11 00");
CODEGEN_TEST(xMOVSSZX(xmm8, ptr[r8]), "f3 45 0f 10 00");
CODEGEN_TEST(xMOVSD(xmm4, xmm8), "f2 41 0f 10 e0");
CODEGEN_TEST(xMOVSD(ptr[rcx], xmm3), "f2 0f 11 19");
CODEGEN_TEST(xMOVSDZX(xmm2, ptr[r9]), "f2 41 0f 10 11");
}
TEST(CodegenTests, AVXTest)
@@ -668,6 +676,14 @@ TEST(CodegenTests, AVXTest)
CODEGEN_TEST(xMOVQZX(xmm9, xmm4), "c5 7a 7e cc");
CODEGEN_TEST(xMOVQZX(xmm9, ptr[r8]), "c4 41 7a 7e 08");
CODEGEN_TEST(xMOVSS(xmm1, xmm1), "");
CODEGEN_TEST(xMOVSS(xmm1, xmm4), "c5 f2 10 cc");
CODEGEN_TEST(xMOVSS(ptr[rax], xmm8), "c5 7a 11 00");
CODEGEN_TEST(xMOVSSZX(xmm8, ptr[r8]), "c4 41 7a 10 00");
CODEGEN_TEST(xMOVSD(xmm4, xmm8), "c5 5b 11 c4");
CODEGEN_TEST(xMOVSD(ptr[rcx], xmm3), "c5 fb 11 19");
CODEGEN_TEST(xMOVSDZX(xmm2, ptr[r9]), "c4 c1 7b 10 11");
CODEGEN_TEST(xVMOVAPS(xmm0, xmm1), "c5 f8 28 c1");
CODEGEN_TEST(xVMOVAPS(xmm0, ptr32[rdi]), "c5 f8 28 07");
CODEGEN_TEST(xVMOVAPS(ptr32[rdi], xmm0), "c5 f8 29 07");