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https://github.com/ARMSX2/ARMSX2.git
synced 2026-08-24 16:50:16 -07:00
IOP: Use names for interrupt registers
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@@ -542,7 +542,7 @@ void cdrInterrupt()
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}
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if (cdr.Stat != NoIntr && cdr.Reg2 != 0x18)
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psxHu32(0x1070) |= 0x4;
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psxHu32(HW_ISTAT) |= 0x4;
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CDVD_LOG("Cdr Interrupt %x\n", Irq);
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}
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@@ -620,7 +620,7 @@ void cdrReadInterrupt()
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CDREAD_INT((cdr.Mode & 0x80) ? (cdReadTime / 2) : cdReadTime);
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}
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psxHu32(0x1070) |= 0x4;
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psxHu32(HW_ISTAT) |= 0x4;
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return;
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}
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+3
-2
@@ -4,6 +4,7 @@
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#include "Common.h"
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#include "Hardware.h"
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#include "Gif_Unit.h"
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#include "IopHw.h"
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#include "IopMem.h"
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#include "ps2/HwInternal.h"
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@@ -180,8 +181,8 @@ void _hwWrite32( u32 mem, u32 value )
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PSXCLK = 33868800;
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SPU2::Reset(true);
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setPs1CDVDSpeed(cdvd.Speed);
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psxHu32(0x1f801450) = 0x8;
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psxHu32(0x1f801078) = 1;
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psxHu32(HW_ICFG) = 0x8;
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psxHu32(HW_ICTRL) = 1;
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psxRegs.cycle = cycle;
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}
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if(!(value & 0x100))
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@@ -214,7 +214,7 @@ static void _rcntFireInterrupt(int i, bool isOverflow)
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{
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// IRQ fired
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//DevCon.Warning("Counter %d %s IRQ Fired count %x target %x psx Cycle %d", i, isOverflow ? "Overflow" : "Target", psxCounters[i].count, psxCounters[i].target, psxRegs.cycle);
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psxHu32(0x1070) |= psxCounters[i].interrupt;
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psxHu32(HW_ISTAT) |= psxCounters[i].interrupt;
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iopTestIntc();
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}
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+1
-1
@@ -35,7 +35,7 @@ static const u32
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HW_SIO_BAUD = 0x1f80104e,
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HW_RAM_SIZE = 0x1f801060,
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HW_IREG = 0x1f801070,
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HW_ISTAT = 0x1f801070,
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HW_IMASK = 0x1f801074,
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HW_ICTRL = 0x1f801078,
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+1
-1
@@ -47,6 +47,6 @@ void spu2Irq()
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void iopIntcIrq(uint irqType)
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{
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psxHu32(0x1070) |= 1 << irqType;
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psxHu32(HW_ISTAT) |= 1 << irqType;
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iopTestIntc();
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}
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+4
-4
@@ -228,11 +228,11 @@ __ri void iopEventTest()
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iopEventTestIsActive = false;
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}
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if ((psxHu32(0x1078) != 0) && ((psxHu32(0x1070) & psxHu32(0x1074)) != 0))
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if ((psxHu32(HW_ICTRL) != 0) && ((psxHu32(HW_ISTAT) & psxHu32(HW_IMASK)) != 0))
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{
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if ((psxRegs.CP0.n.Status & 0xFE01) >= 0x401)
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{
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PSXCPU_LOG("Interrupt: %x %x", psxHu32(0x1070), psxHu32(0x1074));
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PSXCPU_LOG("Interrupt: %x %x", psxHu32(HW_ISTAT), psxHu32(HW_IMASK));
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psxException(0, 0);
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iopEventAction = true;
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}
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@@ -241,8 +241,8 @@ __ri void iopEventTest()
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void iopTestIntc()
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{
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if( psxHu32(0x1078) == 0 ) return;
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if( (psxHu32(0x1070) & psxHu32(0x1074)) == 0 ) return;
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if( psxHu32(HW_ICTRL) == 0 ) return;
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if( (psxHu32(HW_ISTAT) & psxHu32(HW_IMASK)) == 0 ) return;
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if( !eeEventTestIsActive )
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{
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@@ -290,13 +290,13 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
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// case 0x05e: hard = serial_baud_read(); break;
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mcase(HW_ICTRL):
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ret = psxHu32(0x1078);
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psxHu32(0x1078) = 0;
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ret = psxHu32(HW_ICTRL);
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psxHu32(HW_ICTRL) = 0;
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break;
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mcase(HW_ICTRL+2):
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ret = psxHu16(0x107a);
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psxHu32(0x1078) = 0; // most likely should clear all 32 bits here.
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ret = psxHu16(HW_ICTRL+2);
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psxHu32(HW_ICTRL) = 0; // most likely should clear all 32 bits here.
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break;
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// ------------------------------------------------------------------------
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@@ -325,7 +325,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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// case 0x05a: serial_control_write( val ); break;
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// case 0x05e: serial_baud_write( val ); break;
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mcase(HW_IREG):
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mcase(HW_ISTAT):
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psxHu(addr) &= val;
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if (val == 0xffffffff) {
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psxHu32(addr) |= 1 << 2;
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@@ -333,7 +333,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
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}
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break;
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mcase(HW_IREG+2):
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mcase(HW_ISTAT+2):
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psxHu(addr) &= val;
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break;
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@@ -58,8 +58,8 @@ static __ri const char* _ioplog_GetHwName( u32 addr, T val )
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// ------------------------------------------------------------------------
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case 0x1f801060:return "RAM_SIZE";
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case HW_IREG: return "IREG";
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case HW_IREG+2: return "IREG_hi";
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case HW_ISTAT: return "ISTAT";
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case HW_ISTAT+2: return "ISTAT_hi";
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case HW_IMASK: return "IMASK";
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case HW_IMASK+2:return "IMASK_hi";
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case HW_ICTRL: return "ICTRL";
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