IOP: Use names for interrupt registers

This commit is contained in:
Ziemas
2026-03-05 10:35:45 -05:00
committed by Ty
parent 4dd0121576
commit 3104fc20da
9 changed files with 20 additions and 19 deletions
+2 -2
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@@ -542,7 +542,7 @@ void cdrInterrupt()
}
if (cdr.Stat != NoIntr && cdr.Reg2 != 0x18)
psxHu32(0x1070) |= 0x4;
psxHu32(HW_ISTAT) |= 0x4;
CDVD_LOG("Cdr Interrupt %x\n", Irq);
}
@@ -620,7 +620,7 @@ void cdrReadInterrupt()
CDREAD_INT((cdr.Mode & 0x80) ? (cdReadTime / 2) : cdReadTime);
}
psxHu32(0x1070) |= 0x4;
psxHu32(HW_ISTAT) |= 0x4;
return;
}
+3 -2
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@@ -4,6 +4,7 @@
#include "Common.h"
#include "Hardware.h"
#include "Gif_Unit.h"
#include "IopHw.h"
#include "IopMem.h"
#include "ps2/HwInternal.h"
@@ -180,8 +181,8 @@ void _hwWrite32( u32 mem, u32 value )
PSXCLK = 33868800;
SPU2::Reset(true);
setPs1CDVDSpeed(cdvd.Speed);
psxHu32(0x1f801450) = 0x8;
psxHu32(0x1f801078) = 1;
psxHu32(HW_ICFG) = 0x8;
psxHu32(HW_ICTRL) = 1;
psxRegs.cycle = cycle;
}
if(!(value & 0x100))
+1 -1
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@@ -214,7 +214,7 @@ static void _rcntFireInterrupt(int i, bool isOverflow)
{
// IRQ fired
//DevCon.Warning("Counter %d %s IRQ Fired count %x target %x psx Cycle %d", i, isOverflow ? "Overflow" : "Target", psxCounters[i].count, psxCounters[i].target, psxRegs.cycle);
psxHu32(0x1070) |= psxCounters[i].interrupt;
psxHu32(HW_ISTAT) |= psxCounters[i].interrupt;
iopTestIntc();
}
+1 -1
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@@ -35,7 +35,7 @@ static const u32
HW_SIO_BAUD = 0x1f80104e,
HW_RAM_SIZE = 0x1f801060,
HW_IREG = 0x1f801070,
HW_ISTAT = 0x1f801070,
HW_IMASK = 0x1f801074,
HW_ICTRL = 0x1f801078,
+1 -1
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@@ -47,6 +47,6 @@ void spu2Irq()
void iopIntcIrq(uint irqType)
{
psxHu32(0x1070) |= 1 << irqType;
psxHu32(HW_ISTAT) |= 1 << irqType;
iopTestIntc();
}
+4 -4
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@@ -228,11 +228,11 @@ __ri void iopEventTest()
iopEventTestIsActive = false;
}
if ((psxHu32(0x1078) != 0) && ((psxHu32(0x1070) & psxHu32(0x1074)) != 0))
if ((psxHu32(HW_ICTRL) != 0) && ((psxHu32(HW_ISTAT) & psxHu32(HW_IMASK)) != 0))
{
if ((psxRegs.CP0.n.Status & 0xFE01) >= 0x401)
{
PSXCPU_LOG("Interrupt: %x %x", psxHu32(0x1070), psxHu32(0x1074));
PSXCPU_LOG("Interrupt: %x %x", psxHu32(HW_ISTAT), psxHu32(HW_IMASK));
psxException(0, 0);
iopEventAction = true;
}
@@ -241,8 +241,8 @@ __ri void iopEventTest()
void iopTestIntc()
{
if( psxHu32(0x1078) == 0 ) return;
if( (psxHu32(0x1070) & psxHu32(0x1074)) == 0 ) return;
if( psxHu32(HW_ICTRL) == 0 ) return;
if( (psxHu32(HW_ISTAT) & psxHu32(HW_IMASK)) == 0 ) return;
if( !eeEventTestIsActive )
{
+4 -4
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@@ -290,13 +290,13 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
// case 0x05e: hard = serial_baud_read(); break;
mcase(HW_ICTRL):
ret = psxHu32(0x1078);
psxHu32(0x1078) = 0;
ret = psxHu32(HW_ICTRL);
psxHu32(HW_ICTRL) = 0;
break;
mcase(HW_ICTRL+2):
ret = psxHu16(0x107a);
psxHu32(0x1078) = 0; // most likely should clear all 32 bits here.
ret = psxHu16(HW_ICTRL+2);
psxHu32(HW_ICTRL) = 0; // most likely should clear all 32 bits here.
break;
// ------------------------------------------------------------------------
+2 -2
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@@ -325,7 +325,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
// case 0x05a: serial_control_write( val ); break;
// case 0x05e: serial_baud_write( val ); break;
mcase(HW_IREG):
mcase(HW_ISTAT):
psxHu(addr) &= val;
if (val == 0xffffffff) {
psxHu32(addr) |= 1 << 2;
@@ -333,7 +333,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
}
break;
mcase(HW_IREG+2):
mcase(HW_ISTAT+2):
psxHu(addr) &= val;
break;
+2 -2
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@@ -58,8 +58,8 @@ static __ri const char* _ioplog_GetHwName( u32 addr, T val )
// ------------------------------------------------------------------------
case 0x1f801060:return "RAM_SIZE";
case HW_IREG: return "IREG";
case HW_IREG+2: return "IREG_hi";
case HW_ISTAT: return "ISTAT";
case HW_ISTAT+2: return "ISTAT_hi";
case HW_IMASK: return "IMASK";
case HW_IMASK+2:return "IMASK_hi";
case HW_ICTRL: return "ICTRL";