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https://github.com/ARMSX2/ARMSX2.git
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Tests: EE FPU overflow against hardware — the max is 0x7FFFFFFF, not FLT_MAX
The only hardware evidence for the EE's top exponent was ps2autotests' fpu/fcr.cpp, which runs MUL.S(0x7F7FFFFF, 0x7F7FFFFF) but prints the result with %f and so records the string "NaN". This captures the bits: 57 EE FPU rows and 8 VU0 macro-mode rows from a real PS2 over ps2link, every value a raw word. The rule they establish is at the top of autocases_fpuovf.h; the generator checks it in exact rational arithmetic across all 47 arithmetic rows. Every console divergence in the capture is shared by both engines and deliberate, since the fast path cannot hold the EE's top binade at all, so the conformance test carries the console column as data, classifies the divergences at the top of the file, and leaves them to the hardware-alignment stage. One gap is not deliberate: recSQRT_S_xmm is the only emitter in iFPU-arm64.cpp that never clamps its operand, and no clamp mode closes the rows it splits. Recorded as a divergence with a DISABLED tripwire, not fixed here.
This commit is contained in:
pstef
@@ -24,14 +24,9 @@
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// engine-vs-engine divergence is not. The console column is therefore carried
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// as data and asserted only by the DISABLED tripwire at the bottom.
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//
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// SQRT.S has left this compromise: both engines scale instead of clamping and
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// match the console, which is what moved rows 44 and 45 out of the value-only
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// column below. ABS.S likewise (ee_fpu_absneg_clamp_tests.cpp). The arithmetic
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// ops cannot follow: their results do exceed what a host single can hold.
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//
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// The measured console divergences, all shared by both engines and all
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// deliberate, for the record:
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// * 17 rows differ in VALUE only -- the +/-FLT_MAX saturation compromise.
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// * 19 rows differ in VALUE only -- the +/-FLT_MAX saturation compromise.
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// DO NOT "fix" posFmax (pcsx2/FPU.cpp:14) globally; that pushes host
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// exponent-255 patterns through every downstream op in the clamp mode
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// nearly every game runs in. ee_fpu_zero_divisor_console_tests.cpp carries
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@@ -40,7 +35,7 @@
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// by DISABLED_UnderflowFlagsNeedFzOff in the FCR conformance file.
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// * 15 rows differ in both, the overflow rows, for the binade reason above.
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// Owned by DISABLED_ExceptionFlagsInProductionFpEnvMissOverflow.
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// * 22 rows match exactly.
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// * 20 rows match exactly.
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#include "autocases_fpuovf.h"
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#include "harness/EeRecTestHarness.h"
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@@ -49,8 +44,6 @@
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#include <gtest/gtest.h>
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#include <ios>
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using namespace recompiler_tests;
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using namespace mips;
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using namespace mips::ee;
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@@ -152,17 +145,6 @@ constexpr EngineDivergence kEngineDivergences[] = {
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{14, true, "mul 2^128, 0.5 -- same"},
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{17, true, "sub 2^128, 2^128 -- interp gets 0, JIT gets Inf-Inf"},
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// CLASS 3 -- the divide-unit ROUNDING axis, one row, and no clamp mode
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// touches it. sqrt(+EEMAX) is inexact in single precision, and the two
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// engines round it differently: the JIT's Fsqrt runs under FPUDivFPCR
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// (round-to-nearest, the divide unit's mode, and the value silicon
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// returns -- 0x5FB504F3), while the interpreter computes in double and
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// narrows under the ambient ChopZero, landing one ULP low at 0x5FB504F2.
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// The JIT is the console-exact side. Closes when the interpreter models
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// the div-unit rounding law; until then the interp's chop value is pinned
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// where each SQRT test asserts it.
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{44, false, "sqrt +EEMAX -- interp narrows under ChopZero, 1 ULP low"},
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// Rows 3, 11 and 16 used to be listed here and are not divergences any
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// more. They were never the operand-clamp axis: their RESULT words were
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// identical on both engines and only FCR31 differed, because the arm64 fast
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@@ -174,15 +156,11 @@ constexpr EngineDivergence kEngineDivergences[] = {
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// question is deferred to the redesign (see the DISABLED tripwires in
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// ee_fpu_fcr_console_conformance_tests.cpp).
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// CLASS 2 used to live here: rows 44 and 45, sqrt of an exponent-255 Ft,
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// where recSQRT_S_xmm was the one emitter in iFPU-arm64.cpp that never
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// clamped its operand at all. That was a defect rather than a mode axis --
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// it did not close under CHECK_FPU_EXTRA_OVERFLOW because there was no gate
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// to turn on -- and it is fixed twice over: first with a clamp matching x86
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// recSQRT_S_xmm, then by dropping the clamp for the |Ft|/4 scaling that
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// lands on the console value (see SqrtMatchesConsoleOnEveryCapturedOperand).
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// Row 45 (sqrt 2^128) is exact and both engines agree on silicon's value;
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// row 44 remains above as CLASS 3, which is a rounding gap, not this one.
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// CLASS 2 -- a real gap rather than a mode axis: recSQRT_S_xmm never clamps
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// Ft, so no clamp mode closes these two rows. Mechanism and fix direction
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// at DISABLED_SqrtOperandClampIsMissing below.
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{44, false, "sqrt +EEMAX -- recSQRT_S_xmm never clamps Ft"},
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{45, false, "sqrt 2^128 -- same"},
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};
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constexpr int kEngineDivergenceCount =
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static_cast<int>(sizeof(kEngineDivergences) / sizeof(kEngineDivergences[0]));
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@@ -206,11 +184,10 @@ const EngineDivergence* FindDivergence(int row)
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// stale -- a row that gets fixed without being removed here fails loudly
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// instead of sitting as a silent allowance.
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// ---------------------------------------------------------------------------
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// Disabled: the interpreter now takes the divide unit's round-to-nearest,
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// which moves SQRT.S off the values these rows were written against.
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// "Tests: EE FPU overflow against hardware" restates them against the
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// console; "Fix: SQRT.S raises invalid on -0 and negative denormals" turns
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// them back on.
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// Disabled here: these rows are restated against the console, but the
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// interpreter's SQRT.S still raises no invalid on -0 and negative
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// denormals. Re-enabled by "Fix: SQRT.S raises invalid on -0 and negative
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// denormals".
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TEST(EeFpuOverflowConsole, DISABLED_EnginesAgreeExceptOnTheDocumentedRows)
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{
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for (int i = 0; i < kCaseCount; ++i)
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@@ -236,14 +213,12 @@ TEST(EeFpuOverflowConsole, DISABLED_EnginesAgreeExceptOnTheDocumentedRows)
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}
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// ---------------------------------------------------------------------------
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// ENABLED. Every listed row must close when the operand clamp is on. The
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// else-branch covers a future entry that does not close: that would be a
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// defect rather than the mode axis.
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// ENABLED. The operand-clamp rows close when the clamp is on; the SQRT rows do
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// not, having no clamp to turn on.
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// ---------------------------------------------------------------------------
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// Disabled with EnginesAgreeExceptOnTheDocumentedRows above, same reason.
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TEST(EeFpuOverflowConsole, DISABLED_OperandClampHealsEveryDocumentedDivergence)
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TEST(EeFpuOverflowConsole, DISABLED_OperandClampHealsEveryDivergenceExceptSqrt)
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{
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ASSERT_GT(kEngineDivergenceCount, 0) << "nothing left to classify";
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for (int i = 0; i < kEngineDivergenceCount; ++i)
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{
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const EngineDivergence& d = kEngineDivergences[i];
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@@ -300,153 +275,32 @@ TEST(EeFpuOverflowConsole, DefaultClampModeSaturatesToFltMaxOnBothEngines)
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}
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// ---------------------------------------------------------------------------
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// Both engines against the console on every SQRT row in the capture.
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// TRIPWIRE. recSQRT_S_xmm is the one emitter in iFPU-arm64.cpp that never
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// clamps its operand: fpuClampInput's twelve call sites cover ADD/SUB/MUL/DIV,
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// RSQRT and the six accumulator forms, and none of them is SQRT. An
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// exponent-255 Ft therefore reaches Fsqrt as a host +Inf and comes back
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// 0x7F7FFFFF, where the interpreter's sqrt(fpuDouble(Ft)) gives 0x5F7FFFFF.
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// CHECK_FPU_EXTRA_OVERFLOW closes the class 1 rows above but not these two:
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// SQRT has no gate to turn on.
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//
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// The capture surfaced this as a clamp defect: recSQRT_S_xmm was the one
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// emitter in iFPU-arm64.cpp that never clamped its operand, so an exponent-255
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// Ft reached Fsqrt as a host +Inf and fpuClampResult flattened the result to
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// 0x7F7FFFFF, while the interpreter's sqrt(fpuDouble(Ft)) gave 0x5F7FFFFF.
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// Clamping SQRT too made both engines say 0x5F7FFFFF, which is not the console
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// value either. They scale instead now -- see SQRT_S (pcsx2/FPU.cpp) and
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// recSQRT_S_xmm (pcsx2/arm64/iFPU-arm64.cpp).
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//
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// Rows 44 and 45 failed until then (console 5fb504f3 / 5f800000, both engines
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// 5f7fffff); row 46's Ft has exponent field 254, never reached the clamp, and
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// passed throughout. Both clamp modes are checked because the clamp this
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// replaced was gated on CHECK_FPU_OVERFLOW.
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// The console gives 5fb504f3 and 5f800000, so the interpreter is the nearer
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// side and the recompiler is what moves. Enable this once recSQRT_S_xmm calls
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// fpuClampInput under CHECK_FPU_EXTRA_OVERFLOW like the rest, then drop rows 44
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// and 45 from kEngineDivergences.
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// ---------------------------------------------------------------------------
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// Disabled with EnginesAgreeExceptOnTheDocumentedRows above, same reason.
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TEST(EeFpuOverflowConsole, DISABLED_SqrtMatchesConsoleOnEveryCapturedOperand)
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TEST(EeFpuOverflowConsole, DISABLED_SqrtOperandClampIsMissing)
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{
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int exp255_rows = 0, control_rows = 0, total_rows = 0;
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for (int i = 0; i < kCaseCount; ++i)
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{
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const FpuOvfCase& c = kCases[i];
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if (c.op != FO_SQRT)
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continue;
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++total_rows;
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SCOPED_TRACE(::testing::Message() << "row " << i << ": " << c.what);
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// CLASS 3 (see kEngineDivergences): where the sqrt is inexact in
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// single precision the interpreter narrows under the ambient ChopZero
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// and lands one ULP below the divide unit's round-to-nearest. The JIT
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// column stays console-exact; the interp's chop value is pinned so the
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// gap closes loudly when the interp models the div-unit rounding law.
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const u32 interp_want =
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(c.result == 0x5FB504F3u) ? 0x5FB504F2u : c.result;
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for (int extra = 0; extra < 2; ++extra)
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{
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SCOPED_TRACE(::testing::Message()
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<< (extra ? "eeClampMode >= 2" : "default clamp mode"));
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const Observed in = RunCase(c, false, extra != 0);
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const Observed ji = RunCase(c, true, extra != 0);
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EXPECT_EQ(in.result, interp_want) << "interp result";
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EXPECT_EQ(ji.result, c.result) << "jit result vs console";
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EXPECT_EQ(in.fcr31, c.fcr31) << "interp FCR31 vs console";
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EXPECT_EQ(ji.fcr31, c.fcr31) << "jit FCR31 vs console";
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}
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if ((c.ft & 0x7F800000u) == 0x7F800000u)
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++exp255_rows;
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else
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++control_rows;
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EXPECT_TRUE(Agree(RunCase(c, false, /*extra_overflow=*/true),
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RunCase(c, true, /*extra_overflow=*/true)))
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<< "SQRT.S still does not clamp its operand under "
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"CHECK_FPU_EXTRA_OVERFLOW";
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}
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EXPECT_GT(total_rows, 0) << "no SQRT rows in the capture; vacuous";
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EXPECT_GT(exp255_rows, 0)
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<< "anti-vacuity: no SQRT row feeds an exponent-255 operand any more, "
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"so the scaling path is never entered";
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EXPECT_GT(control_rows, 0)
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<< "anti-vacuity: no SQRT row with exponent field <= 254 is left, so "
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"nothing here would notice the scaling being applied unconditionally";
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}
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// ---------------------------------------------------------------------------
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// The same property over the whole exponent-255 class rather than the three
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// patterns the capture happens to contain. As host bit patterns those words
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// are infinities, quiet NaNs and signalling NaNs; to the EE they are all large
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// finite floats, so the pool carries every shape. The signalling ones are the
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// half a host-NaN-aware implementation gets wrong -- see recSQRT_S_xmm
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// (iFPU-arm64.cpp) for why the clamp they replaced had to be an integer Umin
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// rather than an Fminnm.
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//
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// The wanted values are correctly-rounded square roots computed by exact
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// integer arithmetic (math.isqrt on the significand, round-to-nearest-even,
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// the divide unit's mode) rather than by a host float. The six marked `true`
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// were read off silicon; the other three are computed only, for class
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// coverage.
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// ---------------------------------------------------------------------------
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// Disabled with EnginesAgreeExceptOnTheDocumentedRows above, same reason.
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TEST(EeFpuOverflowConsole, DISABLED_SqrtMatchesConsoleOnEveryExponent255Operand)
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{
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struct Operand
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{
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u32 ft;
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u32 want; // correctly-rounded sqrt(|ft|) as an EE single (JIT)
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u32 interp_want; // the interp's value -- one ULP low where the sqrt is
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// inexact, because it narrows under the ambient
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// ChopZero rather than the divide unit's nearest.
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// CLASS 3 in kEngineDivergences; equal to `want`
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// everywhere the sqrt is exact or the roundings agree.
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bool witnessed; // true == `want` was read off silicon
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const char* what;
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};
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// Every exponent-255 shape, both signs, plus one exponent-254 control.
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static constexpr Operand kOperands[] = {
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{0x7F800000u, 0x5F800000u, 0x5F800000u, true, "+2^128 (host +Inf)"},
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{0xFF800000u, 0x5F800000u, 0x5F800000u, true, "-2^128 (host -Inf)"},
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{0x7F800001u, 0x5F800000u, 0x5F800000u, false, "exp255 mant 1 (host +sNaN, smallest)"},
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{0xFF800001u, 0x5F800000u, 0x5F800000u, false, "exp255 mant 1 (host -sNaN, smallest)"},
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{0x7FBFFFFFu, 0x5F9CC470u, 0x5F9CC470u, false, "exp255 mant 0x3FFFFF (host +sNaN, largest)"},
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{0x7FC00000u, 0x5F9CC471u, 0x5F9CC470u, true, "exp255 mant 0x400000 (host +qNaN, smallest)"},
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{0x7FFFFFFFu, 0x5FB504F3u, 0x5FB504F2u, true, "+EEMAX (host +qNaN, largest)"},
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{0xFFFFFFFFu, 0x5FB504F3u, 0x5FB504F2u, true, "-EEMAX (host -qNaN, largest)"},
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// Control: exponent field 254, below the scaling branch.
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{0xFF7FFFFFu, 0x5F7FFFFFu, 0x5F7FFFFFu, true, "-FLT_MAX (exp 254 -- CONTROL)"},
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};
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int signalling = 0, controls = 0, witnessed = 0;
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for (const Operand& o : kOperands)
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{
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const FpuOvfCase c{FO_SQRT, 0u, o.ft, 0u, 0u, 0u, false, o.what};
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SCOPED_TRACE(::testing::Message()
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<< o.what << (o.witnessed ? " [silicon]" : " [computed]"));
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// SQRT.S raises invalid on the sign bit alone -- exponent plays no part.
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const u32 want_fcr31 =
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kFcr31FixedOnes | ((o.ft & 0x80000000u) ? 0x00020040u : 0u);
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for (int extra = 0; extra < 2; ++extra)
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{
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SCOPED_TRACE(::testing::Message()
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<< (extra ? "eeClampMode >= 2" : "default clamp mode"));
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const Observed in = RunCase(c, false, extra != 0);
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const Observed ji = RunCase(c, true, extra != 0);
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EXPECT_EQ(in.result, o.interp_want) << "[interp] result";
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EXPECT_EQ(ji.result, o.want) << "[jit] result";
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EXPECT_EQ(in.fcr31, want_fcr31) << "[interp] FCR31";
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EXPECT_EQ(ji.fcr31, want_fcr31) << "[jit] FCR31";
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}
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const u32 mant = o.ft & 0x7FFFFFu;
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if ((o.ft & 0x7F800000u) != 0x7F800000u)
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++controls;
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else if (mant != 0 && (mant & 0x400000u) == 0)
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++signalling;
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if (o.witnessed)
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++witnessed;
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}
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EXPECT_GE(signalling, 3)
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<< "anti-vacuity: the operand pool must keep signalling-NaN patterns -- "
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"they are the class a host-NaN-aware implementation would get wrong";
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EXPECT_GT(controls, 0)
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<< "anti-vacuity: without an exponent <= 254 operand nothing here would "
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"notice the scaling being applied unconditionally";
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EXPECT_GE(witnessed, 5)
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<< "anti-vacuity: most of this pool must stay silicon-witnessed, or the "
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"test is only checking the model against itself";
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}
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// ---------------------------------------------------------------------------
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