mirror of
https://github.com/ARMSX2/ARMSX1.git
synced 2026-08-24 16:53:35 -07:00
Add Makefile, implement more instructions
This commit is contained in:
Lycoder
@@ -0,0 +1,20 @@
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.ONESHELL:
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VERSION_TAG := $(shell git describe --always --tags --abbrev=0)
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COMMIT_HASH := $(shell git rev-parse --short HEAD)
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OS_INFO := $(shell uname -rmo)
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SOURCES := $(wildcard psx/*.c)
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SOURCES += main.c
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bin/psxe main.c:
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mkdir -p bin
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gcc $(SOURCES) -o bin/psxe \
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-DOS_INFO="$(OS_INFO)" \
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-DREP_VERSION="$(VERSION_TAG)" \
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-DREP_COMMIT_HASH="$(COMMIT_HASH)" \
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-g -DLOG_USE_COLOR
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clean:
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rm -rf "bin"
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+6
-2
@@ -16,11 +16,15 @@ void psx_bios_init(psx_bios_t* bios) {
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void psx_bios_load(psx_bios_t* bios, const char* path) {
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FILE* file = fopen(path, "rb");
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if (!file) {
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log_error("Couldn't open BIOS file \"%s\", path");
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exit(1);
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}
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fread(bios->buf, 1, PSX_BIOS_SIZE, file);
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#ifdef PSXE_DEBUG_BIOS
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log_info("Loaded BIOS file \"%s\"", path);
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#endif
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fclose(file);
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}
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@@ -6,14 +6,142 @@
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#include "bus.h"
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typedef struct {
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// Pointer to bus structure
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psx_bus_t* bus;
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// Registers (including $zero and $ra)
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uint32_t r[32];
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uint32_t buf[2], pc;
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// Pipeline simulation (for branch delay slots)
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uint32_t buf[2];
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// Program Counter
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uint32_t pc;
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// Result registers for mult and div
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uint32_t hi, lo;
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/*
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cop0r0 - N/A
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cop0r1 - N/A
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cop0r2 - N/A
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cop0r3 - BPC - Breakpoint on execute (R/W)
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cop0r4 - N/A
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cop0r5 - BDA - Breakpoint on data access (R/W)
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cop0r6 - JUMPDEST - Randomly memorized jump address (R)
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cop0r7 - DCIC - Breakpoint control (R/W)
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cop0r8 - BadVaddr - Bad Virtual Address (R)
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cop0r9 - BDAM - Data Access breakpoint mask (R/W)
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cop0r10 - N/A
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cop0r11 - BPCM - Execute breakpoint mask (R/W)
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cop0r12 - SR - System status register (R/W)
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cop0r13 - CAUSE - Describes the most recently recognised exception (R)
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cop0r14 - EPC - Return Address from Trap (R)
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cop0r15 - PRID - Processor ID (R)
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*/
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// r3 - BPC - Breakpoint on execute (R/W)
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uint32_t cop0_bpc;
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// r5 - BDA - Breakpoint on data access (R/W)
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uint32_t cop0_bda;
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// r6 - JUMPDEST - Randomly memorized jump address (R)
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uint32_t cop0_jumpdest;
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// r7 - DCIC - Breakpoint control (R/W)
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uint32_t cop0_dcic;
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// r8 - BadVaddr - Bad Virtual Address (R)
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uint32_t cop0_badvaddr;
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// r9 - BDAM - Data Access breakpoint mask (R/W)
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uint32_t cop0_bdam;
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// r11 - BPCM - Execute breakpoint mask (R/W)
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uint32_t cop0_bpcm;
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// r12 - SR - System status register (R/W)
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uint32_t cop0_sr;
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// r13 - CAUSE - Describes the most recently recognised exception (R)
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uint32_t cop0_cause;
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// r14 - EPC - Return Address from Trap (R)
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uint32_t cop0_epc;
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// r15 - PRID - Processor ID (R)
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uint32_t cop0_prid;
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} psx_cpu_t;
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/*
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0 IEc Current Interrupt Enable (0=Disable, 1=Enable) ;rfe pops IUp here
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1 KUc Current Kernel/User Mode (0=Kernel, 1=User) ;rfe pops KUp here
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2 IEp Previous Interrupt Disable ;rfe pops IUo here
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3 KUp Previous Kernel/User Mode ;rfe pops KUo here
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4 IEo Old Interrupt Disable ;left unchanged by rfe
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5 KUo Old Kernel/User Mode ;left unchanged by rfe
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6-7 - Not used (zero)
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8-15 Im 8 bit interrupt mask fields. When set the corresponding
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interrupts are allowed to cause an exception.
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16 Isc Isolate Cache (0=No, 1=Isolate)
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When isolated, all load and store operations are targetted
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to the Data cache, and never the main memory.
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(Used by PSX Kernel, in combination with Port FFFE0130h)
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17 Swc Swapped cache mode (0=Normal, 1=Swapped)
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Instruction cache will act as Data cache and vice versa.
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Use only with Isc to access & invalidate Instr. cache entries.
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(Not used by PSX Kernel)
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18 PZ When set cache parity bits are written as 0.
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19 CM Shows the result of the last load operation with the D-cache
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isolated. It gets set if the cache really contained data
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for the addressed memory location.
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20 PE Cache parity error (Does not cause exception)
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21 TS TLB shutdown. Gets set if a programm address simultaneously
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matches 2 TLB entries.
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(initial value on reset allows to detect extended CPU version?)
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22 BEV Boot exception vectors in RAM/ROM (0=RAM/KSEG0, 1=ROM/KSEG1)
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23-24 - Not used (zero)
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25 RE Reverse endianness (0=Normal endianness, 1=Reverse endianness)
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Reverses the byte order in which data is stored in
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memory. (lo-hi -> hi-lo)
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(Affects only user mode, not kernel mode) (?)
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(The bit doesn't exist in PSX ?)
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26-27 - Not used (zero)
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28 CU0 COP0 Enable (0=Enable only in Kernel Mode, 1=Kernel and User Mode)
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29 CU1 COP1 Enable (0=Disable, 1=Enable) (none in PSX)
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30 CU2 COP2 Enable (0=Disable, 1=Enable) (GTE in PSX)
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31 CU3 COP3 Enable (0=Disable, 1=Enable) (none in PSX)
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*/
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#define SR_IEC 0x00000001
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#define SR_KUC 0x00000002
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#define SR_IEP 0x00000004
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#define SR_KUP 0x00000008
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#define SR_IEO 0x00000010
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#define SR_KUO 0x00000020
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#define SR_IM 0x0000ff00
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#define SR_IM0 0x00000100
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#define SR_IM1 0x00000200
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#define SR_IM2 0x00000400
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#define SR_IM3 0x00000800
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#define SR_IM4 0x00001000
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#define SR_IM5 0x00002000
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#define SR_IM6 0x00004000
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#define SR_IM7 0x00008000
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#define SR_ISC 0x00010000
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#define SR_SWC 0x00020000
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#define SR_PZ 0x00040000
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#define SR_CM 0x00080000
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#define SR_PE 0x00100000
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#define SR_TS 0x00200000
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#define SR_BEV 0x00400000
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#define SR_RE 0x02000000
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#define SR_CU0 0x10000000
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#define SR_CU1 0x20000000
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#define SR_CU2 0x40000000
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#define SR_CU3 0x80000000
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psx_cpu_t* psx_cpu_create();
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void psx_cpu_init(psx_cpu_t*, psx_bus_t*);
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void psx_cpu_destroy(psx_cpu_t*);
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