Sd card mux redesign (#3)

* WIP initial commit

* Added TQFN for size comparison

* Added second port with different MUX

example of MAX4948

* 74LVC1G3157 & STM32 version

only 2 SD ports are populated

* Change to 1.27 ribbon cables

* Added MCP23008 alternative

* Small updte of technical layers

* Removal of  board connector

* Addedd missing upload port

* Correction of inverted pins

* Added uSD adapter

* Small changes

Co-authored-by: Jannis <jannis@imserv.org>
This commit is contained in:
Arek
2020-07-09 13:19:27 +02:00
committed by GitHub
parent 141bd0d3ed
commit f3ad467e57
60 changed files with 218460 additions and 550 deletions

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(module "ConnectorMicromatch-8" (layer F.Cu) (tedit 5EEEEED6)
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(module "Pin_2.9x0.8mm" (layer F.Cu) (tedit 5EF30463)
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@@ -0,0 +1,9 @@
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80837
sd-card-adapter/fp-info-cache Normal file

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update=24.06.2020 10:01:35
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
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version=1
NetIExt=net
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version=1
LibDir=
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PageLayoutDescrFile=
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LastIDFExportPath=
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LastGenCADExportPath=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
MinClearance=0
MinTrackWidth=0.15
MinViaAnnulus=0.05
MinViaDiameter=0.4
MinThroughDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
Unconnected_items=error
Track_too_close_to_hole=error
Track_too_close_to_pad=error
Track_too_close_to_via=error
Track_too_close_to_copper_area=error
Track_too_close_to_copper_item=error
Vias_too_close=error
Via_too_close_to_track=error
Via_too_close_to_copper_item=error
Track_ends_too_close=error
Parallel_tracks_too_close=error
Tracks_crossing=error
Track_too_close_to_board_edge=error
Via_too_close_to_board_edge=error
Pad_too_close_to_board_edge=error
Pads_too_close=error
Pad_too_close_to_copper_item=error
Copper_areas_intersect=error
Copper_areas_too_close=error
Copper_zone_net_has_no_pads=error
Via_is_not_connected=warning
Track_has_unconnected_end=warning
Hole_too_close_to_pad=error
Hole_too_close_to_track=error
Drilled_holes_too_close_together=error
Track_width_too_small=error
Track_width_too_large=error
Via_size_too_small=error
Via_annulus_too_small=error
Via_drill_too_small=error
Pad_drill_too_small=error
Via_hole_larger_than_diameter=error
Micro_via_not_allowed=error
Micro_via_through_too_many_layers=error
Micro_via_size_too_small=error
Micro_via_drill_too_small=error
Buried_via_not_allowed=error
NetClass_Track_Width_too_small=error
NetClass_Clearance_too_small=error
NetClass_via_annulus_too_small=error
NetClass_Via_Dia_too_small=error
NetClass_Via_Drill_too_small=error
NetClass_uVia_Dia_too_small=error
NetClass_uVia_Drill_too_small=error
Via_inside_keepout_area=error
Micro_via_inside_keepout_area=error
Buried_via_inside_keepout_area=error
Track_inside_keepout_area=error
Pad_inside_keepout_area=error
Footprint_inside_keepout_area=error
Hole_inside_keepout_area=error
Text_inside_keepout_area=error
Graphic_inside_keepout_area=error
Courtyards_overlap=error
Footprint_has_no_courtyard_defined=ignore
Footprint_has_malformed_courtyard=error
PTH_inside_courtyard=ignore
NPTH_inside_courtyard=ignore
Item_on_a_disabled_layer=error
Board_has_malformed_outline=error
Missing_footprint=warning
Duplicate_footprints=warning
Extra_footprint=warning
Unresolved_text_variable=error
CopperEdgeClearance=0.01
TrackWidth1=0.25
TrackWidth2=0.17
TrackWidth3=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=0
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=0
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
FabLineWidth=0.09999999999999999
FabTextSizeV=1
FabTextSizeH=1
FabTextSizeThickness=0.15
FabTextItalic=0
FabTextUpright=0
OthersLineWidth=0.09999999999999999
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=0
DimensionUnits=0
DimensionPrecision=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
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Enabled=0
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[pcbnew/Layer.In17.Cu]
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[pcbnew/Layer.In23.Cu]
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[pcbnew/Layer.In26.Cu]
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[pcbnew/Layer.In28.Cu]
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[pcbnew/Layer.In29.Cu]
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Enabled=0
[pcbnew/Layer.In30.Cu]
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Enabled=0
[pcbnew/Layer.B.Cu]
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Enabled=1
[pcbnew/Layer.B.Adhes]
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[pcbnew/Layer.F.Adhes]
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[pcbnew/Layer.B.Paste]
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[pcbnew/Layer.F.Paste]
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[pcbnew/Layer.B.SilkS]
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[pcbnew/Layer.F.Mask]
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[pcbnew/Layer.Dwgs.User]
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[pcbnew/Layer.Cmts.User]
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[pcbnew/Layer.Eco1.User]
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[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
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[pcbnew/Layer.B.CrtYd]
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[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=0
[pcbnew/Layer.F.Fab]
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[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
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Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
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View File

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EESchema Schematic File Version 4
LIBS:sd-adapter-cache
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