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Merge tag 'remove-nondt-exynos-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim: cleanup and removing dead code for only support DT for exynos - remove board file for exynos - remove legacy files which are not used anymore - decouple ARCH_EXYNOS from PLAT_S5P * tag 'remove-nondt-exynos-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (35 commits) ARM: EXYNOS: Remove remaining dead code after non-DT support removal ARM: EXYNOS: Remove legacy L2X0 initialization ARM: EXYNOS: Use exynos_init_io() as map_io callback ARM: EXYNOS: Remove custom init_irq callbacks ARM: EXYNOS: Remove mach/regs-usb-phy.h header thermal: exynos: Support both EXYNOS4X12 SoCs ARM: EXYNOS: Remove unused base addresses from mach/map.h header ARM: EXYNOS: Remove mach/irqs.h header ARM: EXYNOS: Select SPARSE_IRQ for Exynos ARM: SAMSUNG: Make legacy MFC support code depend on SAMSUNG_ATAGS ARM: EXYNOS: Remove mach/regs-gpio.h header ARM: EXYNOS: Remove mach/gpio.h ARM: EXYNOS: Remove setup-i2c0.c ARM: EXYNOS: Do not select legacy Kconfig symbols any more ARM: SAMSUNG: Include most of mach/ headers conditionally ARM: EXYNOS: Decouple ARCH_EXYNOS from PLAT_S5P USB: Check for ARCH_EXYNOS separately platform: Check for ARCH_EXYNOS separately ARM: SAMSUNG: Compile legacy IRQ and GPIO PM code only with ATAGS support ARM: EXYNOS: Provide compatibility stubs for PM code in pm-core.h header ... Conflicts: arch/arm/mach-exynos/Kconfig Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -697,6 +697,7 @@ config ARCH_S3C24XX
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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select HAVE_CLK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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@@ -704,6 +705,7 @@ config ARCH_S3C24XX
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select MULTI_IRQ_HANDLER
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select NEED_MACH_GPIO_H
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select NEED_MACH_IO_H
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select SAMSUNG_ATAGS
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help
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Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
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and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
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@@ -719,6 +721,7 @@ config ARCH_S3C64XX
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select CLKSRC_MMIO
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select CPU_V6
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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select HAVE_CLK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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@@ -728,6 +731,7 @@ config ARCH_S3C64XX
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select PLAT_SAMSUNG
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select S3C_DEV_NAND
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select S3C_GPIO_TRACK
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select SAMSUNG_ATAGS
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select SAMSUNG_CLKSRC
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select SAMSUNG_GPIOLIB_4BIT
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select SAMSUNG_IRQ_VIC_TIMER
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@@ -741,11 +745,13 @@ config ARCH_S5P64X0
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select CLKSRC_MMIO
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select CPU_V6
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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select HAVE_CLK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select NEED_MACH_GPIO_H
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select SAMSUNG_ATAGS
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help
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Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
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SMDK6450.
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@@ -757,11 +763,13 @@ config ARCH_S5PC100
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select CLKSRC_MMIO
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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select HAVE_CLK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select NEED_MACH_GPIO_H
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select SAMSUNG_ATAGS
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help
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Samsung S5PC100 series based systems
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@@ -774,12 +782,14 @@ config ARCH_S5PV210
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select CLKSRC_MMIO
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select CPU_V7
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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select HAVE_CLK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select NEED_MACH_GPIO_H
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select NEED_MACH_MEMORY_H
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select SAMSUNG_ATAGS
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help
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Samsung S5PV210/S5PC110 series based systems
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@@ -787,7 +797,9 @@ config ARCH_EXYNOS
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bool "Samsung EXYNOS"
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select ARCH_HAS_CPUFREQ
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select ARCH_HAS_HOLES_MEMORYMODEL
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_SPARSEMEM_ENABLE
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select ARM_GIC
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select CLKDEV_LOOKUP
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select COMMON_CLK
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select CPU_V7
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@@ -796,8 +808,9 @@ config ARCH_EXYNOS
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select NEED_MACH_GPIO_H
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select NEED_MACH_MEMORY_H
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select SPARSE_IRQ
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select USE_OF
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help
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Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
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@@ -199,6 +199,7 @@ machine-$(CONFIG_ARCH_KEYSTONE) += keystone
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# Platform directory name. This list is sorted alphanumerically
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# by CONFIG_* macro name.
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plat-$(CONFIG_ARCH_EXYNOS) += samsung
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plat-$(CONFIG_ARCH_OMAP) += omap
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plat-$(CONFIG_ARCH_S3C64XX) += samsung
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plat-$(CONFIG_PLAT_IOP) += iop
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@@ -14,6 +14,7 @@ menu "SAMSUNG EXYNOS SoCs Support"
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config ARCH_EXYNOS4
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bool "SAMSUNG EXYNOS4"
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default y
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select GIC_NON_BANKED
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select HAVE_ARM_SCU if SMP
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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@@ -89,329 +90,11 @@ config SOC_EXYNOS5440
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help
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Enable EXYNOS5440 SoC support
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config EXYNOS_ATAGS
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bool "ATAGS based boot for EXYNOS (deprecated)"
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depends on !ARCH_MULTIPLATFORM
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depends on ATAGS
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default y
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help
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The EXYNOS platform is moving towards being completely probed
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through device tree. This enables support for board files using
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the traditional ATAGS boot format.
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Note that this option is not available for multiplatform builds.
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if EXYNOS_ATAGS
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config EXYNOS_DEV_DMA
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bool
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help
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Compile in amba device definitions for DMA controller
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config EXYNOS4_DEV_AHCI
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bool
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help
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Compile in platform device definitions for AHCI
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config EXYNOS4_SETUP_FIMD0
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bool
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help
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Common setup code for FIMD0.
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config EXYNOS4_DEV_USB_OHCI
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bool
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help
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Compile in platform device definition for USB OHCI
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config EXYNOS4_SETUP_I2C1
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bool
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help
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Common setup code for i2c bus 1.
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config EXYNOS4_SETUP_I2C2
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bool
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help
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Common setup code for i2c bus 2.
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config EXYNOS4_SETUP_I2C3
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bool
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help
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Common setup code for i2c bus 3.
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config EXYNOS4_SETUP_I2C4
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bool
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help
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Common setup code for i2c bus 4.
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config EXYNOS4_SETUP_I2C5
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bool
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help
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Common setup code for i2c bus 5.
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config EXYNOS4_SETUP_I2C6
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bool
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help
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Common setup code for i2c bus 6.
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config EXYNOS4_SETUP_I2C7
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bool
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help
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Common setup code for i2c bus 7.
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config EXYNOS4_SETUP_KEYPAD
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bool
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help
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Common setup code for keypad.
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config EXYNOS4_SETUP_SDHCI
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bool
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select EXYNOS4_SETUP_SDHCI_GPIO
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help
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Internal helper functions for EXYNOS4 based SDHCI systems.
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config EXYNOS4_SETUP_SDHCI_GPIO
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bool
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help
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Common setup code for SDHCI gpio.
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config EXYNOS4_SETUP_FIMC
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bool
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help
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Common setup code for the camera interfaces.
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config EXYNOS4_SETUP_USB_PHY
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bool
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help
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Common setup code for USB PHY controller
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config EXYNOS_SETUP_SPI
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bool
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help
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Common setup code for SPI GPIO configurations.
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# machine support
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if ARCH_EXYNOS4
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comment "EXYNOS4210 Boards"
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config MACH_SMDKC210
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bool "SMDKC210"
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select MACH_SMDKV310
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help
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Machine support for Samsung SMDKC210
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config MACH_SMDKV310
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bool "SMDKV310"
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select CPU_EXYNOS4210
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select EXYNOS4_DEV_AHCI
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select EXYNOS4_DEV_USB_OHCI
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_KEYPAD
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_SYSMMU
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select S3C24XX_PWM
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC1
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_I2C1
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select S3C_DEV_RTC
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select S3C_DEV_USB_HSOTG
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select S3C_DEV_WDT
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select S5P_DEV_FIMC0
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select S5P_DEV_FIMC1
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select S5P_DEV_FIMC2
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select S5P_DEV_FIMC3
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select S5P_DEV_FIMD0
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select S5P_DEV_G2D
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select S5P_DEV_I2C_HDMIPHY
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select S5P_DEV_JPEG
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select S5P_DEV_MFC
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select S5P_DEV_TV
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select S5P_DEV_USB_EHCI
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select SAMSUNG_DEV_BACKLIGHT
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select SAMSUNG_DEV_KEYPAD
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select SAMSUNG_DEV_PWM
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help
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Machine support for Samsung SMDKV310
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config MACH_ARMLEX4210
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bool "ARMLEX4210"
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select CPU_EXYNOS4210
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select EXYNOS4_DEV_AHCI
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS_DEV_DMA
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select S3C_DEV_HSMMC
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select S3C_DEV_HSMMC2
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select S3C_DEV_HSMMC3
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select S3C_DEV_RTC
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select S3C_DEV_WDT
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help
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Machine support for Samsung ARMLEX4210 based on EXYNOS4210
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|
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config MACH_UNIVERSAL_C210
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bool "Mobile UNIVERSAL_C210 Board"
|
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select CLKSRC_MMIO
|
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select CLKSRC_SAMSUNG_PWM
|
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select CPU_EXYNOS4210
|
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select EXYNOS4_SETUP_FIMC
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select EXYNOS4_SETUP_FIMD0
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select EXYNOS4_SETUP_I2C1
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select EXYNOS4_SETUP_I2C3
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select EXYNOS4_SETUP_I2C5
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select EXYNOS4_SETUP_SDHCI
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select EXYNOS4_SETUP_USB_PHY
|
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select EXYNOS_DEV_DMA
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select EXYNOS_DEV_SYSMMU
|
||||
select S3C_DEV_HSMMC
|
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select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C3
|
||||
select S3C_DEV_I2C5
|
||||
select S3C_DEV_USB_HSOTG
|
||||
select S5P_DEV_CSIS0
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_FIMD0
|
||||
select S5P_DEV_G2D
|
||||
select S5P_DEV_I2C_HDMIPHY
|
||||
select S5P_DEV_JPEG
|
||||
select S5P_DEV_MFC
|
||||
select S5P_DEV_ONENAND
|
||||
select S5P_DEV_TV
|
||||
select S5P_GPIO_INT
|
||||
select S5P_SETUP_MIPIPHY
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
|
||||
config MACH_NURI
|
||||
bool "Mobile NURI Board"
|
||||
select CPU_EXYNOS4210
|
||||
select EXYNOS4_SETUP_FIMC
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C5
|
||||
select EXYNOS4_SETUP_I2C6
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select EXYNOS4_SETUP_USB_PHY
|
||||
select EXYNOS_DEV_DMA
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C3
|
||||
select S3C_DEV_I2C5
|
||||
select S3C_DEV_I2C6
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_USB_HSOTG
|
||||
select S3C_DEV_WDT
|
||||
select S5P_DEV_CSIS0
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_FIMD0
|
||||
select S5P_DEV_G2D
|
||||
select S5P_DEV_JPEG
|
||||
select S5P_DEV_MFC
|
||||
select S5P_DEV_USB_EHCI
|
||||
select S5P_GPIO_INT
|
||||
select S5P_SETUP_MIPIPHY
|
||||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_PWM
|
||||
help
|
||||
Machine support for Samsung Mobile NURI Board.
|
||||
|
||||
config MACH_ORIGEN
|
||||
bool "ORIGEN"
|
||||
select CPU_EXYNOS4210
|
||||
select EXYNOS4_DEV_USB_OHCI
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select EXYNOS4_SETUP_USB_PHY
|
||||
select EXYNOS_DEV_DMA
|
||||
select EXYNOS_DEV_SYSMMU
|
||||
select S3C24XX_PWM
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_USB_HSOTG
|
||||
select S3C_DEV_WDT
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_FIMD0
|
||||
select S5P_DEV_G2D
|
||||
select S5P_DEV_I2C_HDMIPHY
|
||||
select S5P_DEV_JPEG
|
||||
select S5P_DEV_MFC
|
||||
select S5P_DEV_TV
|
||||
select S5P_DEV_USB_EHCI
|
||||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select SAMSUNG_DEV_PWM
|
||||
help
|
||||
Machine support for ORIGEN based on Samsung EXYNOS4210
|
||||
|
||||
comment "EXYNOS4212 Boards"
|
||||
|
||||
config MACH_SMDK4212
|
||||
bool "SMDK4212"
|
||||
select EXYNOS4_SETUP_FIMD0
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C3
|
||||
select EXYNOS4_SETUP_I2C7
|
||||
select EXYNOS4_SETUP_KEYPAD
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select EXYNOS4_SETUP_USB_PHY
|
||||
select EXYNOS_DEV_DMA
|
||||
select EXYNOS_DEV_SYSMMU
|
||||
select S3C24XX_PWM
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C3
|
||||
select S3C_DEV_I2C7
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_USB_HSOTG
|
||||
select S3C_DEV_WDT
|
||||
select S5P_DEV_FIMC0
|
||||
select S5P_DEV_FIMC1
|
||||
select S5P_DEV_FIMC2
|
||||
select S5P_DEV_FIMC3
|
||||
select S5P_DEV_FIMD0
|
||||
select S5P_DEV_MFC
|
||||
select SAMSUNG_DEV_BACKLIGHT
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SOC_EXYNOS4212
|
||||
help
|
||||
Machine support for Samsung SMDK4212
|
||||
|
||||
comment "EXYNOS4412 Boards"
|
||||
|
||||
config MACH_SMDK4412
|
||||
bool "SMDK4412"
|
||||
select MACH_SMDK4212
|
||||
select SOC_EXYNOS4412
|
||||
help
|
||||
Machine support for Samsung SMDK4412
|
||||
endif
|
||||
|
||||
endif
|
||||
|
||||
comment "Flattened Device Tree based board for EXYNOS SoCs"
|
||||
|
||||
config MACH_EXYNOS4_DT
|
||||
bool "Samsung Exynos4 Machine using device tree"
|
||||
default y
|
||||
depends on ARCH_EXYNOS4
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
@@ -419,7 +102,6 @@ config MACH_EXYNOS4_DT
|
||||
select CPU_EXYNOS4210
|
||||
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
|
||||
select S5P_DEV_MFC
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung Exynos4 machine with device tree enabled.
|
||||
Select this if a fdt blob is available for the Exynos4 SoC based board.
|
||||
@@ -433,28 +115,10 @@ config MACH_EXYNOS5_DT
|
||||
select ARM_AMBA
|
||||
select CLKSRC_OF
|
||||
select USB_ARCH_HAS_XHCI
|
||||
select USE_OF
|
||||
help
|
||||
Machine support for Samsung EXYNOS5 machine with device tree enabled.
|
||||
Select this if a fdt blob is available for the EXYNOS5 SoC based board.
|
||||
|
||||
if ARCH_EXYNOS4
|
||||
|
||||
comment "Configuration for HSMMC 8-bit bus width"
|
||||
|
||||
config EXYNOS4_SDHCI_CH0_8BIT
|
||||
bool "Channel 0 with 8-bit bus"
|
||||
help
|
||||
Support HSMMC Channel 0 8-bit bus.
|
||||
If selected, Channel 1 is disabled.
|
||||
|
||||
config EXYNOS4_SDHCI_CH2_8BIT
|
||||
bool "Channel 2 with 8-bit bus"
|
||||
help
|
||||
Support HSMMC Channel 2 8-bit bus.
|
||||
If selected, Channel 3 is disabled.
|
||||
endif
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
||||
@@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
|
||||
|
||||
# machine support
|
||||
|
||||
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o
|
||||
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
|
||||
obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
|
||||
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
|
||||
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
|
||||
obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o
|
||||
|
||||
obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
|
||||
obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
|
||||
|
||||
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
|
||||
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
|
||||
|
||||
# device support
|
||||
|
||||
obj-y += dev-uart.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
|
||||
obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
|
||||
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY) += setup-usb-phy.o
|
||||
obj-$(CONFIG_EXYNOS_SETUP_SPI) += setup-spi.o
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -19,9 +19,7 @@ void exynos_init_time(void);
|
||||
extern unsigned long xxti_f, xusbxti_f;
|
||||
|
||||
struct map_desc;
|
||||
void exynos_init_io(struct map_desc *mach_desc, int size);
|
||||
void exynos4_init_irq(void);
|
||||
void exynos5_init_irq(void);
|
||||
void exynos_init_io(void);
|
||||
void exynos4_restart(char mode, const char *cmd);
|
||||
void exynos5_restart(char mode, const char *cmd);
|
||||
void exynos_init_late(void);
|
||||
|
||||
@@ -1,255 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos4/dev-ahci.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - AHCI support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ahci_platform.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
/* PHY Control Register */
|
||||
#define SATA_CTRL0 0x0
|
||||
/* PHY Link Control Register */
|
||||
#define SATA_CTRL1 0x4
|
||||
/* PHY Status Register */
|
||||
#define SATA_PHY_STATUS 0x8
|
||||
|
||||
#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
|
||||
#define SATA_CTRL0_SPEED_MODE (1 << 26)
|
||||
#define SATA_CTRL0_M_PHY_CAL (1 << 19)
|
||||
#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
|
||||
#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
|
||||
#define SATA_CTRL0_PHY_POR_N (1 << 8)
|
||||
|
||||
#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
|
||||
#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
|
||||
#define SATA_CTRL1_RST_RX_N (1 << 6)
|
||||
#define SATA_CTRL1_RST_TX_N (1 << 5)
|
||||
|
||||
#define SATA_PHY_STATUS_CMU_OK (1 << 18)
|
||||
#define SATA_PHY_STATUS_LANE_OK (1 << 16)
|
||||
|
||||
#define LANE0 0x200
|
||||
#define COM_LANE 0xA00
|
||||
|
||||
#define HOST_PORTS_IMPL 0xC
|
||||
#define SCLK_SATA_FREQ (67 * MHZ)
|
||||
|
||||
static void __iomem *phy_base, *phy_ctrl;
|
||||
|
||||
struct phy_reg {
|
||||
u8 reg;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
/* SATA PHY setup */
|
||||
static const struct phy_reg exynos4_sataphy_cmu[] = {
|
||||
{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
|
||||
{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
|
||||
{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
|
||||
{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
|
||||
{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
|
||||
{ 0x6b, 0xc8 }, { 0x6c, 0x06 },
|
||||
};
|
||||
|
||||
static const struct phy_reg exynos4_sataphy_lane[] = {
|
||||
{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
|
||||
{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
|
||||
{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
|
||||
{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
|
||||
{ 0x51, 0x0f },
|
||||
};
|
||||
|
||||
static const struct phy_reg exynos4_sataphy_comlane[] = {
|
||||
{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
|
||||
{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
|
||||
{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
|
||||
{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
|
||||
{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
|
||||
{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
|
||||
{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
|
||||
{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
|
||||
{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
|
||||
{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
|
||||
{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
|
||||
{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
|
||||
{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
|
||||
{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
|
||||
};
|
||||
|
||||
static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/* wait for maximum of 3 sec */
|
||||
timeout = jiffies + msecs_to_jiffies(3000);
|
||||
while (!(__raw_readl(reg) & bit)) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ahci_phy_init(void __iomem *mmio)
|
||||
{
|
||||
int i, ctrl0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
|
||||
__raw_writeb(exynos4_sataphy_cmu[i].val,
|
||||
phy_base + (exynos4_sataphy_cmu[i].reg * 4));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
|
||||
__raw_writeb(exynos4_sataphy_lane[i].val,
|
||||
phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
|
||||
__raw_writeb(exynos4_sataphy_comlane[i].val,
|
||||
phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
|
||||
|
||||
__raw_writeb(0x07, phy_base);
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
|
||||
SATA_PHY_STATUS_CMU_OK) < 0) {
|
||||
printk(KERN_ERR "PHY CMU not ready\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
__raw_writeb(0x03, phy_base + (COM_LANE * 4));
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
|
||||
SATA_PHY_STATUS_LANE_OK) < 0) {
|
||||
printk(KERN_ERR "PHY LANE not ready\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_M_PHY_CAL;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
|
||||
{
|
||||
struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
|
||||
int val, ret;
|
||||
|
||||
phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
|
||||
if (!phy_base) {
|
||||
dev_err(dev, "failed to allocate memory for SATA PHY\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
|
||||
if (!phy_ctrl) {
|
||||
dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
|
||||
ret = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
clk_sata = clk_get(dev, "sata");
|
||||
if (IS_ERR(clk_sata)) {
|
||||
dev_err(dev, "failed to get sata clock\n");
|
||||
ret = PTR_ERR(clk_sata);
|
||||
clk_sata = NULL;
|
||||
goto err2;
|
||||
|
||||
}
|
||||
clk_enable(clk_sata);
|
||||
|
||||
clk_sataphy = clk_get(dev, "sataphy");
|
||||
if (IS_ERR(clk_sataphy)) {
|
||||
dev_err(dev, "failed to get sataphy clock\n");
|
||||
ret = PTR_ERR(clk_sataphy);
|
||||
clk_sataphy = NULL;
|
||||
goto err3;
|
||||
}
|
||||
clk_enable(clk_sataphy);
|
||||
|
||||
clk_sclk_sata = clk_get(dev, "sclk_sata");
|
||||
if (IS_ERR(clk_sclk_sata)) {
|
||||
dev_err(dev, "failed to get sclk_sata\n");
|
||||
ret = PTR_ERR(clk_sclk_sata);
|
||||
clk_sclk_sata = NULL;
|
||||
goto err4;
|
||||
}
|
||||
clk_enable(clk_sclk_sata);
|
||||
clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
|
||||
|
||||
__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
|
||||
|
||||
/* Enable PHY link control */
|
||||
val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
|
||||
SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
|
||||
__raw_writel(val, phy_ctrl + SATA_CTRL1);
|
||||
|
||||
/* Set communication speed as 3Gbps and enable PHY power */
|
||||
val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
|
||||
SATA_CTRL0_PHY_POR_N;
|
||||
__raw_writel(val, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
/* Port0 is available */
|
||||
__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
|
||||
|
||||
return ahci_phy_init(mmio);
|
||||
|
||||
err4:
|
||||
clk_disable(clk_sataphy);
|
||||
clk_put(clk_sataphy);
|
||||
err3:
|
||||
clk_disable(clk_sata);
|
||||
clk_put(clk_sata);
|
||||
err2:
|
||||
iounmap(phy_ctrl);
|
||||
err1:
|
||||
iounmap(phy_base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct ahci_platform_data exynos4_ahci_pdata = {
|
||||
.init = exynos4_ahci_init,
|
||||
};
|
||||
|
||||
static struct resource exynos4_ahci_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
|
||||
};
|
||||
|
||||
static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_ahci = {
|
||||
.name = "ahci",
|
||||
.id = -1,
|
||||
.resource = exynos4_ahci_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ahci_resource),
|
||||
.dev = {
|
||||
.platform_data = &exynos4_ahci_pdata,
|
||||
.dma_mask = &exynos4_ahci_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
@@ -1,254 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos4/dev-audio.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co. Ltd
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/platform_data/asoc-s3c.h>
|
||||
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/dma.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
|
||||
|
||||
static int exynos4_cfg_i2s(struct platform_device *pdev)
|
||||
{
|
||||
/* configure GPIO for i2s port */
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
case 2:
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct s3c_audio_pdata i2sv5_pdata = {
|
||||
.cfg_gpio = exynos4_cfg_i2s,
|
||||
.type = {
|
||||
.i2s = {
|
||||
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
|
||||
| QUIRK_NEED_RSTCLR,
|
||||
.idma_addr = EXYNOS4_AUDSS_INT_MEM,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource exynos4_i2s0_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
|
||||
[3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_i2s0 = {
|
||||
.name = "samsung-i2s",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
|
||||
.resource = exynos4_i2s0_resource,
|
||||
.dev = {
|
||||
.platform_data = &i2sv5_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata i2sv3_pdata = {
|
||||
.cfg_gpio = exynos4_cfg_i2s,
|
||||
.type = {
|
||||
.i2s = {
|
||||
.quirks = QUIRK_NO_MUXPSR,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource exynos4_i2s1_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_i2s1 = {
|
||||
.name = "samsung-i2s",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
|
||||
.resource = exynos4_i2s1_resource,
|
||||
.dev = {
|
||||
.platform_data = &i2sv3_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource exynos4_i2s2_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_i2s2 = {
|
||||
.name = "samsung-i2s",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
|
||||
.resource = exynos4_i2s2_resource,
|
||||
.dev = {
|
||||
.platform_data = &i2sv3_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
/* PCM Controller platform_devices */
|
||||
|
||||
static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
case 2:
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
default:
|
||||
printk(KERN_DEBUG "Invalid PCM Controller number!");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct s3c_audio_pdata s3c_pcm_pdata = {
|
||||
.cfg_gpio = exynos4_pcm_cfg_gpio,
|
||||
};
|
||||
|
||||
static struct resource exynos4_pcm0_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_pcm0 = {
|
||||
.name = "samsung-pcm",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
|
||||
.resource = exynos4_pcm0_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_pcm_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource exynos4_pcm1_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_pcm1 = {
|
||||
.name = "samsung-pcm",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
|
||||
.resource = exynos4_pcm1_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_pcm_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource exynos4_pcm2_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
|
||||
[2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
|
||||
};
|
||||
|
||||
struct platform_device exynos4_device_pcm2 = {
|
||||
.name = "samsung-pcm",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
|
||||
.resource = exynos4_pcm2_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_pcm_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
/* AC97 Controller platform devices */
|
||||
|
||||
static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
|
||||
}
|
||||
|
||||
static struct resource exynos4_ac97_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
|
||||
[2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
|
||||
[3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
|
||||
[4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata s3c_ac97_pdata = {
|
||||
.cfg_gpio = exynos4_ac97_cfg_gpio,
|
||||
};
|
||||
|
||||
static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_ac97 = {
|
||||
.name = "samsung-ac97",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ac97_resource),
|
||||
.resource = exynos4_ac97_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_ac97_pdata,
|
||||
.dma_mask = &exynos4_ac97_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
/* S/PDIF Controller platform_device */
|
||||
|
||||
static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct resource exynos4_spdif_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
|
||||
[1] = DEFINE_RES_DMA(DMACH_SPDIF),
|
||||
};
|
||||
|
||||
static struct s3c_audio_pdata samsung_spdif_pdata = {
|
||||
.cfg_gpio = exynos4_spdif_cfg_gpio,
|
||||
};
|
||||
|
||||
static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_spdif = {
|
||||
.name = "samsung-spdif",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_spdif_resource),
|
||||
.resource = exynos4_spdif_resource,
|
||||
.dev = {
|
||||
.platform_data = &samsung_spdif_pdata,
|
||||
.dma_mask = &exynos4_spdif_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
@@ -1,52 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos/dev-ohci.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - OHCI support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/platform_data/usb-ohci-exynos.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
#include <plat/usb-phy.h>
|
||||
|
||||
static struct resource exynos4_ohci_resource[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
|
||||
[1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
|
||||
};
|
||||
|
||||
static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_ohci = {
|
||||
.name = "exynos-ohci",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ohci_resource),
|
||||
.resource = exynos4_ohci_resource,
|
||||
.dev = {
|
||||
.dma_mask = &exynos4_ohci_dma_mask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
}
|
||||
};
|
||||
|
||||
void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
|
||||
{
|
||||
struct exynos4_ohci_platdata *npd;
|
||||
|
||||
npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
|
||||
&exynos4_device_ohci);
|
||||
|
||||
if (!npd->phy_init)
|
||||
npd->phy_init = s5p_usb_phy_init;
|
||||
if (!npd->phy_exit)
|
||||
npd->phy_exit = s5p_usb_phy_exit;
|
||||
}
|
||||
@@ -1,55 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Base EXYNOS UART resource and device definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
#define EXYNOS_UART_RESOURCE(_series, _nr) \
|
||||
static struct resource exynos##_series##_uart##_nr##_resource[] = { \
|
||||
[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
|
||||
};
|
||||
|
||||
EXYNOS_UART_RESOURCE(4, 0)
|
||||
EXYNOS_UART_RESOURCE(4, 1)
|
||||
EXYNOS_UART_RESOURCE(4, 2)
|
||||
EXYNOS_UART_RESOURCE(4, 3)
|
||||
|
||||
struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = exynos4_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = exynos4_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = exynos4_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = exynos4_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
|
||||
},
|
||||
};
|
||||
@@ -1,322 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos4/dma.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/pl330.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/irqs.h>
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
static u8 exynos4210_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_MSM_REQ0,
|
||||
DMACH_MSM_REQ2,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
};
|
||||
|
||||
static u8 exynos4212_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI5,
|
||||
};
|
||||
|
||||
static u8 exynos5250_pdma0_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM2_RX,
|
||||
DMACH_PCM2_TX,
|
||||
DMACH_SPI0_RX,
|
||||
DMACH_SPI0_TX,
|
||||
DMACH_SPI2_RX,
|
||||
DMACH_SPI2_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S2_RX,
|
||||
DMACH_I2S2_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART2_RX,
|
||||
DMACH_UART2_TX,
|
||||
DMACH_UART4_RX,
|
||||
DMACH_UART4_TX,
|
||||
DMACH_SLIMBUS0_RX,
|
||||
DMACH_SLIMBUS0_TX,
|
||||
DMACH_SLIMBUS2_RX,
|
||||
DMACH_SLIMBUS2_TX,
|
||||
DMACH_SLIMBUS4_RX,
|
||||
DMACH_SLIMBUS4_TX,
|
||||
DMACH_AC97_MICIN,
|
||||
DMACH_AC97_PCMIN,
|
||||
DMACH_AC97_PCMOUT,
|
||||
DMACH_MIPI_HSI0,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI4,
|
||||
DMACH_MIPI_HSI6,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos_pdma0_pdata;
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
|
||||
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
|
||||
|
||||
static u8 exynos4210_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_MSM_REQ1,
|
||||
DMACH_MSM_REQ3,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
};
|
||||
|
||||
static u8 exynos4212_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_MIPI_HSI2,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_SPDIF,
|
||||
DMACH_MIPI_HSI6,
|
||||
DMACH_MIPI_HSI7,
|
||||
};
|
||||
|
||||
static u8 exynos5250_pdma1_peri[] = {
|
||||
DMACH_PCM0_RX,
|
||||
DMACH_PCM0_TX,
|
||||
DMACH_PCM1_RX,
|
||||
DMACH_PCM1_TX,
|
||||
DMACH_SPI1_RX,
|
||||
DMACH_SPI1_TX,
|
||||
DMACH_PWM,
|
||||
DMACH_SPDIF,
|
||||
DMACH_I2S0S_TX,
|
||||
DMACH_I2S0_RX,
|
||||
DMACH_I2S0_TX,
|
||||
DMACH_I2S1_RX,
|
||||
DMACH_I2S1_TX,
|
||||
DMACH_UART0_RX,
|
||||
DMACH_UART0_TX,
|
||||
DMACH_UART1_RX,
|
||||
DMACH_UART1_TX,
|
||||
DMACH_UART3_RX,
|
||||
DMACH_UART3_TX,
|
||||
DMACH_SLIMBUS1_RX,
|
||||
DMACH_SLIMBUS1_TX,
|
||||
DMACH_SLIMBUS3_RX,
|
||||
DMACH_SLIMBUS3_TX,
|
||||
DMACH_SLIMBUS5_RX,
|
||||
DMACH_SLIMBUS5_TX,
|
||||
DMACH_SLIMBUS0AUX_RX,
|
||||
DMACH_SLIMBUS0AUX_TX,
|
||||
DMACH_DISP1,
|
||||
DMACH_MIPI_HSI1,
|
||||
DMACH_MIPI_HSI3,
|
||||
DMACH_MIPI_HSI5,
|
||||
DMACH_MIPI_HSI7,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos_pdma1_pdata;
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos_pdma1, "dma-pl330.1", 0x00041330,
|
||||
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
|
||||
|
||||
static u8 mdma_peri[] = {
|
||||
DMACH_MTOM_0,
|
||||
DMACH_MTOM_1,
|
||||
DMACH_MTOM_2,
|
||||
DMACH_MTOM_3,
|
||||
DMACH_MTOM_4,
|
||||
DMACH_MTOM_5,
|
||||
DMACH_MTOM_6,
|
||||
DMACH_MTOM_7,
|
||||
};
|
||||
|
||||
static struct dma_pl330_platdata exynos_mdma1_pdata = {
|
||||
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
|
||||
.peri_id = mdma_peri,
|
||||
};
|
||||
|
||||
static AMBA_AHB_DEVICE(exynos_mdma1, "dma-pl330.2", 0x00041330,
|
||||
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
|
||||
|
||||
static int __init exynos_dma_init(void)
|
||||
{
|
||||
if (of_have_populated_dt())
|
||||
return 0;
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
exynos_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma0_peri);
|
||||
exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
|
||||
exynos_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4210_pdma1_peri);
|
||||
exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
|
||||
|
||||
if (samsung_rev() == EXYNOS4210_REV_0)
|
||||
exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
|
||||
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
|
||||
exynos_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma0_peri);
|
||||
exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
|
||||
exynos_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos4212_pdma1_peri);
|
||||
exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
|
||||
} else if (soc_is_exynos5250()) {
|
||||
exynos_pdma0_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos5250_pdma0_peri);
|
||||
exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
|
||||
exynos_pdma1_pdata.nr_valid_peri =
|
||||
ARRAY_SIZE(exynos5250_pdma1_peri);
|
||||
exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
|
||||
|
||||
exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
|
||||
exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
|
||||
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
|
||||
exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
|
||||
exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
|
||||
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
|
||||
exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
|
||||
exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
|
||||
exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
|
||||
}
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
|
||||
amba_device_register(&exynos_pdma0_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
|
||||
dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
|
||||
dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos_pdma1_device, &iomem_resource);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
|
||||
amba_device_register(&exynos_mdma1_device, &iomem_resource);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(exynos_dma_init);
|
||||
@@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = {
|
||||
|
||||
void __init exynos_firmware_init(void)
|
||||
{
|
||||
if (of_have_populated_dt()) {
|
||||
struct device_node *nd;
|
||||
const __be32 *addr;
|
||||
struct device_node *nd;
|
||||
const __be32 *addr;
|
||||
|
||||
nd = of_find_compatible_node(NULL, NULL,
|
||||
"samsung,secure-firmware");
|
||||
if (!nd)
|
||||
return;
|
||||
nd = of_find_compatible_node(NULL, NULL,
|
||||
"samsung,secure-firmware");
|
||||
if (!nd)
|
||||
return;
|
||||
|
||||
addr = of_get_address(nd, 0, NULL, NULL);
|
||||
if (!addr) {
|
||||
pr_err("%s: No address specified.\n", __func__);
|
||||
return;
|
||||
}
|
||||
addr = of_get_address(nd, 0, NULL, NULL);
|
||||
if (!addr) {
|
||||
pr_err("%s: No address specified.\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
pr_info("Running under secure firmware.\n");
|
||||
|
||||
@@ -1,289 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - GPIO lib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H
|
||||
#define __ASM_ARCH_GPIO_H __FILE__
|
||||
|
||||
/* Macro for EXYNOS GPIO numbering */
|
||||
|
||||
#define EXYNOS_GPIO_NEXT(__gpio) \
|
||||
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
|
||||
|
||||
/* EXYNOS4 GPIO bank sizes */
|
||||
|
||||
#define EXYNOS4_GPIO_A0_NR (8)
|
||||
#define EXYNOS4_GPIO_A1_NR (6)
|
||||
#define EXYNOS4_GPIO_B_NR (8)
|
||||
#define EXYNOS4_GPIO_C0_NR (5)
|
||||
#define EXYNOS4_GPIO_C1_NR (5)
|
||||
#define EXYNOS4_GPIO_D0_NR (4)
|
||||
#define EXYNOS4_GPIO_D1_NR (4)
|
||||
#define EXYNOS4_GPIO_E0_NR (5)
|
||||
#define EXYNOS4_GPIO_E1_NR (8)
|
||||
#define EXYNOS4_GPIO_E2_NR (6)
|
||||
#define EXYNOS4_GPIO_E3_NR (8)
|
||||
#define EXYNOS4_GPIO_E4_NR (8)
|
||||
#define EXYNOS4_GPIO_F0_NR (8)
|
||||
#define EXYNOS4_GPIO_F1_NR (8)
|
||||
#define EXYNOS4_GPIO_F2_NR (8)
|
||||
#define EXYNOS4_GPIO_F3_NR (6)
|
||||
#define EXYNOS4_GPIO_J0_NR (8)
|
||||
#define EXYNOS4_GPIO_J1_NR (5)
|
||||
#define EXYNOS4_GPIO_K0_NR (7)
|
||||
#define EXYNOS4_GPIO_K1_NR (7)
|
||||
#define EXYNOS4_GPIO_K2_NR (7)
|
||||
#define EXYNOS4_GPIO_K3_NR (7)
|
||||
#define EXYNOS4_GPIO_L0_NR (8)
|
||||
#define EXYNOS4_GPIO_L1_NR (3)
|
||||
#define EXYNOS4_GPIO_L2_NR (8)
|
||||
#define EXYNOS4_GPIO_X0_NR (8)
|
||||
#define EXYNOS4_GPIO_X1_NR (8)
|
||||
#define EXYNOS4_GPIO_X2_NR (8)
|
||||
#define EXYNOS4_GPIO_X3_NR (8)
|
||||
#define EXYNOS4_GPIO_Y0_NR (6)
|
||||
#define EXYNOS4_GPIO_Y1_NR (4)
|
||||
#define EXYNOS4_GPIO_Y2_NR (6)
|
||||
#define EXYNOS4_GPIO_Y3_NR (8)
|
||||
#define EXYNOS4_GPIO_Y4_NR (8)
|
||||
#define EXYNOS4_GPIO_Y5_NR (8)
|
||||
#define EXYNOS4_GPIO_Y6_NR (8)
|
||||
#define EXYNOS4_GPIO_Z_NR (7)
|
||||
|
||||
/* EXYNOS4 GPIO bank numbers */
|
||||
|
||||
enum exynos4_gpio_number {
|
||||
EXYNOS4_GPIO_A0_START = 0,
|
||||
EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
|
||||
EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
|
||||
EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
|
||||
EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
|
||||
EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
|
||||
EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
|
||||
EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
|
||||
EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
|
||||
EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
|
||||
EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
|
||||
EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
|
||||
EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
|
||||
EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
|
||||
EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
|
||||
EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
|
||||
EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
|
||||
EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
|
||||
EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
|
||||
EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
|
||||
EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
|
||||
EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
|
||||
EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
|
||||
EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
|
||||
EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
|
||||
EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
|
||||
EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
|
||||
EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
|
||||
EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
|
||||
EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
|
||||
EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
|
||||
EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
|
||||
EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
|
||||
EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
|
||||
EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
|
||||
EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
|
||||
EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
|
||||
};
|
||||
|
||||
/* EXYNOS4 GPIO number definitions */
|
||||
|
||||
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
|
||||
#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
|
||||
#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
|
||||
#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
|
||||
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
|
||||
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
|
||||
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
|
||||
#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
|
||||
#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
|
||||
#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
|
||||
#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
|
||||
#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
|
||||
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
|
||||
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
|
||||
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
|
||||
#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
|
||||
#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
|
||||
#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
|
||||
#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
|
||||
#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
|
||||
#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
|
||||
#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
|
||||
#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
|
||||
#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
|
||||
#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
|
||||
#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
|
||||
#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
|
||||
#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
|
||||
#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
|
||||
#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
|
||||
#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
|
||||
#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
|
||||
#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
|
||||
#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
|
||||
#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
|
||||
#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
|
||||
#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
|
||||
|
||||
/* the end of the EXYNOS4 specific gpios */
|
||||
|
||||
#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
|
||||
|
||||
/* EXYNOS5 GPIO bank sizes */
|
||||
|
||||
#define EXYNOS5_GPIO_A0_NR (8)
|
||||
#define EXYNOS5_GPIO_A1_NR (6)
|
||||
#define EXYNOS5_GPIO_A2_NR (8)
|
||||
#define EXYNOS5_GPIO_B0_NR (5)
|
||||
#define EXYNOS5_GPIO_B1_NR (5)
|
||||
#define EXYNOS5_GPIO_B2_NR (4)
|
||||
#define EXYNOS5_GPIO_B3_NR (4)
|
||||
#define EXYNOS5_GPIO_C0_NR (7)
|
||||
#define EXYNOS5_GPIO_C1_NR (4)
|
||||
#define EXYNOS5_GPIO_C2_NR (7)
|
||||
#define EXYNOS5_GPIO_C3_NR (7)
|
||||
#define EXYNOS5_GPIO_C4_NR (7)
|
||||
#define EXYNOS5_GPIO_D0_NR (4)
|
||||
#define EXYNOS5_GPIO_D1_NR (8)
|
||||
#define EXYNOS5_GPIO_Y0_NR (6)
|
||||
#define EXYNOS5_GPIO_Y1_NR (4)
|
||||
#define EXYNOS5_GPIO_Y2_NR (6)
|
||||
#define EXYNOS5_GPIO_Y3_NR (8)
|
||||
#define EXYNOS5_GPIO_Y4_NR (8)
|
||||
#define EXYNOS5_GPIO_Y5_NR (8)
|
||||
#define EXYNOS5_GPIO_Y6_NR (8)
|
||||
#define EXYNOS5_GPIO_X0_NR (8)
|
||||
#define EXYNOS5_GPIO_X1_NR (8)
|
||||
#define EXYNOS5_GPIO_X2_NR (8)
|
||||
#define EXYNOS5_GPIO_X3_NR (8)
|
||||
#define EXYNOS5_GPIO_E0_NR (8)
|
||||
#define EXYNOS5_GPIO_E1_NR (2)
|
||||
#define EXYNOS5_GPIO_F0_NR (4)
|
||||
#define EXYNOS5_GPIO_F1_NR (4)
|
||||
#define EXYNOS5_GPIO_G0_NR (8)
|
||||
#define EXYNOS5_GPIO_G1_NR (8)
|
||||
#define EXYNOS5_GPIO_G2_NR (2)
|
||||
#define EXYNOS5_GPIO_H0_NR (4)
|
||||
#define EXYNOS5_GPIO_H1_NR (8)
|
||||
#define EXYNOS5_GPIO_V0_NR (8)
|
||||
#define EXYNOS5_GPIO_V1_NR (8)
|
||||
#define EXYNOS5_GPIO_V2_NR (8)
|
||||
#define EXYNOS5_GPIO_V3_NR (8)
|
||||
#define EXYNOS5_GPIO_V4_NR (2)
|
||||
#define EXYNOS5_GPIO_Z_NR (7)
|
||||
|
||||
/* EXYNOS5 GPIO bank numbers */
|
||||
|
||||
enum exynos5_gpio_number {
|
||||
EXYNOS5_GPIO_A0_START = 0,
|
||||
EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
|
||||
EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
|
||||
EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
|
||||
EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
|
||||
EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
|
||||
EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
|
||||
EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
|
||||
EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
|
||||
EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
|
||||
EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
|
||||
EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
|
||||
EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
|
||||
EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
|
||||
EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
|
||||
EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
|
||||
EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
|
||||
EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
|
||||
EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
|
||||
EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
|
||||
EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
|
||||
EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
|
||||
EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
|
||||
EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
|
||||
EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
|
||||
EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
|
||||
EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
|
||||
EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
|
||||
EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
|
||||
EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
|
||||
EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
|
||||
EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
|
||||
EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
|
||||
EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
|
||||
EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
|
||||
EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
|
||||
EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
|
||||
EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
|
||||
EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
|
||||
EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
|
||||
};
|
||||
|
||||
/* EXYNOS5 GPIO number definitions */
|
||||
|
||||
#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
|
||||
#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
|
||||
#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
|
||||
#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
|
||||
#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
|
||||
#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
|
||||
#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
|
||||
#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
|
||||
#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
|
||||
#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
|
||||
#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
|
||||
#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
|
||||
#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
|
||||
#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
|
||||
#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
|
||||
#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
|
||||
#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
|
||||
#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
|
||||
#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
|
||||
#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
|
||||
#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
|
||||
#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
|
||||
#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
|
||||
#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
|
||||
#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
|
||||
#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
|
||||
#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
|
||||
#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
|
||||
#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
|
||||
#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
|
||||
#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
|
||||
#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
|
||||
#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
|
||||
#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
|
||||
#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
|
||||
#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
|
||||
#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
|
||||
#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
|
||||
#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
|
||||
#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
|
||||
|
||||
/* the end of the EXYNOS5 specific gpios */
|
||||
|
||||
#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
|
||||
|
||||
/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
|
||||
|
||||
#define S3C_GPIO_END (EXYNOS5_GPIO_END)
|
||||
|
||||
/* define the number of gpios */
|
||||
|
||||
#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */
|
||||
@@ -1,476 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - IRQ definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IRQS_H
|
||||
#define __ASM_ARCH_IRQS_H __FILE__
|
||||
|
||||
#include <plat/irqs.h>
|
||||
|
||||
/* PPI: Private Peripheral Interrupt */
|
||||
|
||||
#define IRQ_PPI(x) (x + 16)
|
||||
|
||||
/* SPI: Shared Peripheral Interrupt */
|
||||
|
||||
#define IRQ_SPI(x) (x + 32)
|
||||
|
||||
/* COMBINER */
|
||||
|
||||
#define MAX_IRQ_IN_COMBINER 8
|
||||
#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
|
||||
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
|
||||
|
||||
/* For EXYNOS4 and EXYNOS5 */
|
||||
|
||||
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
|
||||
|
||||
/* For EXYNOS4 SoCs */
|
||||
|
||||
#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
|
||||
#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
|
||||
#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
|
||||
#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
|
||||
#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
|
||||
#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
|
||||
#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
|
||||
#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
|
||||
#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
|
||||
#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
|
||||
#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
|
||||
#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
|
||||
#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
|
||||
#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
|
||||
#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
|
||||
#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
|
||||
|
||||
#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
|
||||
#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
|
||||
#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
|
||||
#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
|
||||
#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
|
||||
#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
|
||||
#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
|
||||
#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
|
||||
#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
|
||||
#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
|
||||
#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
|
||||
#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
|
||||
#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
|
||||
#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
|
||||
#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
|
||||
#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
|
||||
|
||||
#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
|
||||
#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
|
||||
#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
|
||||
#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
|
||||
#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
|
||||
#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
|
||||
#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
|
||||
#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
|
||||
#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
|
||||
#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
|
||||
#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
|
||||
#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
|
||||
#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
|
||||
#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
|
||||
#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
|
||||
#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
|
||||
#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
|
||||
|
||||
#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
|
||||
#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
|
||||
#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
|
||||
#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
|
||||
#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
|
||||
#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
|
||||
#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
|
||||
#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
|
||||
|
||||
#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
|
||||
#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
|
||||
|
||||
#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
|
||||
#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
|
||||
#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
|
||||
#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
|
||||
#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
|
||||
#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
|
||||
#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
|
||||
#define EXYNOS4_IRQ_2D IRQ_SPI(89)
|
||||
#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
|
||||
|
||||
#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
|
||||
#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
|
||||
#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
|
||||
#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
|
||||
#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
|
||||
|
||||
#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
|
||||
#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
|
||||
#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
|
||||
#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
|
||||
#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
|
||||
|
||||
#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
|
||||
#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
|
||||
#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
|
||||
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
|
||||
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
|
||||
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
|
||||
#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
|
||||
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
|
||||
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
|
||||
|
||||
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
|
||||
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
|
||||
|
||||
#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
|
||||
#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
|
||||
|
||||
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
|
||||
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
|
||||
|
||||
#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
|
||||
#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
|
||||
#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
|
||||
#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
|
||||
|
||||
#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
|
||||
#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
|
||||
#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
|
||||
#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
|
||||
#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
|
||||
#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
|
||||
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
|
||||
#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
|
||||
|
||||
#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
|
||||
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
|
||||
|
||||
#define EXYNOS4210_MAX_COMBINER_NR 16
|
||||
#define EXYNOS4212_MAX_COMBINER_NR 18
|
||||
#define EXYNOS4412_MAX_COMBINER_NR 20
|
||||
#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
|
||||
|
||||
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
|
||||
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
|
||||
|
||||
/*
|
||||
* For Compatibility:
|
||||
* the default is for EXYNOS4, and
|
||||
* for exynos5, should be re-mapped at function
|
||||
*/
|
||||
|
||||
#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
|
||||
#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
|
||||
#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
|
||||
#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
|
||||
#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
|
||||
|
||||
#define IRQ_WDT EXYNOS4_IRQ_WDT
|
||||
#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
|
||||
#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
|
||||
#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
|
||||
#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
|
||||
|
||||
#define IRQ_IIC EXYNOS4_IRQ_IIC
|
||||
#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
|
||||
#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
|
||||
#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
|
||||
#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
|
||||
#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
|
||||
|
||||
#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
|
||||
#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
|
||||
#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
|
||||
|
||||
#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
|
||||
#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
|
||||
|
||||
#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
|
||||
#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
|
||||
#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
|
||||
#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
|
||||
|
||||
#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
|
||||
|
||||
#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
|
||||
|
||||
#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
|
||||
#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
|
||||
#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
|
||||
#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
|
||||
#define IRQ_JPEG EXYNOS4_IRQ_JPEG
|
||||
#define IRQ_2D EXYNOS4_IRQ_2D
|
||||
|
||||
#define IRQ_MIXER EXYNOS4_IRQ_MIXER
|
||||
#define IRQ_HDMI EXYNOS4_IRQ_HDMI
|
||||
#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
|
||||
#define IRQ_MFC EXYNOS4_IRQ_MFC
|
||||
#define IRQ_SDO EXYNOS4_IRQ_SDO
|
||||
|
||||
#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
|
||||
|
||||
#define IRQ_ADC EXYNOS4_IRQ_ADC0
|
||||
#define IRQ_TC EXYNOS4_IRQ_PEN0
|
||||
|
||||
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
|
||||
|
||||
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
|
||||
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
|
||||
#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
|
||||
|
||||
#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
|
||||
#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
|
||||
|
||||
/* For EXYNOS5 SoCs */
|
||||
|
||||
#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
|
||||
#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
|
||||
#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
|
||||
#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
|
||||
#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
|
||||
#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
|
||||
#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
|
||||
#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
|
||||
#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
|
||||
#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
|
||||
#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
|
||||
#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
|
||||
#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
|
||||
#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
|
||||
#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
|
||||
#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
|
||||
#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
|
||||
#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
|
||||
#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
|
||||
#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
|
||||
#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
|
||||
#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
|
||||
#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
|
||||
#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
|
||||
#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
|
||||
#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
|
||||
#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
|
||||
#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
|
||||
#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
|
||||
#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
|
||||
#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
|
||||
#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
|
||||
#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
|
||||
#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
|
||||
#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
|
||||
#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
|
||||
#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
|
||||
#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
|
||||
#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
|
||||
#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
|
||||
#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
|
||||
#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
|
||||
#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
|
||||
#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
|
||||
#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
|
||||
#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
|
||||
#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
|
||||
#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
|
||||
#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
|
||||
#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
|
||||
#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
|
||||
#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
|
||||
#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
|
||||
#define EXYNOS5_IRQ_2D IRQ_SPI(91)
|
||||
#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
|
||||
#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
|
||||
#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
|
||||
#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
|
||||
#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
|
||||
#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
|
||||
#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
|
||||
#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
|
||||
#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
|
||||
#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
|
||||
#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
|
||||
#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
|
||||
#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
|
||||
#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
|
||||
#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
|
||||
#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
|
||||
#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
|
||||
#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
|
||||
#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
|
||||
#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
|
||||
#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
|
||||
#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
|
||||
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
|
||||
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
|
||||
|
||||
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
|
||||
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
|
||||
#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
|
||||
#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
|
||||
|
||||
/* EXYNOS5440 */
|
||||
|
||||
#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
|
||||
#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
|
||||
|
||||
#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
|
||||
|
||||
#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
|
||||
#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
|
||||
|
||||
#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
|
||||
|
||||
#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
|
||||
#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
|
||||
#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
|
||||
#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
|
||||
#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
|
||||
#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
|
||||
#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
|
||||
#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
|
||||
#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
|
||||
#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
|
||||
#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
|
||||
#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
|
||||
#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
|
||||
#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
|
||||
#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
|
||||
|
||||
#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
|
||||
#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
|
||||
|
||||
#define EXYNOS5_MAX_COMBINER_NR 32
|
||||
|
||||
#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
|
||||
#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
|
||||
#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
|
||||
#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
|
||||
|
||||
#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
|
||||
EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
|
||||
|
||||
#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
|
||||
#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
|
||||
#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
|
||||
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
|
||||
#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
|
||||
|
||||
#ifndef CONFIG_SPARSE_IRQ
|
||||
#define NR_IRQS EXYNOS_NR_IRQS
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IRQS_H */
|
||||
@@ -30,31 +30,6 @@
|
||||
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
|
||||
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
|
||||
|
||||
#define EXYNOS4_PA_FIMC0 0x11800000
|
||||
#define EXYNOS4_PA_FIMC1 0x11810000
|
||||
#define EXYNOS4_PA_FIMC2 0x11820000
|
||||
#define EXYNOS4_PA_FIMC3 0x11830000
|
||||
|
||||
#define EXYNOS4_PA_JPEG 0x11840000
|
||||
|
||||
/* x = 0...1 */
|
||||
#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_G2D 0x12800000
|
||||
|
||||
#define EXYNOS4_PA_I2S0 0x03830000
|
||||
#define EXYNOS4_PA_I2S1 0xE3100000
|
||||
#define EXYNOS4_PA_I2S2 0xE2A00000
|
||||
|
||||
#define EXYNOS4_PA_PCM0 0x03840000
|
||||
#define EXYNOS4_PA_PCM1 0x13980000
|
||||
#define EXYNOS4_PA_PCM2 0x13990000
|
||||
|
||||
#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
|
||||
|
||||
#define EXYNOS4_PA_ONENAND 0x0C000000
|
||||
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
|
||||
|
||||
#define EXYNOS_PA_CHIPID 0x10000000
|
||||
|
||||
#define EXYNOS4_PA_SYSCON 0x10010000
|
||||
@@ -71,10 +46,6 @@
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
||||
#define EXYNOS4_PA_RTC 0x10070000
|
||||
|
||||
#define EXYNOS4_PA_KEYPAD 0x100A0000
|
||||
|
||||
#define EXYNOS4_PA_DMC0 0x10400000
|
||||
#define EXYNOS4_PA_DMC1 0x10410000
|
||||
|
||||
@@ -87,207 +58,22 @@
|
||||
#define EXYNOS5_PA_GIC_DIST 0x10481000
|
||||
|
||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||
#define EXYNOS4_PA_TWD 0x10500600
|
||||
#define EXYNOS4_PA_L2CC 0x10502000
|
||||
|
||||
#define EXYNOS4_PA_TMU 0x100C0000
|
||||
|
||||
#define EXYNOS4_PA_MDMA0 0x10810000
|
||||
#define EXYNOS4_PA_MDMA1 0x12850000
|
||||
#define EXYNOS4_PA_S_MDMA1 0x12840000
|
||||
#define EXYNOS4_PA_PDMA0 0x12680000
|
||||
#define EXYNOS4_PA_PDMA1 0x12690000
|
||||
#define EXYNOS5_PA_MDMA0 0x10800000
|
||||
#define EXYNOS5_PA_MDMA1 0x11C10000
|
||||
#define EXYNOS5_PA_PDMA0 0x121A0000
|
||||
#define EXYNOS5_PA_PDMA1 0x121B0000
|
||||
|
||||
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
|
||||
#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
|
||||
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
|
||||
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
|
||||
#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
|
||||
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
|
||||
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
|
||||
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
|
||||
#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
|
||||
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
|
||||
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
|
||||
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
|
||||
|
||||
#define EXYNOS5_PA_GSC0 0x13E00000
|
||||
#define EXYNOS5_PA_GSC1 0x13E10000
|
||||
#define EXYNOS5_PA_GSC2 0x13E20000
|
||||
#define EXYNOS5_PA_GSC3 0x13E30000
|
||||
|
||||
#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
|
||||
#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
|
||||
#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
|
||||
#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
|
||||
#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
|
||||
#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
|
||||
#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
|
||||
#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
|
||||
#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
|
||||
#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
|
||||
#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
|
||||
#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
|
||||
#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
|
||||
#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
|
||||
#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
|
||||
#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
|
||||
#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
|
||||
#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
|
||||
#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
|
||||
#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
|
||||
#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
|
||||
#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
|
||||
#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
|
||||
#define EXYNOS5_PA_SYSMMU_TV 0x14650000
|
||||
|
||||
#define EXYNOS4_PA_SPI0 0x13920000
|
||||
#define EXYNOS4_PA_SPI1 0x13930000
|
||||
#define EXYNOS4_PA_SPI2 0x13940000
|
||||
#define EXYNOS5_PA_SPI0 0x12D20000
|
||||
#define EXYNOS5_PA_SPI1 0x12D30000
|
||||
#define EXYNOS5_PA_SPI2 0x12D40000
|
||||
|
||||
#define EXYNOS4_PA_GPIO1 0x11400000
|
||||
#define EXYNOS4_PA_GPIO2 0x11000000
|
||||
#define EXYNOS4_PA_GPIO3 0x03860000
|
||||
#define EXYNOS5_PA_GPIO1 0x11400000
|
||||
#define EXYNOS5_PA_GPIO2 0x13400000
|
||||
#define EXYNOS5_PA_GPIO3 0x10D10000
|
||||
#define EXYNOS5_PA_GPIO4 0x03860000
|
||||
|
||||
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
|
||||
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
|
||||
|
||||
#define EXYNOS4_PA_FIMD0 0x11C00000
|
||||
|
||||
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
|
||||
#define EXYNOS4_PA_DWMCI 0x12550000
|
||||
#define EXYNOS5_PA_DWMCI0 0x12200000
|
||||
#define EXYNOS5_PA_DWMCI1 0x12210000
|
||||
#define EXYNOS5_PA_DWMCI2 0x12220000
|
||||
#define EXYNOS5_PA_DWMCI3 0x12230000
|
||||
|
||||
#define EXYNOS4_PA_HSOTG 0x12480000
|
||||
#define EXYNOS4_PA_USB_HSPHY 0x125B0000
|
||||
|
||||
#define EXYNOS4_PA_SATA 0x12560000
|
||||
#define EXYNOS4_PA_SATAPHY 0x125D0000
|
||||
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
|
||||
|
||||
#define EXYNOS4_PA_SROMC 0x12570000
|
||||
#define EXYNOS5_PA_SROMC 0x12250000
|
||||
|
||||
#define EXYNOS4_PA_EHCI 0x12580000
|
||||
#define EXYNOS4_PA_OHCI 0x12590000
|
||||
#define EXYNOS4_PA_HSPHY 0x125B0000
|
||||
#define EXYNOS4_PA_MFC 0x13400000
|
||||
|
||||
#define EXYNOS4_PA_UART 0x13800000
|
||||
#define EXYNOS5_PA_UART 0x12C00000
|
||||
|
||||
#define EXYNOS4_PA_VP 0x12C00000
|
||||
#define EXYNOS4_PA_MIXER 0x12C10000
|
||||
#define EXYNOS4_PA_SDO 0x12C20000
|
||||
#define EXYNOS4_PA_HDMI 0x12D00000
|
||||
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
|
||||
|
||||
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
|
||||
#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_ADC 0x13910000
|
||||
#define EXYNOS4_PA_ADC1 0x13911000
|
||||
|
||||
#define EXYNOS4_PA_AC97 0x139A0000
|
||||
|
||||
#define EXYNOS4_PA_SPDIF 0x139B0000
|
||||
|
||||
#define EXYNOS4_PA_TIMER 0x139D0000
|
||||
#define EXYNOS5_PA_TIMER 0x12DD0000
|
||||
|
||||
#define EXYNOS4_PA_SDRAM 0x40000000
|
||||
#define EXYNOS5_PA_SDRAM 0x40000000
|
||||
|
||||
/* Compatibiltiy Defines */
|
||||
|
||||
#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
|
||||
#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
|
||||
#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
|
||||
#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
|
||||
#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
|
||||
#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
|
||||
#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
|
||||
#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
|
||||
#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
|
||||
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
|
||||
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
|
||||
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
|
||||
#define S3C_PA_RTC EXYNOS4_PA_RTC
|
||||
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
|
||||
#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
|
||||
#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
|
||||
#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
|
||||
#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
|
||||
|
||||
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
|
||||
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
|
||||
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
|
||||
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
|
||||
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
|
||||
#define S5P_PA_JPEG EXYNOS4_PA_JPEG
|
||||
#define S5P_PA_G2D EXYNOS4_PA_G2D
|
||||
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
|
||||
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
|
||||
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
|
||||
#define S5P_PA_MFC EXYNOS4_PA_MFC
|
||||
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
|
||||
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
|
||||
#define S5P_PA_MIXER EXYNOS4_PA_MIXER
|
||||
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
|
||||
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
|
||||
#define S5P_PA_SDO EXYNOS4_PA_SDO
|
||||
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
|
||||
#define S5P_PA_VP EXYNOS4_PA_VP
|
||||
|
||||
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
|
||||
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
|
||||
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
|
||||
|
||||
/* Compatibility UART */
|
||||
|
||||
#define EXYNOS4_PA_UART0 0x13800000
|
||||
#define EXYNOS4_PA_UART1 0x13810000
|
||||
#define EXYNOS4_PA_UART2 0x13820000
|
||||
#define EXYNOS4_PA_UART3 0x13830000
|
||||
#define EXYNOS4_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS5_PA_UART0 0x12C00000
|
||||
#define EXYNOS5_PA_UART1 0x12C10000
|
||||
#define EXYNOS5_PA_UART2 0x12C20000
|
||||
#define EXYNOS5_PA_UART3 0x12C30000
|
||||
|
||||
#define EXYNOS5440_PA_UART0 0x000B0000
|
||||
#define EXYNOS5440_PA_UART1 0x000C0000
|
||||
#define EXYNOS5440_SZ_UART SZ_256
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
|
||||
@@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
|
||||
|
||||
static inline void s3c_pm_arch_prepare_irqs(void)
|
||||
{
|
||||
u32 eintmask = s3c_irqwake_eintmask;
|
||||
|
||||
if (of_have_populated_dt())
|
||||
eintmask = exynos_get_eint_wake_mask();
|
||||
|
||||
__raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
|
||||
__raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
|
||||
__raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
@@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
/* Compatibility definitions to make plat-samsung/pm.c compile */
|
||||
#define IRQ_EINT_BIT(x) 1
|
||||
#define s3c_irqwake_intallow 0
|
||||
#define s3c_irqwake_eintallow 0
|
||||
|
||||
#endif /* __ASM_ARCH_PM_CORE_H */
|
||||
|
||||
@@ -1,40 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - GPIO (including EINT) register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_GPIO_H
|
||||
#define __ASM_ARCH_REGS_GPIO_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
|
||||
#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
|
||||
#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
|
||||
#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
|
||||
#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
|
||||
|
||||
#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
|
||||
|
||||
/* compatibility for plat-s5p/irq-pm.c */
|
||||
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
|
||||
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
|
||||
|
||||
#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
|
||||
#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
|
||||
|
||||
#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
|
||||
#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
|
||||
|
||||
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
|
||||
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_GPIO_H */
|
||||
@@ -1,74 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co.Ltd
|
||||
* Author: Joonyoung Shim <jy0922.shim@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __PLAT_S5P_REGS_USB_PHY_H
|
||||
#define __PLAT_S5P_REGS_USB_PHY_H
|
||||
|
||||
#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
|
||||
|
||||
#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
|
||||
#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
|
||||
#define PHY1_HSIC1_SLEEP (1 << 12)
|
||||
#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
|
||||
#define PHY1_HSIC0_SLEEP (1 << 10)
|
||||
#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
|
||||
|
||||
#define PHY1_STD_NORMAL_MASK (0x7 << 6)
|
||||
#define PHY1_STD_SLEEP (1 << 8)
|
||||
#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
|
||||
#define PHY1_STD_FORCE_SUSPEND (1 << 6)
|
||||
|
||||
#define PHY0_NORMAL_MASK (0x39 << 0)
|
||||
#define PHY0_SLEEP (1 << 5)
|
||||
#define PHY0_OTG_DISABLE (1 << 4)
|
||||
#define PHY0_ANALOG_POWERDOWN (1 << 3)
|
||||
#define PHY0_FORCE_SUSPEND (1 << 0)
|
||||
|
||||
#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
|
||||
#define PHY1_COMMON_ON_N (1 << 7)
|
||||
#define PHY0_COMMON_ON_N (1 << 4)
|
||||
#define PHY0_ID_PULLUP (1 << 2)
|
||||
|
||||
#define EXYNOS4_CLKSEL_SHIFT (0)
|
||||
|
||||
#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
|
||||
#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
|
||||
#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
|
||||
#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
|
||||
|
||||
#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
|
||||
#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
|
||||
#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
|
||||
#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
|
||||
#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
|
||||
#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
|
||||
#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
|
||||
|
||||
#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
|
||||
#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
|
||||
#define HOST_LINK_PORT2_SWRST (1 << 9)
|
||||
#define HOST_LINK_PORT1_SWRST (1 << 8)
|
||||
#define HOST_LINK_PORT0_SWRST (1 << 7)
|
||||
#define HOST_LINK_ALL_SWRST (1 << 6)
|
||||
|
||||
#define PHY1_SWRST_MASK (0x7 << 3)
|
||||
#define PHY1_HSIC_SWRST (1 << 5)
|
||||
#define PHY1_STD_SWRST (1 << 4)
|
||||
#define PHY1_ALL_SWRST (1 << 3)
|
||||
|
||||
#define PHY0_SWRST_MASK (0x7 << 0)
|
||||
#define PHY0_PHYLINK_SWRST (1 << 2)
|
||||
#define PHY0_HLINK_SWRST (1 << 1)
|
||||
#define PHY0_SWRST (1 << 0)
|
||||
|
||||
#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
|
||||
#define FPENABLEN (1 << 0)
|
||||
|
||||
#endif /* __PLAT_S5P_REGS_USB_PHY_H */
|
||||
@@ -1,207 +0,0 @@
|
||||
/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include "common.h"
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG4 | \
|
||||
S5PV210_UFCON_RXTRIG4)
|
||||
|
||||
static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPX2(5),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.max_width = 4,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.max_width = 4,
|
||||
};
|
||||
|
||||
static void __init armlex4210_sdhci_init(void)
|
||||
{
|
||||
s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
|
||||
s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
|
||||
s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
|
||||
}
|
||||
|
||||
static void __init armlex4210_wlan_init(void)
|
||||
{
|
||||
/* enable */
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
|
||||
|
||||
/* reset */
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
|
||||
|
||||
/* wakeup */
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
static struct resource armlex4210_smsc911x_resources[] = {
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
|
||||
[1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
|
||||
| IRQF_TRIGGER_HIGH),
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc9215_config = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
|
||||
};
|
||||
|
||||
static struct platform_device armlex4210_smsc911x = {
|
||||
.name = "smsc911x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
|
||||
.resource = armlex4210_smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc9215_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *armlex4210_devices[] __initdata = {
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&armlex4210_smsc911x,
|
||||
&exynos4_device_ahci,
|
||||
};
|
||||
|
||||
static void __init armlex4210_smsc911x_init(void)
|
||||
{
|
||||
u32 cs1;
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
cs1 = __raw_readl(S5P_SROM_BW) &
|
||||
~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
|
||||
cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
|
||||
(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
|
||||
(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
|
||||
(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
|
||||
S5P_SROM_BW__NCS1__SHIFT;
|
||||
__raw_writel(cs1, S5P_SROM_BW);
|
||||
|
||||
/* set timing for nCS1 suitable for ethernet chip */
|
||||
__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
|
||||
(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
|
||||
(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
|
||||
(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
|
||||
}
|
||||
|
||||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init armlex4210_machine_init(void)
|
||||
{
|
||||
armlex4210_smsc911x_init();
|
||||
|
||||
armlex4210_sdhci_init();
|
||||
|
||||
armlex4210_wlan_init();
|
||||
|
||||
platform_add_devices(armlex4210_devices,
|
||||
ARRAY_SIZE(armlex4210_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
||||
/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
|
||||
.atag_offset = 0x100,
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
.init_time = exynos_init_time,
|
||||
.restart = exynos4_restart,
|
||||
MACHINE_END
|
||||
@@ -23,11 +23,6 @@
|
||||
|
||||
#include "common.h"
|
||||
|
||||
static void __init exynos4_dt_map_io(void)
|
||||
{
|
||||
exynos_init_io(NULL, 0);
|
||||
}
|
||||
|
||||
static void __init exynos4_dt_machine_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
@@ -55,8 +50,7 @@ static void __init exynos4_reserve(void)
|
||||
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
|
||||
/* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
|
||||
.smp = smp_ops(exynos_smp_ops),
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = exynos4_dt_map_io,
|
||||
.map_io = exynos_init_io,
|
||||
.init_early = exynos_firmware_init,
|
||||
.init_machine = exynos4_dt_machine_init,
|
||||
.init_late = exynos_init_late,
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user