improve pinctrl device tree

arch/arm/boot/dts/rk3188.dtsi

@@ -1,6 +1,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pinctrl/rockchip-rk3188.h>
 
 #include "skeleton.dtsi"
 
@@ -174,195 +175,196 @@
 	};
 
 	pinctrl@20008000 {
-			compatible = "rockchip,rk3188-pinctrl";
-			reg = <0x20008000 0xa0>,
-			      <0x20008164 0x1a0>;
-			reg-names = "base", "pull";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
+		compatible = "rockchip,rk3188-pinctrl";
+		reg = <0x20008000 0xa0>,
+		      <0x20008164 0x1a0>;
+		reg-names = "base", "pull";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
 
-			gpio0: gpio0@0x2000a000 {
-				compatible = "rockchip,rk3188-gpio-bank0";
-				reg = <0x2000a000 0x100>,
-				      <0x20004064 0x8>;
-				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-				/*clocks = <&clk_gates8 9>;*/
+		gpio0: gpio0@0x2000a000 {
+			compatible = "rockchip,rk3188-gpio-bank0";
+			reg = <0x2000a000 0x100>,
+			      <0x20004064 0x8>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			/*clocks = <&clk_gates8 9>;*/
 
-				gpio-controller;
-				#gpio-cells = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
 
-				interrupt-controller;
-				#interrupt-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio1@0x2003c000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x2003c000 0x100>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			/*clocks = <&clk_gates8 10>;*/
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio2@2003e000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x2003e000 0x100>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			/*clocks = <&clk_gates8 11>;*/
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio3@20080000 {
+			compatible = "rockchip,gpio-bank";
+			reg = <0x20080000 0x100>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			/*clocks = <&clk_gates8 12>;*/
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		pcfg_pull_up: pcfg_pull_up {
+			bias-pull-up;
+		};
+
+		pcfg_pull_down: pcfg_pull_down {
+			bias-pull-down;
+		};
+
+		pcfg_pull_none: pcfg_pull_none {
+			bias-disable;
+		};
+
+		uart0 {
+			uart0_xfer: uart0-xfer {
+				rockchip,pins = <UART0_SIN &pcfg_pull_none>,
+						<UART0_SOUT &pcfg_pull_none>;
 			};
 
-			gpio1: gpio1@0x2003c000 {
-				compatible = "rockchip,gpio-bank";
-				reg = <0x2003c000 0x100>;
-				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-				/*clocks = <&clk_gates8 10>;*/
-
-				gpio-controller;
-				#gpio-cells = <2>;
-
-				interrupt-controller;
-				#interrupt-cells = <2>;
+			uart0_cts: uart0-cts {
+				rockchip,pins = <UART0_CTSN &pcfg_pull_none>;
 			};
 
-			gpio2: gpio2@2003e000 {
-				compatible = "rockchip,gpio-bank";
-				reg = <0x2003e000 0x100>;
-				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-				/*clocks = <&clk_gates8 11>;*/
-
-				gpio-controller;
-				#gpio-cells = <2>;
-
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			gpio3: gpio3@20080000 {
-				compatible = "rockchip,gpio-bank";
-				reg = <0x20080000 0x100>;
-				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
-				/*clocks = <&clk_gates8 12>;*/
-
-				gpio-controller;
-				#gpio-cells = <2>;
-
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-
-			pcfg_pull_up: pcfg_pull_up {
-				bias-pull-up;
-			};
-
-			pcfg_pull_down: pcfg_pull_down {
-				bias-pull-down;
-			};
-
-			pcfg_pull_none: pcfg_pull_none {
-				bias-disable;
-			};
-
-			uart0 {
-				uart0_xfer: uart0-xfer {
-					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				uart0_cts: uart0-cts {
-					rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				uart0_rts: uart0-rts {
-					rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
-				};
-			};
-
-			uart1 {
-				uart1_xfer: uart1-xfer {
-					rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				uart1_cts: uart1-cts {
-					rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				uart1_rts: uart1-rts {
-					rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
-				};
-			};
-
-			uart2 {
-				uart2_xfer: uart2-xfer {
-					rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
-				};
-				/* no rts / cts for uart2 */
-			};
-
-			uart3 {
-				uart3_xfer: uart3-xfer {
-					rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				uart3_cts: uart3-cts {
-					rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				uart3_rts: uart3-rts {
-					rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
-				};
-			};
-
-			sd0 {
-				sd0_clk: sd0-clk {
-					rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd0_cmd: sd0-cmd {
-					rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd0_cd: sd0-cd {
-					rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd0_wp: sd0-wp {
-					rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd0_pwr: sd0-pwr {
-					rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd0_bus1: sd0-bus-width1 {
-					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd0_bus4: sd0-bus-width4 {
-					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
-				};
-			};
-
-			sd1 {
-				sd1_clk: sd1-clk {
-					rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd1_cmd: sd1-cmd {
-					rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd1_cd: sd1-cd {
-					rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd1_wp: sd1-wp {
-					rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd1_bus1: sd1-bus-width1 {
-					rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
-				};
-
-				sd1_bus4: sd1-bus-width4 {
-					rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
-							<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
-				};
+			uart0_rts: uart0-rts {
+				rockchip,pins = <UART0_RTSN &pcfg_pull_none>;
 			};
 		};
 
+		uart1 {
+			uart1_xfer: uart1-xfer {
+				rockchip,pins = <UART1_SIN &pcfg_pull_none>,
+						<UART1_SOUT &pcfg_pull_none>;
+			};
+
+			uart1_cts: uart1-cts {
+				rockchip,pins = <UART1_CTSN &pcfg_pull_none>;
+			};
+
+			uart1_rts: uart1-rts {
+				rockchip,pins = <UART1_RTSN &pcfg_pull_none>;
+			};
+		};
+
+		uart2 {
+			uart2_xfer: uart2-xfer {
+				rockchip,pins = <UART2_SIN &pcfg_pull_none>,
+						<UART2_SOUT &pcfg_pull_none>;
+			};
+			/* no rts / cts for uart2 */
+		};
+
+		uart3 {
+			uart3_xfer: uart3-xfer {
+				rockchip,pins = <UART3_SIN &pcfg_pull_none>,
+						<UART3_SOUT &pcfg_pull_none>;
+			};
+
+			uart3_cts: uart3-cts {
+				rockchip,pins = <UART3_CTSN &pcfg_pull_none>;
+			};
+
+			uart3_rts: uart3-rts {
+				rockchip,pins = <UART3_RTSN &pcfg_pull_none>;
+			};
+		};
+		
+		sd0 {
+			sd0_clk: sd0-clk {
+				rockchip,pins = <MMC0_CLKOUT &pcfg_pull_none>;
+			};
+
+			sd0_cmd: sd0-cmd {
+				rockchip,pins = <MMC0_CMD &pcfg_pull_none>;
+			};
+
+			sd0_cd: sd0-cd {
+				rockchip,pins = <MMC0_DETN &pcfg_pull_none>;
+			};
+
+			sd0_wp: sd0-wp {
+				rockchip,pins = <MMC0_WRPRT &pcfg_pull_none>;
+			};
+
+			sd0_pwr: sd0-pwr {
+				rockchip,pins = <MMC0_PWREN &pcfg_pull_none>;
+			};
+
+			sd0_bus1: sd0-bus-width1 {
+				rockchip,pins = <MMC0_D0 &pcfg_pull_none>;
+			};
+
+			sd0_bus4: sd0-bus-width4 {
+				rockchip,pins = <MMC0_D0 &pcfg_pull_none>,
+						<MMC0_D1 &pcfg_pull_none>,
+						<MMC0_D2 &pcfg_pull_none>,
+						<MMC0_D3 &pcfg_pull_none>;
+			};
+		};
+
+	
+		sd1 {
+			sd1_clk: sd1-clk {
+				rockchip,pins = <MMC1_CLKOUT &pcfg_pull_none>;
+			};
+
+			sd1_cmd: sd1-cmd {
+				rockchip,pins = <MMC1_CMD &pcfg_pull_none>;
+			};
+
+			sd1_cd: sd1-cd {
+				rockchip,pins = <MMC1_DETN &pcfg_pull_none>;
+			};
+
+			sd1_wp: sd1-wp {
+				rockchip,pins = <MMC1_WRPRT &pcfg_pull_none>;
+			};
+
+			sd1_bus1: sd1-bus-width1 {
+				rockchip,pins = <MMC1_D0 &pcfg_pull_none>;
+			};
+
+			sd1_bus4: sd1-bus-width4 {
+				rockchip,pins = <MMC1_D0 &pcfg_pull_none>,
+						<MMC1_D1 &pcfg_pull_none>,
+						<MMC1_D2 &pcfg_pull_none>,
+						<MMC1_D3 &pcfg_pull_none>;
+			};
+		};
+	};
+
 
 	uart0: serial@10124000 {
 		compatible = "rockchip,serial";
@@ -424,15 +426,5 @@
 		wake-irq = <0>;
 		status = "disabled";
 	};
-	
-	/*sample code for gpio*/
-	leds {
-		compatible = "gpio-leds";
-
-		d2 {
-			label = "d2";
-			gpios = <&gpio0 2 1>;	/* GPIO0-2 level1*/
-		};
-	};
 
 };

drivers/pinctrl/pinctrl-rockchip.c

@@ -185,6 +185,22 @@ struct rockchip_pinctrl {
 	atomic_t			debug_flag;	
 };
 
+struct iomux_mode{
+        unsigned int mode:4,
+                     off:4,
+                     goff:4,
+                     bank:4,
+                     reserve:16;
+};
+
+struct union_mode{
+        union{
+                struct iomux_mode mux;
+                unsigned int mode;
+        };
+};
+
+
 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 {
 	return container_of(gc, struct rockchip_pin_bank, gpio_chip);
@@ -363,9 +379,20 @@ static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 	unsigned long flags;
 	u8 bit;
 	u32 data;
-
-	DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n",
-						__func__, bank->bank_num, pin, mux);
+	struct union_mode m;
+	
+	/* GPIO0_C */
+	/*GPIO0_C0 = 0x0c00, NAND_D8, */
+	/*GPIO0_C1 = 0x0c10, NAND_D9, */
+    
+        m.mode = mux;
+	
+	if((m.mux.bank != bank->bank_num) || (((m.mux.goff - 0x0A) * 8 + m.mux.off ) != pin))
+	{
+		printk("%s:error:mux_bank(%d) != gpio_bank(%d), mux_offset(%d) != gpio_offset(%d)\n",__func__,
+		m.mux.bank, bank->bank_num, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), pin);
+		return;
+	}
 
 	/* get basic quadrupel of mux registers and the correct reg inside */
 	reg += bank->bank_num * 0x10;
@@ -379,6 +406,10 @@ static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 	writel(data, reg);
 
 	spin_unlock_irqrestore(&bank->slock, flags);
+
+	DBG_PINCTRL("%s:GPIO%d-%d mux:0x%x\n", __func__, m.mux.bank, ((m.mux.goff - 0x0A) * 8 + m.mux.off ), mux);
+		
+	DBG_PINCTRL("%s:setting mux of GPIO%d-%d to %d\n", __func__, bank->bank_num, pin, mux&0x3);
 }
 
 #define RK2928_PULL_OFFSET		0x118
@@ -792,6 +823,8 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np,
 	int num;
 	int i, j;
 	int ret;
+	struct union_mode m;
+	
 
 	DBG_PINCTRL("%s:group(%d): %s\n", __func__, index, np->name);
 
@@ -805,8 +838,8 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np,
 	list = of_get_property(np, "rockchip,pins", &size);
 	/* we do not check return since it's safe node passed down */
 	size /= sizeof(*list);
-	if (!size || size % 4) {
-		dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
+	if (!size) {
+		dev_err(info->dev, "wrong pins number size=%d\n",size);
 		return -EINVAL;
 	}
 
@@ -817,13 +850,14 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np,
 	grp->data = devm_kzalloc(info->dev, grp->npins *
 					  sizeof(struct rockchip_pin_config),
 					GFP_KERNEL);
+
 	if (!grp->pins || !grp->data)
 		return -ENOMEM;
 
 	for (i = 0, j = 0; i < size; i += 4, j++) {
 		const __be32 *phandle;
 		struct device_node *np_config;
-
+#if 0
 		num = be32_to_cpu(*list++);
 		bank = bank_num_to_bank(info, num);
 		if (IS_ERR(bank))
@@ -831,7 +865,16 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np,
 
 		grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 		grp->data[j].func = be32_to_cpu(*list++);
+#else	
+		m.mode = be32_to_cpu(*list++);
 
+		bank = bank_num_to_bank(info, m.mux.bank);
+		if (IS_ERR(bank))
+			return PTR_ERR(bank);
+
+		grp->pins[j] = bank->pin_base + (m.mux.goff - 0x0A) * 8 + m.mux.off;
+		grp->data[j].func = m.mode;
+#endif
 		phandle = list++;
 		if (!phandle)
 			return -EINVAL;