mirror of
https://github.com/armbian/linux.git
synced 2026-01-06 10:13:00 -08:00
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Fix wreckage after removal of tickadj; convert to GENERIC_TIME. [MIPS] DECstation defconfig update [MIPS] Fix size of zones_size and zholes_size array [MIPS] BCM1480: Mask pending interrupts against c0_status.im. [MIPS] SB1250: Interrupt handler fixes [MIPS] Remove IT8172-based platforms, ITE 8172G and Globespan IVR support. [MIPS] Remove Atlas and SEAD from feature-removal-schedule. [MIPS] Remove Jaguar and Ocelot family from feature list. [MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems [MIPS] Remove dead DECstation boot code [MIPS] Let gcc align 'struct pt_regs' on 8 bytes boundary
This commit is contained in:
Linus Torvalds
@@ -211,42 +211,6 @@ Who: Nick Piggin <npiggin@suse.de>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: Support for the Momentum / PMC-Sierra Jaguar ATX evaluation board
|
||||
When: September 2006
|
||||
Why: Does no longer build since quite some time, and was never popular,
|
||||
due to the platform being replaced by successor models. Apparently
|
||||
no user base left. It also is one of the last users of
|
||||
WANT_PAGE_VIRTUAL.
|
||||
Who: Ralf Baechle <ralf@linux-mips.org>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: Support for the Momentum Ocelot, Ocelot 3, Ocelot C and Ocelot G
|
||||
When: September 2006
|
||||
Why: Some do no longer build and apparently there is no user base left
|
||||
for these platforms.
|
||||
Who: Ralf Baechle <ralf@linux-mips.org>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: Support for MIPS Technologies' Altas and SEAD evaluation board
|
||||
When: September 2006
|
||||
Why: Some do no longer build and apparently there is no user base left
|
||||
for these platforms. Hardware out of production since several years.
|
||||
Who: Ralf Baechle <ralf@linux-mips.org>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: Support for the IT8172-based platforms, ITE 8172G and Globespan IVR
|
||||
When: September 2006
|
||||
Why: Code does no longer build since at least 2.6.0, apparently there is
|
||||
no user base left for these platforms. Hardware out of production
|
||||
since several years and hardly a trace of the manufacturer left on
|
||||
the net.
|
||||
Who: Ralf Baechle <ralf@linux-mips.org>
|
||||
|
||||
---------------------------
|
||||
|
||||
What: Interrupt only SA_* flags
|
||||
When: Januar 2007
|
||||
Why: The interrupt related SA_* flags are replaced by IRQF_* to move them
|
||||
|
||||
@@ -203,39 +203,6 @@ config MIPS_EV64120
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||||
<http://www.marvell.com/>. Say Y here if you wish to build a
|
||||
kernel for this platform.
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||||
|
||||
config MIPS_IVR
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||||
bool "Globespan IVR board"
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||||
select DMA_NONCOHERENT
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select HW_HAS_PCI
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select ITE_BOARD_GEN
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||||
select SYS_HAS_CPU_NEVADA
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||||
select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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||||
help
|
||||
This is an evaluation board built by Globespan to showcase thir
|
||||
iVR (Internet Video Recorder) design. It utilizes a QED RM5231
|
||||
R5000 MIPS core. More information can be found out their website
|
||||
located at <http://www.globespan.net/>. Say Y here if you wish to
|
||||
build a kernel for this platform.
|
||||
|
||||
config MIPS_ITE8172
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||||
bool "ITE 8172G board"
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||||
select DMA_NONCOHERENT
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select HW_HAS_PCI
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||||
select ITE_BOARD_GEN
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||||
select SYS_HAS_CPU_R5432
|
||||
select SYS_HAS_CPU_NEVADA
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
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||||
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
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||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
help
|
||||
Ths is an evaluation board made by ITE <http://www.ite.com.tw/>
|
||||
with ATX form factor that utilizes a MIPS R5000 to work with its
|
||||
ITE8172G companion internet appliance chip. The MIPS core can be
|
||||
either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
|
||||
a kernel for this platform.
|
||||
|
||||
config MACH_JAZZ
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||||
bool "Jazz family of machines"
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||||
select ARC
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||||
@@ -804,7 +771,6 @@ endchoice
|
||||
source "arch/mips/ddb5xxx/Kconfig"
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||||
source "arch/mips/gt64120/ev64120/Kconfig"
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||||
source "arch/mips/jazz/Kconfig"
|
||||
source "arch/mips/ite-boards/Kconfig"
|
||||
source "arch/mips/lasat/Kconfig"
|
||||
source "arch/mips/momentum/Kconfig"
|
||||
source "arch/mips/pmc-sierra/Kconfig"
|
||||
@@ -837,6 +803,10 @@ config GENERIC_CALIBRATE_DELAY
|
||||
bool
|
||||
default y
|
||||
|
||||
config GENERIC_TIME
|
||||
bool
|
||||
default y
|
||||
|
||||
config SCHED_NO_NO_OMIT_FRAME_POINTER
|
||||
bool
|
||||
default y
|
||||
@@ -964,9 +934,6 @@ config MIPS_RM9122
|
||||
config PCI_MARVELL
|
||||
bool
|
||||
|
||||
config ITE_BOARD_GEN
|
||||
bool
|
||||
|
||||
config SOC_AU1000
|
||||
bool
|
||||
select SOC_AU1X00
|
||||
@@ -1050,16 +1017,6 @@ config AU1X00_USB_DEVICE
|
||||
depends on MIPS_PB1500 || MIPS_PB1100 || MIPS_PB1000
|
||||
default n
|
||||
|
||||
config IT8172_CIR
|
||||
bool
|
||||
depends on MIPS_ITE8172 || MIPS_IVR
|
||||
default y
|
||||
|
||||
config IT8712
|
||||
bool
|
||||
depends on MIPS_ITE8172
|
||||
default y
|
||||
|
||||
config BOOT_ELF32
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||||
bool
|
||||
|
||||
|
||||
@@ -286,19 +286,6 @@ core-$(CONFIG_WR_PPMC) += arch/mips/gt64120/wrppmc/
|
||||
cflags-$(CONFIG_WR_PPMC) += -Iinclude/asm-mips/mach-wrppmc
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||||
load-$(CONFIG_WR_PPMC) += 0xffffffff80100000
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||||
|
||||
#
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||||
# Globespan IVR eval board with QED 5231 CPU
|
||||
#
|
||||
core-$(CONFIG_ITE_BOARD_GEN) += arch/mips/ite-boards/generic/
|
||||
core-$(CONFIG_MIPS_IVR) += arch/mips/ite-boards/ivr/
|
||||
load-$(CONFIG_MIPS_IVR) += 0xffffffff80100000
|
||||
|
||||
#
|
||||
# ITE 8172 eval board with QED 5231 CPU
|
||||
#
|
||||
core-$(CONFIG_MIPS_ITE8172) += arch/mips/ite-boards/qed-4n-s01b/
|
||||
load-$(CONFIG_MIPS_ITE8172) += 0xffffffff80100000
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||||
|
||||
#
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||||
# For all MIPS, Inc. eval boards
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||||
#
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||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#
|
||||
# Automatically generated make config: don't edit
|
||||
# Linux kernel version: 2.6.18-rc1
|
||||
# Thu Jul 6 10:04:01 2006
|
||||
# Linux kernel version: 2.6.18
|
||||
# Tue Oct 3 11:57:53 2006
|
||||
#
|
||||
CONFIG_MIPS=y
|
||||
|
||||
@@ -167,27 +167,28 @@ CONFIG_SWAP=y
|
||||
CONFIG_SYSVIPC=y
|
||||
# CONFIG_POSIX_MQUEUE is not set
|
||||
# CONFIG_BSD_PROCESS_ACCT is not set
|
||||
CONFIG_SYSCTL=y
|
||||
# CONFIG_TASKSTATS is not set
|
||||
# CONFIG_AUDIT is not set
|
||||
# CONFIG_IKCONFIG is not set
|
||||
CONFIG_RELAY=y
|
||||
# CONFIG_RELAY is not set
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_SYSCTL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SYSCTL_SYSCALL is not set
|
||||
CONFIG_KALLSYMS=y
|
||||
# CONFIG_KALLSYMS_ALL is not set
|
||||
# CONFIG_KALLSYMS_EXTRA_PASS is not set
|
||||
# CONFIG_HOTPLUG is not set
|
||||
CONFIG_PRINTK=y
|
||||
CONFIG_BUG=y
|
||||
CONFIG_ELF_CORE=y
|
||||
CONFIG_BASE_FULL=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
CONFIG_FUTEX=y
|
||||
CONFIG_EPOLL=y
|
||||
CONFIG_SHMEM=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_RT_MUTEXES=y
|
||||
# CONFIG_TINY_SHMEM is not set
|
||||
CONFIG_BASE_SMALL=0
|
||||
# CONFIG_SLOB is not set
|
||||
@@ -205,6 +206,7 @@ CONFIG_KMOD=y
|
||||
#
|
||||
# Block layer
|
||||
#
|
||||
CONFIG_BLOCK=y
|
||||
# CONFIG_LBD is not set
|
||||
# CONFIG_BLK_DEV_IO_TRACE is not set
|
||||
# CONFIG_LSF is not set
|
||||
@@ -231,7 +233,6 @@ CONFIG_MMU=y
|
||||
#
|
||||
# PCCARD (PCMCIA/CardBus) support
|
||||
#
|
||||
# CONFIG_PCCARD is not set
|
||||
|
||||
#
|
||||
# PCI Hotplug Support
|
||||
@@ -258,9 +259,10 @@ CONFIG_PACKET_MMAP=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM=y
|
||||
# CONFIG_XFRM_USER is not set
|
||||
# CONFIG_NET_KEY is not set
|
||||
# CONFIG_XFRM_SUB_POLICY is not set
|
||||
CONFIG_NET_KEY=m
|
||||
CONFIG_INET=y
|
||||
# CONFIG_IP_MULTICAST is not set
|
||||
CONFIG_IP_MULTICAST=y
|
||||
# CONFIG_IP_ADVANCED_ROUTER is not set
|
||||
CONFIG_IP_FIB_HASH=y
|
||||
CONFIG_IP_PNP=y
|
||||
@@ -269,22 +271,37 @@ CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_IP_PNP_RARP is not set
|
||||
# CONFIG_NET_IPIP is not set
|
||||
# CONFIG_NET_IPGRE is not set
|
||||
# CONFIG_IP_MROUTE is not set
|
||||
# CONFIG_ARPD is not set
|
||||
# CONFIG_SYN_COOKIES is not set
|
||||
# CONFIG_INET_AH is not set
|
||||
# CONFIG_INET_ESP is not set
|
||||
# CONFIG_INET_IPCOMP is not set
|
||||
# CONFIG_INET_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET_TUNNEL is not set
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
CONFIG_INET_XFRM_TUNNEL=m
|
||||
CONFIG_INET_TUNNEL=m
|
||||
CONFIG_INET_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET_DIAG=y
|
||||
CONFIG_INET_TCP_DIAG=y
|
||||
# CONFIG_TCP_CONG_ADVANCED is not set
|
||||
CONFIG_TCP_CONG_BIC=y
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_INET6_XFRM_TUNNEL is not set
|
||||
# CONFIG_INET6_TUNNEL is not set
|
||||
CONFIG_TCP_CONG_CUBIC=y
|
||||
CONFIG_DEFAULT_TCP_CONG="cubic"
|
||||
CONFIG_IPV6=m
|
||||
CONFIG_IPV6_PRIVACY=y
|
||||
CONFIG_IPV6_ROUTER_PREF=y
|
||||
CONFIG_IPV6_ROUTE_INFO=y
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_MIP6=y
|
||||
CONFIG_INET6_XFRM_TUNNEL=m
|
||||
CONFIG_INET6_TUNNEL=m
|
||||
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
|
||||
CONFIG_INET6_XFRM_MODE_TUNNEL=m
|
||||
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
|
||||
# CONFIG_IPV6_TUNNEL is not set
|
||||
CONFIG_IPV6_SUBTREES=y
|
||||
CONFIG_IPV6_MULTIPLE_TABLES=y
|
||||
CONFIG_NETWORK_SECMARK=y
|
||||
# CONFIG_NETFILTER is not set
|
||||
|
||||
@@ -304,14 +321,13 @@ CONFIG_NETWORK_SECMARK=y
|
||||
# CONFIG_TIPC is not set
|
||||
# CONFIG_ATM is not set
|
||||
# CONFIG_BRIDGE is not set
|
||||
# CONFIG_VLAN_8021Q is not set
|
||||
CONFIG_VLAN_8021Q=m
|
||||
# CONFIG_DECNET is not set
|
||||
# CONFIG_LLC2 is not set
|
||||
# CONFIG_IPX is not set
|
||||
# CONFIG_ATALK is not set
|
||||
# CONFIG_X25 is not set
|
||||
# CONFIG_LAPB is not set
|
||||
# CONFIG_NET_DIVERT is not set
|
||||
# CONFIG_ECONET is not set
|
||||
# CONFIG_WAN_ROUTER is not set
|
||||
|
||||
@@ -327,13 +343,8 @@ CONFIG_NETWORK_SECMARK=y
|
||||
# CONFIG_HAMRADIO is not set
|
||||
# CONFIG_IRDA is not set
|
||||
# CONFIG_BT is not set
|
||||
CONFIG_IEEE80211=m
|
||||
# CONFIG_IEEE80211_DEBUG is not set
|
||||
CONFIG_IEEE80211_CRYPT_WEP=m
|
||||
CONFIG_IEEE80211_CRYPT_CCMP=m
|
||||
CONFIG_IEEE80211_SOFTMAC=m
|
||||
# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
|
||||
CONFIG_WIRELESS_EXT=y
|
||||
# CONFIG_IEEE80211 is not set
|
||||
CONFIG_FIB_RULES=y
|
||||
|
||||
#
|
||||
# Device Drivers
|
||||
@@ -344,8 +355,6 @@ CONFIG_WIRELESS_EXT=y
|
||||
#
|
||||
CONFIG_STANDALONE=y
|
||||
CONFIG_PREVENT_FIRMWARE_BUILD=y
|
||||
# CONFIG_FW_LOADER is not set
|
||||
# CONFIG_DEBUG_DRIVER is not set
|
||||
# CONFIG_SYS_HYPERVISOR is not set
|
||||
|
||||
#
|
||||
@@ -387,8 +396,9 @@ CONFIG_BLK_DEV_LOOP=m
|
||||
#
|
||||
# SCSI device support
|
||||
#
|
||||
CONFIG_RAID_ATTRS=m
|
||||
# CONFIG_RAID_ATTRS is not set
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_NETLINK is not set
|
||||
CONFIG_SCSI_PROC_FS=y
|
||||
|
||||
#
|
||||
@@ -410,12 +420,13 @@ CONFIG_SCSI_CONSTANTS=y
|
||||
# CONFIG_SCSI_LOGGING is not set
|
||||
|
||||
#
|
||||
# SCSI Transport Attributes
|
||||
# SCSI Transports
|
||||
#
|
||||
CONFIG_SCSI_SPI_ATTRS=m
|
||||
# CONFIG_SCSI_FC_ATTRS is not set
|
||||
CONFIG_SCSI_ISCSI_ATTRS=m
|
||||
CONFIG_SCSI_SAS_ATTRS=m
|
||||
# CONFIG_SCSI_SAS_LIBSAS is not set
|
||||
|
||||
#
|
||||
# SCSI low-level drivers
|
||||
@@ -423,9 +434,13 @@ CONFIG_SCSI_SAS_ATTRS=m
|
||||
CONFIG_ISCSI_TCP=m
|
||||
CONFIG_SCSI_DECNCR=y
|
||||
# CONFIG_SCSI_DECSII is not set
|
||||
# CONFIG_SCSI_SATA is not set
|
||||
# CONFIG_SCSI_DEBUG is not set
|
||||
|
||||
#
|
||||
# Serial ATA (prod) and Parallel ATA (experimental) drivers
|
||||
#
|
||||
# CONFIG_ATA is not set
|
||||
|
||||
#
|
||||
# Multi-device support (RAID and LVM)
|
||||
#
|
||||
@@ -456,18 +471,7 @@ CONFIG_NETDEVICES=y
|
||||
#
|
||||
# PHY device support
|
||||
#
|
||||
CONFIG_PHYLIB=m
|
||||
|
||||
#
|
||||
# MII PHY device drivers
|
||||
#
|
||||
CONFIG_MARVELL_PHY=m
|
||||
CONFIG_DAVICOM_PHY=m
|
||||
CONFIG_QSEMI_PHY=m
|
||||
CONFIG_LXT_PHY=m
|
||||
CONFIG_CICADA_PHY=m
|
||||
CONFIG_VITESSE_PHY=m
|
||||
CONFIG_SMSC_PHY=m
|
||||
# CONFIG_PHYLIB is not set
|
||||
|
||||
#
|
||||
# Ethernet (10 or 100Mbit)
|
||||
@@ -712,7 +716,12 @@ CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT2_FS_SECURITY=y
|
||||
# CONFIG_EXT2_FS_XIP is not set
|
||||
# CONFIG_EXT3_FS is not set
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_XATTR=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS_SECURITY=y
|
||||
CONFIG_JBD=y
|
||||
# CONFIG_JBD_DEBUG is not set
|
||||
CONFIG_FS_MBCACHE=y
|
||||
# CONFIG_REISERFS_FS is not set
|
||||
# CONFIG_JFS_FS is not set
|
||||
@@ -747,11 +756,13 @@ CONFIG_FUSE_FS=m
|
||||
#
|
||||
CONFIG_PROC_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_PROC_SYSCTL=y
|
||||
CONFIG_SYSFS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_HUGETLB_PAGE is not set
|
||||
CONFIG_RAMFS=y
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
|
||||
#
|
||||
# Miscellaneous filesystems
|
||||
@@ -769,7 +780,7 @@ CONFIG_RAMFS=y
|
||||
# CONFIG_QNX4FS_FS is not set
|
||||
# CONFIG_SYSV_FS is not set
|
||||
CONFIG_UFS_FS=y
|
||||
# CONFIG_UFS_FS_WRITE is not set
|
||||
CONFIG_UFS_FS_WRITE=y
|
||||
# CONFIG_UFS_DEBUG is not set
|
||||
|
||||
#
|
||||
@@ -777,24 +788,25 @@ CONFIG_UFS_FS=y
|
||||
#
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
# CONFIG_NFS_V3_ACL is not set
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
# CONFIG_NFS_V4 is not set
|
||||
# CONFIG_NFS_DIRECTIO is not set
|
||||
# CONFIG_NFSD is not set
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_LOCKD=y
|
||||
CONFIG_LOCKD_V4=y
|
||||
CONFIG_NFS_ACL_SUPPORT=y
|
||||
CONFIG_NFS_COMMON=y
|
||||
CONFIG_SUNRPC=y
|
||||
# CONFIG_RPCSEC_GSS_KRB5 is not set
|
||||
# CONFIG_RPCSEC_GSS_SPKM3 is not set
|
||||
# CONFIG_SMB_FS is not set
|
||||
# CONFIG_CIFS is not set
|
||||
# CONFIG_CIFS_DEBUG2 is not set
|
||||
# CONFIG_NCP_FS is not set
|
||||
# CONFIG_CODA_FS is not set
|
||||
# CONFIG_AFS_FS is not set
|
||||
# CONFIG_9P_FS is not set
|
||||
CONFIG_GENERIC_ACL=y
|
||||
|
||||
#
|
||||
# Partition Types
|
||||
@@ -832,44 +844,29 @@ CONFIG_ULTRIX_PARTITION=y
|
||||
#
|
||||
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
|
||||
# CONFIG_PRINTK_TIME is not set
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_UNUSED_SYMBOLS is not set
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
# CONFIG_DEBUG_KERNEL is not set
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_DETECT_SOFTLOCKUP=y
|
||||
# CONFIG_SCHEDSTATS is not set
|
||||
# CONFIG_DEBUG_SLAB is not set
|
||||
# CONFIG_DEBUG_RT_MUTEXES is not set
|
||||
# CONFIG_RT_MUTEX_TESTER is not set
|
||||
# CONFIG_DEBUG_SPINLOCK is not set
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
# CONFIG_DEBUG_RWSEMS is not set
|
||||
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
|
||||
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
|
||||
# CONFIG_DEBUG_KOBJECT is not set
|
||||
# CONFIG_DEBUG_INFO is not set
|
||||
# CONFIG_DEBUG_FS is not set
|
||||
# CONFIG_DEBUG_VM is not set
|
||||
CONFIG_FORCED_INLINING=y
|
||||
# CONFIG_RCU_TORTURE_TEST is not set
|
||||
CONFIG_CROSSCOMPILE=y
|
||||
CONFIG_CMDLINE=""
|
||||
# CONFIG_DEBUG_STACK_USAGE is not set
|
||||
# CONFIG_KGDB is not set
|
||||
# CONFIG_RUNTIME_DEBUG is not set
|
||||
# CONFIG_MIPS_UNCACHED is not set
|
||||
|
||||
#
|
||||
# Security options
|
||||
#
|
||||
CONFIG_KEYS=y
|
||||
CONFIG_KEYS_DEBUG_PROC_KEYS=y
|
||||
# CONFIG_KEYS is not set
|
||||
# CONFIG_SECURITY is not set
|
||||
|
||||
#
|
||||
# Cryptographic options
|
||||
#
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_ALGAPI=y
|
||||
CONFIG_CRYPTO_BLKCIPHER=m
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_MANAGER=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_MD4=m
|
||||
@@ -879,9 +876,12 @@ CONFIG_CRYPTO_SHA256=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_ECB=m
|
||||
CONFIG_CRYPTO_CBC=m
|
||||
CONFIG_CRYPTO_DES=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
CONFIG_CRYPTO_TWOFISH_COMMON=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_AES=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
@@ -903,7 +903,7 @@ CONFIG_CRYPTO_CRC32C=m
|
||||
# Library routines
|
||||
#
|
||||
# CONFIG_CRC_CCITT is not set
|
||||
CONFIG_CRC16=m
|
||||
# CONFIG_CRC16 is not set
|
||||
CONFIG_CRC32=y
|
||||
CONFIG_LIBCRC32C=m
|
||||
CONFIG_ZLIB_INFLATE=m
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,12 +0,0 @@
|
||||
#
|
||||
# Makefile for the DECstation family specific parts of the kernel
|
||||
#
|
||||
|
||||
netboot: all
|
||||
$(LD) -N -G 0 -T ld.ecoff ../../boot/zImage \
|
||||
dec_boot.o ramdisk.img -o nbImage
|
||||
|
||||
obj-y := decstation.o
|
||||
|
||||
clean:
|
||||
rm -f nbImage
|
||||
@@ -1,84 +0,0 @@
|
||||
/*
|
||||
* arch/mips/dec/decstation.c
|
||||
*/
|
||||
#include <asm/sections.h>
|
||||
|
||||
#define RELOC
|
||||
#define INITRD
|
||||
#define DEBUG_BOOT
|
||||
|
||||
/*
|
||||
* Magic number indicating REX PROM available on DECSTATION.
|
||||
*/
|
||||
#define REX_PROM_MAGIC 0x30464354
|
||||
|
||||
#define REX_PROM_CLEARCACHE 0x7c/4
|
||||
#define REX_PROM_PRINTF 0x30/4
|
||||
|
||||
#define VEC_RESET 0xBFC00000 /* Prom base address */
|
||||
#define PMAX_PROM_ENTRY(x) (VEC_RESET+((x)*8)) /* Prom jump table */
|
||||
#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17)
|
||||
|
||||
#define PARAM (k_start + 0x2000)
|
||||
|
||||
#define LOADER_TYPE (*(unsigned char *) (PARAM+0x210))
|
||||
#define INITRD_START (*(unsigned long *) (PARAM+0x218))
|
||||
#define INITRD_SIZE (*(unsigned long *) (PARAM+0x21c))
|
||||
|
||||
extern int _ftext; /* begin and end of kernel image */
|
||||
extern void kernel_entry(int, char **, unsigned long, int *);
|
||||
|
||||
void * memcpy(void * dest, const void *src, unsigned int count)
|
||||
{
|
||||
unsigned long *tmp = (unsigned long *) dest, *s = (unsigned long *) src;
|
||||
|
||||
count >>= 2;
|
||||
while (count--)
|
||||
*tmp++ = *s++;
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
void dec_entry(int argc, char **argv,
|
||||
unsigned long magic, int *prom_vec)
|
||||
{
|
||||
void (*rex_clear_cache)(void);
|
||||
int (*prom_printf)(char *, ...);
|
||||
unsigned long k_start, len;
|
||||
|
||||
/*
|
||||
* The DS5100 leaves cpu with BEV enabled, clear it.
|
||||
*/
|
||||
asm( "lui\t$8,0x3000\n\t"
|
||||
"mtc0\t$8,$12\n\t"
|
||||
".section\t.sdata\n\t"
|
||||
".section\t.sbss\n\t"
|
||||
".section\t.text"
|
||||
: : : "$8");
|
||||
|
||||
#ifdef DEBUG_BOOT
|
||||
if (magic == REX_PROM_MAGIC) {
|
||||
prom_printf = (int (*)(char *, ...)) *(prom_vec + REX_PROM_PRINTF);
|
||||
} else {
|
||||
prom_printf = (int (*)(char *, ...)) PMAX_PROM_PRINTF;
|
||||
}
|
||||
prom_printf("Launching kernel...\n");
|
||||
#endif
|
||||
|
||||
k_start = (unsigned long) (&kernel_entry) & 0xffff0000;
|
||||
|
||||
#ifdef RELOC
|
||||
/*
|
||||
* Now copy kernel image to its destination.
|
||||
*/
|
||||
len = ((unsigned long) (&_end) - k_start);
|
||||
memcpy((void *)k_start, &_ftext, len);
|
||||
#endif
|
||||
|
||||
if (magic == REX_PROM_MAGIC) {
|
||||
rex_clear_cache = (void (*)(void)) * (prom_vec + REX_PROM_CLEARCACHE);
|
||||
rex_clear_cache();
|
||||
}
|
||||
|
||||
kernel_entry(argc, argv, magic, prom_vec);
|
||||
}
|
||||
@@ -1,43 +0,0 @@
|
||||
OUTPUT_FORMAT("ecoff-littlemips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(dec_entry)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80200000;
|
||||
|
||||
.text :
|
||||
{
|
||||
_ftext = .;
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
}
|
||||
.rdata :
|
||||
{
|
||||
*(.rodata .rodata.* .rdata)
|
||||
}
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(0x1000);
|
||||
ramdisk.img (.data)
|
||||
*(.data)
|
||||
}
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata)
|
||||
}
|
||||
_gp = .;
|
||||
.sbss :
|
||||
{
|
||||
*(.sbss)
|
||||
*(.scommon)
|
||||
}
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
/DISCARD/ : {
|
||||
*(.reginfo .mdebug .note)
|
||||
}
|
||||
}
|
||||
@@ -184,8 +184,6 @@ void __init dec_time_init(void)
|
||||
CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - __ffs(HZ)), RTC_REG_A);
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(do_settimeofday);
|
||||
|
||||
void __init plat_timer_setup(struct irqaction *irq)
|
||||
{
|
||||
setup_irq(dec_interrupt[DEC_IRQ_RTC], irq);
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
config IT8172_REVC
|
||||
bool "Support for older IT8172 (Rev C)"
|
||||
depends on MIPS_ITE8172
|
||||
help
|
||||
Say Y here to support the older, Revision C version of the Integrated
|
||||
Technology Express, Inc. ITE8172 SBC. Vendor page at
|
||||
<http://www.ite.com.tw/ia/brief_it8172bsp.htm>; picture of the
|
||||
board at <http://www.mvista.com/partners/semiconductor/ite.html>.
|
||||
@@ -1,15 +0,0 @@
|
||||
#
|
||||
# Copyright 2000 MontaVista Software Inc.
|
||||
# Author: MontaVista Software, Inc.
|
||||
# ppopov@mvista.com or source@mvista.com
|
||||
#
|
||||
# Makefile for the ITE 8172 (qed-4n-s01b) board, generic files.
|
||||
#
|
||||
|
||||
obj-y += it8172_setup.o irq.o pmon_prom.o \
|
||||
time.o lpc.o puts.o reset.o
|
||||
|
||||
obj-$(CONFIG_IT8172_CIR)+= it8172_cir.o
|
||||
obj-$(CONFIG_KGDB) += dbg_io.o
|
||||
|
||||
EXTRA_AFLAGS := $(CFLAGS)
|
||||
@@ -1,124 +0,0 @@
|
||||
|
||||
|
||||
#ifdef CONFIG_KGDB
|
||||
|
||||
/* --- CONFIG --- */
|
||||
|
||||
/* we need uint32 uint8 */
|
||||
/* #include "types.h" */
|
||||
typedef unsigned char uint8;
|
||||
typedef unsigned int uint32;
|
||||
|
||||
/* --- END OF CONFIG --- */
|
||||
|
||||
#define UART16550_BAUD_2400 2400
|
||||
#define UART16550_BAUD_4800 4800
|
||||
#define UART16550_BAUD_9600 9600
|
||||
#define UART16550_BAUD_19200 19200
|
||||
#define UART16550_BAUD_38400 38400
|
||||
#define UART16550_BAUD_57600 57600
|
||||
#define UART16550_BAUD_115200 115200
|
||||
|
||||
#define UART16550_PARITY_NONE 0
|
||||
#define UART16550_PARITY_ODD 0x08
|
||||
#define UART16550_PARITY_EVEN 0x18
|
||||
#define UART16550_PARITY_MARK 0x28
|
||||
#define UART16550_PARITY_SPACE 0x38
|
||||
|
||||
#define UART16550_DATA_5BIT 0x0
|
||||
#define UART16550_DATA_6BIT 0x1
|
||||
#define UART16550_DATA_7BIT 0x2
|
||||
#define UART16550_DATA_8BIT 0x3
|
||||
|
||||
#define UART16550_STOP_1BIT 0x0
|
||||
#define UART16550_STOP_2BIT 0x4
|
||||
|
||||
/* ----------------------------------------------------- */
|
||||
|
||||
/* === CONFIG === */
|
||||
|
||||
/* [stevel] we use the IT8712 serial port for kgdb */
|
||||
#define DEBUG_BASE 0xB40003F8 /* 8712 serial port 1 base address */
|
||||
#define MAX_BAUD 115200
|
||||
|
||||
/* === END OF CONFIG === */
|
||||
|
||||
/* register offset */
|
||||
#define OFS_RCV_BUFFER 0
|
||||
#define OFS_TRANS_HOLD 0
|
||||
#define OFS_SEND_BUFFER 0
|
||||
#define OFS_INTR_ENABLE 1
|
||||
#define OFS_INTR_ID 2
|
||||
#define OFS_DATA_FORMAT 3
|
||||
#define OFS_LINE_CONTROL 3
|
||||
#define OFS_MODEM_CONTROL 4
|
||||
#define OFS_RS232_OUTPUT 4
|
||||
#define OFS_LINE_STATUS 5
|
||||
#define OFS_MODEM_STATUS 6
|
||||
#define OFS_RS232_INPUT 6
|
||||
#define OFS_SCRATCH_PAD 7
|
||||
|
||||
#define OFS_DIVISOR_LSB 0
|
||||
#define OFS_DIVISOR_MSB 1
|
||||
|
||||
|
||||
/* memory-mapped read/write of the port */
|
||||
#define UART16550_READ(y) (*((volatile uint8*)(DEBUG_BASE + y)))
|
||||
#define UART16550_WRITE(y,z) ((*((volatile uint8*)(DEBUG_BASE + y))) = z)
|
||||
|
||||
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
|
||||
{
|
||||
/* disable interrupts */
|
||||
UART16550_WRITE(OFS_INTR_ENABLE, 0);
|
||||
|
||||
/* set up baud rate */
|
||||
{
|
||||
uint32 divisor;
|
||||
|
||||
/* set DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
|
||||
|
||||
/* set divisor */
|
||||
divisor = MAX_BAUD / baud;
|
||||
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
|
||||
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
|
||||
|
||||
/* clear DIAB bit */
|
||||
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
|
||||
}
|
||||
|
||||
/* set data format */
|
||||
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
|
||||
}
|
||||
|
||||
static int remoteDebugInitialized = 0;
|
||||
|
||||
uint8 getDebugChar(void)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_115200,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
|
||||
return UART16550_READ(OFS_RCV_BUFFER);
|
||||
}
|
||||
|
||||
|
||||
int putDebugChar(uint8 byte)
|
||||
{
|
||||
if (!remoteDebugInitialized) {
|
||||
remoteDebugInitialized = 1;
|
||||
debugInit(UART16550_BAUD_115200,
|
||||
UART16550_DATA_8BIT,
|
||||
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
|
||||
}
|
||||
|
||||
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
|
||||
UART16550_WRITE(OFS_SEND_BUFFER, byte);
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,308 +0,0 @@
|
||||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* ITE 8172G interrupt/setup routines.
|
||||
*
|
||||
* Copyright 2000,2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* Part of this file was derived from Carsten Langgaard's
|
||||
* arch/mips/mips-boards/atlas/atlas_int.c.
|
||||
*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/errno.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/kernel_stat.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/signal.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/timex.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_int.h>
|
||||
#include <asm/it8172/it8172_dbg.h>
|
||||
|
||||
/* revisit */
|
||||
#define EXT_IRQ0_TO_IP 2 /* IP 2 */
|
||||
#define EXT_IRQ5_TO_IP 7 /* IP 7 */
|
||||
|
||||
#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
|
||||
|
||||
extern void set_debug_traps(void);
|
||||
extern void mips_timer_interrupt(int irq, struct pt_regs *regs);
|
||||
|
||||
struct it8172_intc_regs volatile *it8172_hw0_icregs =
|
||||
(struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE));
|
||||
|
||||
static void disable_it8172_irq(unsigned int irq_nr)
|
||||
{
|
||||
if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
|
||||
/* LPC interrupt */
|
||||
it8172_hw0_icregs->lpc_mask |=
|
||||
(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
|
||||
} else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
|
||||
/* Local Bus interrupt */
|
||||
it8172_hw0_icregs->lb_mask |=
|
||||
(1 << (irq_nr - IT8172_LB_IRQ_BASE));
|
||||
} else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
|
||||
/* PCI and other interrupts */
|
||||
it8172_hw0_icregs->pci_mask |=
|
||||
(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
|
||||
} else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
|
||||
/* NMI interrupts */
|
||||
it8172_hw0_icregs->nmi_mask |=
|
||||
(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
|
||||
} else {
|
||||
panic("disable_it8172_irq: bad irq %d", irq_nr);
|
||||
}
|
||||
}
|
||||
|
||||
static void enable_it8172_irq(unsigned int irq_nr)
|
||||
{
|
||||
if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) {
|
||||
/* LPC interrupt */
|
||||
it8172_hw0_icregs->lpc_mask &=
|
||||
~(1 << (irq_nr - IT8172_LPC_IRQ_BASE));
|
||||
}
|
||||
else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) {
|
||||
/* Local Bus interrupt */
|
||||
it8172_hw0_icregs->lb_mask &=
|
||||
~(1 << (irq_nr - IT8172_LB_IRQ_BASE));
|
||||
}
|
||||
else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) {
|
||||
/* PCI and other interrupts */
|
||||
it8172_hw0_icregs->pci_mask &=
|
||||
~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE));
|
||||
}
|
||||
else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) {
|
||||
/* NMI interrupts */
|
||||
it8172_hw0_icregs->nmi_mask &=
|
||||
~(1 << (irq_nr - IT8172_NMI_IRQ_BASE));
|
||||
}
|
||||
else {
|
||||
panic("enable_it8172_irq: bad irq %d", irq_nr);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int startup_ite_irq(unsigned int irq)
|
||||
{
|
||||
enable_it8172_irq(irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define shutdown_ite_irq disable_it8172_irq
|
||||
#define mask_and_ack_ite_irq disable_it8172_irq
|
||||
|
||||
static void end_ite_irq(unsigned int irq)
|
||||
{
|
||||
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
||||
enable_it8172_irq(irq);
|
||||
}
|
||||
|
||||
static struct irq_chip it8172_irq_type = {
|
||||
.typename = "ITE8172",
|
||||
.startup = startup_ite_irq,
|
||||
.shutdown = shutdown_ite_irq,
|
||||
.enable = enable_it8172_irq,
|
||||
.disable = disable_it8172_irq,
|
||||
.ack = mask_and_ack_ite_irq,
|
||||
.end = end_ite_irq,
|
||||
};
|
||||
|
||||
|
||||
static void enable_none(unsigned int irq) { }
|
||||
static unsigned int startup_none(unsigned int irq) { return 0; }
|
||||
static void disable_none(unsigned int irq) { }
|
||||
static void ack_none(unsigned int irq) { }
|
||||
|
||||
/* startup is the same as "enable", shutdown is same as "disable" */
|
||||
#define shutdown_none disable_none
|
||||
#define end_none enable_none
|
||||
|
||||
static struct irq_chip cp0_irq_type = {
|
||||
.typename = "CP0 Count",
|
||||
.startup = startup_none,
|
||||
.shutdown = shutdown_none,
|
||||
.enable = enable_none,
|
||||
.disable = disable_none,
|
||||
.ack = ack_none,
|
||||
.end = end_none
|
||||
};
|
||||
|
||||
void enable_cpu_timer(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
set_c0_status(0x100 << EXT_IRQ5_TO_IP);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long flags;
|
||||
|
||||
/* mask all interrupts */
|
||||
it8172_hw0_icregs->lb_mask = 0xffff;
|
||||
it8172_hw0_icregs->lpc_mask = 0xffff;
|
||||
it8172_hw0_icregs->pci_mask = 0xffff;
|
||||
it8172_hw0_icregs->nmi_mask = 0xffff;
|
||||
|
||||
/* make all interrupts level triggered */
|
||||
it8172_hw0_icregs->lb_trigger = 0;
|
||||
it8172_hw0_icregs->lpc_trigger = 0;
|
||||
it8172_hw0_icregs->pci_trigger = 0;
|
||||
it8172_hw0_icregs->nmi_trigger = 0;
|
||||
|
||||
/* active level setting */
|
||||
/* uart, keyboard, and mouse are active high */
|
||||
it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000);
|
||||
it8172_hw0_icregs->lb_level |= 0x20;
|
||||
|
||||
/* keyboard and mouse are edge triggered */
|
||||
it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000);
|
||||
|
||||
|
||||
#if 0
|
||||
// Enable this piece of code to make internal USB interrupt
|
||||
// edge triggered.
|
||||
it8172_hw0_icregs->pci_trigger |=
|
||||
(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
|
||||
it8172_hw0_icregs->pci_level &=
|
||||
~(1 << (IT8172_USB_IRQ - IT8172_PCI_DEV_IRQ_BASE));
|
||||
#endif
|
||||
|
||||
for (i = 0; i <= IT8172_LAST_IRQ; i++) {
|
||||
irq_desc[i].chip = &it8172_irq_type;
|
||||
spin_lock_init(&irq_desc[i].lock);
|
||||
}
|
||||
irq_desc[MIPS_CPU_TIMER_IRQ].chip = &cp0_irq_type;
|
||||
set_c0_status(ALLINTS_NOTIMER);
|
||||
}
|
||||
|
||||
void mips_spurious_interrupt(struct pt_regs *regs)
|
||||
{
|
||||
#if 1
|
||||
return;
|
||||
#else
|
||||
unsigned long status, cause;
|
||||
|
||||
printk("got spurious interrupt\n");
|
||||
status = read_c0_status();
|
||||
cause = read_c0_cause();
|
||||
printk("status %x cause %x\n", status, cause);
|
||||
printk("epc %x badvaddr %x \n", regs->cp0_epc, regs->cp0_badvaddr);
|
||||
#endif
|
||||
}
|
||||
|
||||
void it8172_hw0_irqdispatch(struct pt_regs *regs)
|
||||
{
|
||||
int irq;
|
||||
unsigned short intstatus = 0, status = 0;
|
||||
|
||||
intstatus = it8172_hw0_icregs->intstatus;
|
||||
if (intstatus & 0x8) {
|
||||
panic("Got NMI interrupt");
|
||||
} else if (intstatus & 0x4) {
|
||||
/* PCI interrupt */
|
||||
irq = 0;
|
||||
status |= it8172_hw0_icregs->pci_req;
|
||||
while (!(status & 0x1)) {
|
||||
irq++;
|
||||
status >>= 1;
|
||||
}
|
||||
irq += IT8172_PCI_DEV_IRQ_BASE;
|
||||
} else if (intstatus & 0x1) {
|
||||
/* Local Bus interrupt */
|
||||
irq = 0;
|
||||
status |= it8172_hw0_icregs->lb_req;
|
||||
while (!(status & 0x1)) {
|
||||
irq++;
|
||||
status >>= 1;
|
||||
}
|
||||
irq += IT8172_LB_IRQ_BASE;
|
||||
} else if (intstatus & 0x2) {
|
||||
/* LPC interrupt */
|
||||
/* Since some lpc interrupts are edge triggered,
|
||||
* we could lose an interrupt this way because
|
||||
* we acknowledge all ints at onces. Revisit.
|
||||
*/
|
||||
status |= it8172_hw0_icregs->lpc_req;
|
||||
it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */
|
||||
irq = 0;
|
||||
while (!(status & 0x1)) {
|
||||
irq++;
|
||||
status >>= 1;
|
||||
}
|
||||
irq += IT8172_LPC_IRQ_BASE;
|
||||
} else
|
||||
return;
|
||||
|
||||
do_IRQ(irq, regs);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
|
||||
{
|
||||
unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
|
||||
|
||||
if (!pending)
|
||||
mips_spurious_interrupt(regs);
|
||||
else if (pending & CAUSEF_IP7)
|
||||
ll_timer_interrupt(127, regs);
|
||||
else if (pending & CAUSEF_IP2)
|
||||
it8172_hw0_irqdispatch(regs);
|
||||
}
|
||||
|
||||
void show_pending_irqs(void)
|
||||
{
|
||||
fputs("intstatus: ");
|
||||
put32(it8172_hw0_icregs->intstatus);
|
||||
puts("");
|
||||
|
||||
fputs("pci_req: ");
|
||||
put32(it8172_hw0_icregs->pci_req);
|
||||
puts("");
|
||||
|
||||
fputs("lb_req: ");
|
||||
put32(it8172_hw0_icregs->lb_req);
|
||||
puts("");
|
||||
|
||||
fputs("lpc_req: ");
|
||||
put32(it8172_hw0_icregs->lpc_req);
|
||||
puts("");
|
||||
}
|
||||
@@ -1,170 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172 Consumer IR port generic routines.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
|
||||
#ifdef CONFIG_IT8172_CIR
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8172/it8172_cir.h>
|
||||
|
||||
|
||||
volatile struct it8172_cir_regs *cir_regs[NUM_CIR_PORTS] = {
|
||||
(volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR0_BASE)),
|
||||
(volatile struct it8172_cir_regs *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_CIR1_BASE))};
|
||||
|
||||
|
||||
/*
|
||||
* Initialize Consumer IR Port.
|
||||
*/
|
||||
int cir_port_init(struct cir_port *cir)
|
||||
{
|
||||
int port = cir->port;
|
||||
unsigned char data;
|
||||
|
||||
/* set baud rate */
|
||||
cir_regs[port]->bdlr = cir->baud_rate & 0xff;
|
||||
cir_regs[port]->bdhr = (cir->baud_rate >> 8) & 0xff;
|
||||
|
||||
/* set receiver control register */
|
||||
cir_regs[port]->rcr = (CIR_SET_RDWOS(cir->rdwos) | CIR_SET_RXDCR(cir->rxdcr));
|
||||
|
||||
/* set carrier frequency register */
|
||||
cir_regs[port]->cfr = (CIR_SET_CF(cir->cfq) | CIR_SET_HS(cir->hcfs));
|
||||
|
||||
/* set fifo threshold */
|
||||
data = cir_regs[port]->mstcr & 0xf3;
|
||||
data |= CIR_SET_FIFO_TL(cir->fifo_tl);
|
||||
cir_regs[port]->mstcr = data;
|
||||
|
||||
clear_fifo(cir);
|
||||
enable_receiver(cir);
|
||||
disable_rx_demodulation(cir);
|
||||
|
||||
set_rx_active(cir);
|
||||
int_enable(cir);
|
||||
rx_int_enable(cir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void clear_fifo(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->mstcr |= CIR_FIFO_CLEAR;
|
||||
}
|
||||
|
||||
void enable_receiver(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr |= CIR_RXEN;
|
||||
}
|
||||
|
||||
void disable_receiver(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr &= ~CIR_RXEN;
|
||||
}
|
||||
|
||||
void enable_rx_demodulation(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr |= CIR_RXEND;
|
||||
}
|
||||
|
||||
void disable_rx_demodulation(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr &= ~CIR_RXEND;
|
||||
}
|
||||
|
||||
void set_rx_active(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->rcr |= CIR_RXACT;
|
||||
}
|
||||
|
||||
void int_enable(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->ier |= CIR_IEC;
|
||||
}
|
||||
|
||||
void rx_int_enable(struct cir_port *cir)
|
||||
{
|
||||
cir_regs[cir->port]->ier |= CIR_RDAIE;
|
||||
}
|
||||
|
||||
void dump_regs(struct cir_port *cir)
|
||||
{
|
||||
printk("mstcr %x ier %x iir %x cfr %x rcr %x tcr %x tfsr %x rfsr %x\n",
|
||||
cir_regs[cir->port]->mstcr,
|
||||
cir_regs[cir->port]->ier,
|
||||
cir_regs[cir->port]->iir,
|
||||
cir_regs[cir->port]->cfr,
|
||||
cir_regs[cir->port]->rcr,
|
||||
cir_regs[cir->port]->tcr,
|
||||
cir_regs[cir->port]->tfsr,
|
||||
cir_regs[cir->port]->rfsr);
|
||||
|
||||
while (cir_regs[cir->port]->iir & CIR_RDAI) {
|
||||
printk("data %x\n", cir_regs[cir->port]->dr);
|
||||
}
|
||||
}
|
||||
|
||||
void dump_reg_addr(struct cir_port *cir)
|
||||
{
|
||||
printk("dr %x mstcr %x ier %x iir %x cfr %x rcr %x tcr %x bdlr %x bdhr %x tfsr %x rfsr %x\n",
|
||||
(unsigned)&cir_regs[cir->port]->dr,
|
||||
(unsigned)&cir_regs[cir->port]->mstcr,
|
||||
(unsigned)&cir_regs[cir->port]->ier,
|
||||
(unsigned)&cir_regs[cir->port]->iir,
|
||||
(unsigned)&cir_regs[cir->port]->cfr,
|
||||
(unsigned)&cir_regs[cir->port]->rcr,
|
||||
(unsigned)&cir_regs[cir->port]->tcr,
|
||||
(unsigned)&cir_regs[cir->port]->bdlr,
|
||||
(unsigned)&cir_regs[cir->port]->bdhr,
|
||||
(unsigned)&cir_regs[cir->port]->tfsr,
|
||||
(unsigned)&cir_regs[cir->port]->rfsr);
|
||||
}
|
||||
|
||||
int cir_get_rx_count(struct cir_port *cir)
|
||||
{
|
||||
return cir_regs[cir->port]->rfsr & CIR_RXFBC_MASK;
|
||||
}
|
||||
|
||||
char cir_read_data(struct cir_port *cir)
|
||||
{
|
||||
return cir_regs[cir->port]->dr;
|
||||
}
|
||||
|
||||
char get_int_status(struct cir_port *cir)
|
||||
{
|
||||
return cir_regs[cir->port]->iir;
|
||||
}
|
||||
#endif
|
||||
@@ -1,352 +0,0 @@
|
||||
/*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* IT8172/QED5231 board setup.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <linux/major.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/root_dev.h>
|
||||
#include <linux/pm.h>
|
||||
|
||||
#include <asm/cpu.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
#include <asm/it8712.h>
|
||||
|
||||
extern struct resource ioport_resource;
|
||||
#ifdef CONFIG_SERIO_I8042
|
||||
int init_8712_keyboard(void);
|
||||
#endif
|
||||
|
||||
extern int SearchIT8712(void);
|
||||
extern void InitLPCInterface(void);
|
||||
extern char * __init prom_getcmdline(void);
|
||||
extern void it8172_restart(char *command);
|
||||
extern void it8172_halt(void);
|
||||
extern void it8172_power_off(void);
|
||||
|
||||
extern void it8172_time_init(void);
|
||||
|
||||
#ifdef CONFIG_IT8172_REVC
|
||||
struct {
|
||||
struct resource ram;
|
||||
struct resource pci_mem;
|
||||
struct resource pci_io;
|
||||
struct resource flash;
|
||||
struct resource boot;
|
||||
} it8172_resources = {
|
||||
{
|
||||
.start = 0, /* to be initted */
|
||||
.end = 0,
|
||||
.name = "RAM",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x10000000,
|
||||
.end = 0x13FFFFFF,
|
||||
.name = "PCI Mem",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x14000000,
|
||||
.end = 0x17FFFFFF
|
||||
.name = "PCI I/O",
|
||||
}, {
|
||||
.start = 0x08000000,
|
||||
.end = 0x0CFFFFFF
|
||||
.name = "Flash",
|
||||
}, {
|
||||
.start = 0x1FC00000,
|
||||
.end = 0x1FFFFFFF
|
||||
.name = "Boot ROM",
|
||||
}
|
||||
};
|
||||
#else
|
||||
struct {
|
||||
struct resource ram;
|
||||
struct resource pci_mem0;
|
||||
struct resource pci_mem1;
|
||||
struct resource pci_io;
|
||||
struct resource pci_mem2;
|
||||
struct resource pci_mem3;
|
||||
struct resource flash;
|
||||
struct resource boot;
|
||||
} it8172_resources = {
|
||||
{
|
||||
.start = 0, /* to be initted */
|
||||
.end = 0,
|
||||
.name = "RAM",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x0C000000,
|
||||
.end = 0x0FFFFFFF,
|
||||
.name = "PCI Mem0",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x10000000,
|
||||
.end = 0x13FFFFFF,
|
||||
.name = "PCI Mem1",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x14000000,
|
||||
.end = 0x17FFFFFF
|
||||
.name = "PCI I/O",
|
||||
}, {
|
||||
.start = 0x1A000000,
|
||||
.end = 0x1BFFFFFF,
|
||||
.name = "PCI Mem2",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x1C000000,
|
||||
.end = 0x1FBFFFFF,
|
||||
.name = "PCI Mem3",
|
||||
.flags = IORESOURCE_MEM
|
||||
}, {
|
||||
.start = 0x08000000,
|
||||
.end = 0x0CFFFFFF
|
||||
.name = "Flash",
|
||||
}, {
|
||||
.start = 0x1FC00000,
|
||||
.end = 0x1FFFFFFF
|
||||
.name = "Boot ROM",
|
||||
}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
void __init it8172_init_ram_resource(unsigned long memsize)
|
||||
{
|
||||
it8172_resources.ram.end = memsize;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
unsigned short dsr;
|
||||
char *argptr;
|
||||
|
||||
argptr = prom_getcmdline();
|
||||
#ifdef CONFIG_SERIAL_CONSOLE
|
||||
if ((argptr = strstr(argptr, "console=")) == NULL) {
|
||||
argptr = prom_getcmdline();
|
||||
strcat(argptr, " console=ttyS0,115200");
|
||||
}
|
||||
#endif
|
||||
|
||||
clear_c0_status(ST0_FR);
|
||||
|
||||
board_time_init = it8172_time_init;
|
||||
|
||||
_machine_restart = it8172_restart;
|
||||
_machine_halt = it8172_halt;
|
||||
pm_power_off = it8172_power_off;
|
||||
|
||||
/*
|
||||
* IO/MEM resources.
|
||||
*
|
||||
* revisit this area.
|
||||
*/
|
||||
set_io_port_base(KSEG1);
|
||||
ioport_resource.start = it8172_resources.pci_io.start;
|
||||
ioport_resource.end = it8172_resources.pci_io.end;
|
||||
#ifdef CONFIG_IT8172_REVC
|
||||
iomem_resource.start = it8172_resources.pci_mem.start;
|
||||
iomem_resource.end = it8172_resources.pci_mem.end;
|
||||
#else
|
||||
iomem_resource.start = it8172_resources.pci_mem0.start;
|
||||
iomem_resource.end = it8172_resources.pci_mem3.end;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BLK_DEV_INITRD
|
||||
ROOT_DEV = Root_RAM0;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pull enabled devices out of standby
|
||||
*/
|
||||
IT_IO_READ16(IT_PM_DSR, dsr);
|
||||
|
||||
/*
|
||||
* Fixme: This breaks when these drivers are modules!!!
|
||||
*/
|
||||
#ifdef CONFIG_SOUND_IT8172
|
||||
dsr &= ~IT_PM_DSR_ACSB;
|
||||
#else
|
||||
dsr |= IT_PM_DSR_ACSB;
|
||||
#endif
|
||||
#ifdef CONFIG_BLK_DEV_IT8172
|
||||
dsr &= ~IT_PM_DSR_IDESB;
|
||||
#else
|
||||
dsr |= IT_PM_DSR_IDESB;
|
||||
#endif
|
||||
IT_IO_WRITE16(IT_PM_DSR, dsr);
|
||||
|
||||
InitLPCInterface();
|
||||
|
||||
#ifdef CONFIG_MIPS_ITE8172
|
||||
if (SearchIT8712()) {
|
||||
printk("Found IT8712 Super IO\n");
|
||||
/* enable IT8712 serial port */
|
||||
LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */
|
||||
LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */
|
||||
#ifdef CONFIG_SERIO_I8042
|
||||
if (init_8712_keyboard()) {
|
||||
printk("Unable to initialize keyboard\n");
|
||||
LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */
|
||||
} else {
|
||||
LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */
|
||||
LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2);
|
||||
LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3);
|
||||
|
||||
LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */
|
||||
|
||||
LPCSetConfig(0x4, 0x30, 0x1);
|
||||
LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80);
|
||||
|
||||
if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) ||
|
||||
(LPCGetConfig(LDN_MOUSE, 0x30) == 0))
|
||||
printk("Error: keyboard or mouse not enabled\n");
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
printk("IT8712 Super IO not found\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IT8172_CIR
|
||||
{
|
||||
unsigned long data;
|
||||
//printk("Enabling CIR0\n");
|
||||
IT_IO_READ16(IT_PM_DSR, data);
|
||||
data &= ~IT_PM_DSR_CIR0SB;
|
||||
IT_IO_WRITE16(IT_PM_DSR, data);
|
||||
//printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data));
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_IT8172_SCR0
|
||||
{
|
||||
unsigned i;
|
||||
/* Enable Smart Card Reader 0 */
|
||||
/* First power it up */
|
||||
IT_IO_READ16(IT_PM_DSR, i);
|
||||
i &= ~IT_PM_DSR_SCR0SB;
|
||||
IT_IO_WRITE16(IT_PM_DSR, i);
|
||||
/* Then initialize its registers */
|
||||
outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
|
||||
|IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
|
||||
|IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
|
||||
|IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
|
||||
|IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
|
||||
IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR);
|
||||
outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
|
||||
IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR);
|
||||
}
|
||||
#endif /* CONFIG_IT8172_SCR0 */
|
||||
#ifdef CONFIG_IT8172_SCR1
|
||||
{
|
||||
unsigned i;
|
||||
/* Enable Smart Card Reader 1 */
|
||||
/* First power it up */
|
||||
IT_IO_READ16(IT_PM_DSR, i);
|
||||
i &= ~IT_PM_DSR_SCR1SB;
|
||||
IT_IO_WRITE16(IT_PM_DSR, i);
|
||||
/* Then initialize its registers */
|
||||
outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT
|
||||
|IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT
|
||||
|IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT
|
||||
|IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT
|
||||
|IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT),
|
||||
IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR);
|
||||
outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT,
|
||||
IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR);
|
||||
}
|
||||
#endif /* CONFIG_IT8172_SCR1 */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIO_I8042
|
||||
/*
|
||||
* According to the ITE Special BIOS Note for waking up the
|
||||
* keyboard controller...
|
||||
*/
|
||||
static int init_8712_keyboard(void)
|
||||
{
|
||||
unsigned int cmd_port = 0x14000064;
|
||||
unsigned int data_port = 0x14000060;
|
||||
^^^^^^^^^^^
|
||||
Somebody here doesn't grok the concept of io ports.
|
||||
|
||||
unsigned char data;
|
||||
int i;
|
||||
|
||||
outb(0xaa, cmd_port); /* send self-test cmd */
|
||||
i = 0;
|
||||
while (!(inb(cmd_port) & 0x1)) { /* wait output buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
|
||||
data = inb(data_port);
|
||||
outb(0xcb, cmd_port); /* set ps2 mode */
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
outb(0x01, data_port);
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
|
||||
outb(0x60, cmd_port); /* write 8042 command byte */
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
outb(0x45, data_port); /* at interface, keyboard enabled, system flag */
|
||||
while (inb(cmd_port) & 0x2) { /* wait while input buffer full */
|
||||
i++;
|
||||
if (i > 0xffffff)
|
||||
return 1;
|
||||
}
|
||||
|
||||
outb(0xae, cmd_port); /* enable interface */
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@@ -1,144 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* ITE Semi IT8712 Super I/O functions.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/it8712.h>
|
||||
#include <asm/it8172/it8172.h>
|
||||
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
void LPCEnterMBPnP(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
|
||||
|
||||
for (i = 0; i<4; i++)
|
||||
outb(key[i], LPC_KEY_ADDR);
|
||||
|
||||
}
|
||||
|
||||
void LPCExitMBPnP(void)
|
||||
{
|
||||
outb(0x02, LPC_KEY_ADDR);
|
||||
outb(0x02, LPC_DATA_ADDR);
|
||||
}
|
||||
|
||||
void LPCSetConfig(char LdnNumber, char Index, char data)
|
||||
{
|
||||
LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
|
||||
outb(0x07, LPC_KEY_ADDR);
|
||||
outb(LdnNumber, LPC_DATA_ADDR);
|
||||
outb(Index, LPC_KEY_ADDR);
|
||||
outb(data, LPC_DATA_ADDR);
|
||||
LPCExitMBPnP();
|
||||
}
|
||||
|
||||
char LPCGetConfig(char LdnNumber, char Index)
|
||||
{
|
||||
char rtn;
|
||||
|
||||
LPCEnterMBPnP(); // Enter IT8712 MB PnP mode
|
||||
outb(0x07, LPC_KEY_ADDR);
|
||||
outb(LdnNumber, LPC_DATA_ADDR);
|
||||
outb(Index, LPC_KEY_ADDR);
|
||||
rtn = inb(LPC_DATA_ADDR);
|
||||
LPCExitMBPnP();
|
||||
return rtn;
|
||||
}
|
||||
|
||||
int SearchIT8712(void)
|
||||
{
|
||||
unsigned char Id1, Id2;
|
||||
unsigned short Id;
|
||||
|
||||
LPCEnterMBPnP();
|
||||
outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
|
||||
Id1 = inb(LPC_DATA_ADDR);
|
||||
outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
|
||||
Id2 = inb(LPC_DATA_ADDR);
|
||||
Id = (Id1 << 8) | Id2;
|
||||
LPCExitMBPnP();
|
||||
if (Id == 0x8712)
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
void InitLPCInterface(void)
|
||||
{
|
||||
unsigned char bus, dev_fn;
|
||||
unsigned long data;
|
||||
|
||||
bus = 0;
|
||||
dev_fn = 1<<3 | 4;
|
||||
|
||||
|
||||
/* pci cmd, SERR# Enable */
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x4 / 4) << IT_REGNUM_SHF));
|
||||
IT_READ(IT_CONFDATA, data);
|
||||
data |= 0x0100;
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x4 / 4) << IT_REGNUM_SHF));
|
||||
IT_WRITE(IT_CONFDATA, data);
|
||||
|
||||
/* setup serial irq control register */
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x48 / 4) << IT_REGNUM_SHF));
|
||||
IT_READ(IT_CONFDATA, data);
|
||||
data = (data & 0xffff00ff) | 0xc400;
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x48 / 4) << IT_REGNUM_SHF));
|
||||
IT_WRITE(IT_CONFDATA, data);
|
||||
|
||||
|
||||
/* Enable I/O Space Subtractive Decode */
|
||||
/* default 0x4C is 0x3f220000 */
|
||||
IT_WRITE(IT_CONFADDR,
|
||||
(bus << IT_BUSNUM_SHF) |
|
||||
(dev_fn << IT_FUNCNUM_SHF) |
|
||||
((0x4C / 4) << IT_REGNUM_SHF));
|
||||
IT_WRITE(IT_CONFDATA, 0x3f2200f3);
|
||||
}
|
||||
@@ -1,135 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* PROM library initialisation code, assuming a version of
|
||||
* pmon is the boot code.
|
||||
*
|
||||
* Copyright 2000 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This file was derived from Carsten Langgaard's
|
||||
* arch/mips/mips-boards/xx files.
|
||||
*
|
||||
* Carsten Langgaard, carstenl@mips.com
|
||||
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
extern int prom_argc;
|
||||
extern char **prom_argv, **prom_envp;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char *name;
|
||||
/* char *val; */
|
||||
}t_env_var;
|
||||
|
||||
|
||||
char * __init prom_getcmdline(void)
|
||||
{
|
||||
return &(arcs_cmdline[0]);
|
||||
}
|
||||
|
||||
void __init prom_init_cmdline(void)
|
||||
{
|
||||
char *cp;
|
||||
int actr;
|
||||
|
||||
actr = 1; /* Always ignore argv[0] */
|
||||
|
||||
cp = &(arcs_cmdline[0]);
|
||||
while(actr < prom_argc) {
|
||||
strcpy(cp, prom_argv[actr]);
|
||||
cp += strlen(prom_argv[actr]);
|
||||
*cp++ = ' ';
|
||||
actr++;
|
||||
}
|
||||
if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
|
||||
--cp;
|
||||
*cp = '\0';
|
||||
|
||||
}
|
||||
|
||||
|
||||
char *prom_getenv(char *envname)
|
||||
{
|
||||
/*
|
||||
* Return a pointer to the given environment variable.
|
||||
* Environment variables are stored in the form of "memsize=64".
|
||||
*/
|
||||
|
||||
t_env_var *env = (t_env_var *)prom_envp;
|
||||
int i;
|
||||
|
||||
i = strlen(envname);
|
||||
|
||||
while(env->name) {
|
||||
if(strncmp(envname, env->name, i) == 0) {
|
||||
return(env->name + strlen(envname) + 1);
|
||||
}
|
||||
env++;
|
||||
}
|
||||
return(NULL);
|
||||
}
|
||||
|
||||
static inline unsigned char str2hexnum(unsigned char c)
|
||||
{
|
||||
if(c >= '0' && c <= '9')
|
||||
return c - '0';
|
||||
if(c >= 'a' && c <= 'f')
|
||||
return c - 'a' + 10;
|
||||
return 0; /* foo */
|
||||
}
|
||||
|
||||
unsigned long __init prom_free_prom_memory(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long __init prom_get_memsize(void)
|
||||
{
|
||||
char *memsize_str;
|
||||
unsigned int memsize;
|
||||
|
||||
memsize_str = prom_getenv("memsize");
|
||||
if (!memsize_str) {
|
||||
#ifdef CONFIG_MIPS_ITE8172
|
||||
memsize = 32;
|
||||
#elif defined(CONFIG_MIPS_IVR)
|
||||
memsize = 64;
|
||||
#else
|
||||
memsize = 8;
|
||||
#endif
|
||||
printk("memsize unknown: setting to %dMB\n", memsize);
|
||||
} else {
|
||||
printk("memsize: %s\n", memsize_str);
|
||||
memsize = simple_strtol(memsize_str, NULL, 0);
|
||||
}
|
||||
return memsize;
|
||||
}
|
||||
@@ -1,139 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* Low level uart routines to directly access a 16550 uart.
|
||||
*
|
||||
* Copyright 2000,2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#define SERIAL_BASE 0xB4011800 /* it8172 */
|
||||
#define SER_CMD 5
|
||||
#define SER_DATA 0x00
|
||||
#define TX_BUSY 0x20
|
||||
|
||||
#define TIMEOUT 0xffff
|
||||
#undef SLOW_DOWN
|
||||
|
||||
static const char digits[16] = "0123456789abcdef";
|
||||
static volatile unsigned char *const com1 = (unsigned char *) SERIAL_BASE;
|
||||
|
||||
|
||||
#ifdef SLOW_DOWN
|
||||
static inline void slow_down()
|
||||
{
|
||||
int k;
|
||||
for (k = 0; k < 10000; k++);
|
||||
}
|
||||
#else
|
||||
#define slow_down()
|
||||
#endif
|
||||
|
||||
void putch(const unsigned char c)
|
||||
{
|
||||
unsigned char ch;
|
||||
int i = 0;
|
||||
|
||||
do {
|
||||
ch = com1[SER_CMD];
|
||||
slow_down();
|
||||
i++;
|
||||
if (i > TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (0 == (ch & TX_BUSY));
|
||||
com1[SER_DATA] = c;
|
||||
}
|
||||
|
||||
void puts(unsigned char *cp)
|
||||
{
|
||||
unsigned char ch;
|
||||
int i = 0;
|
||||
|
||||
while (*cp) {
|
||||
do {
|
||||
ch = com1[SER_CMD];
|
||||
slow_down();
|
||||
i++;
|
||||
if (i > TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (0 == (ch & TX_BUSY));
|
||||
com1[SER_DATA] = *cp++;
|
||||
}
|
||||
putch('\r');
|
||||
putch('\n');
|
||||
}
|
||||
|
||||
void fputs(unsigned char *cp)
|
||||
{
|
||||
unsigned char ch;
|
||||
int i = 0;
|
||||
|
||||
while (*cp) {
|
||||
|
||||
do {
|
||||
ch = com1[SER_CMD];
|
||||
slow_down();
|
||||
i++;
|
||||
if (i > TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (0 == (ch & TX_BUSY));
|
||||
com1[SER_DATA] = *cp++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void put64(uint64_t ul)
|
||||
{
|
||||
int cnt;
|
||||
unsigned ch;
|
||||
|
||||
cnt = 16; /* 16 nibbles in a 64 bit long */
|
||||
putch('0');
|
||||
putch('x');
|
||||
do {
|
||||
cnt--;
|
||||
ch = (unsigned char) (ul >> cnt * 4) & 0x0F;
|
||||
putch(digits[ch]);
|
||||
} while (cnt > 0);
|
||||
}
|
||||
|
||||
void put32(unsigned u)
|
||||
{
|
||||
int cnt;
|
||||
unsigned ch;
|
||||
|
||||
cnt = 8; /* 8 nibbles in a 32 bit long */
|
||||
putch('0');
|
||||
putch('x');
|
||||
do {
|
||||
cnt--;
|
||||
ch = (unsigned char) (u >> cnt * 4) & 0x0F;
|
||||
putch(digits[ch]);
|
||||
} while (cnt > 0);
|
||||
}
|
||||
@@ -1,60 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* BRIEF MODULE DESCRIPTION
|
||||
* ITE 8172 reset routines.
|
||||
*
|
||||
* Copyright 2001 MontaVista Software Inc.
|
||||
* Author: MontaVista Software, Inc.
|
||||
* ppopov@mvista.com or source@mvista.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
|
||||
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/mm.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/system.h>
|
||||
|
||||
void it8172_restart()
|
||||
{
|
||||
set_c0_status(ST0_BEV | ST0_ERL);
|
||||
change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
|
||||
flush_cache_all();
|
||||
write_c0_wired(0);
|
||||
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
|
||||
}
|
||||
|
||||
void it8172_halt(void)
|
||||
{
|
||||
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
|
||||
while (1)
|
||||
__asm__(".set\tmips3\n\t"
|
||||
"wait\n\t"
|
||||
".set\tmips0");
|
||||
}
|
||||
|
||||
void it8172_power_off(void)
|
||||
{
|
||||
it8172_halt();
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user