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MIPS: Convert the irq functions to the new names

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Scripted with coccinelle.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Thomas Gleixner
2011-03-27 15:19:28 +02:00
parent 9efbc3fba2
commit e4ec7989b4
59 changed files with 185 additions and 167 deletions
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6
arch/mips/alchemy/devboards/bcsr.c
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@@ -142,8 +142,8 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
bcsr_csc_base = csc_start;
for (irq = csc_start; irq <= csc_end; irq++)
set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
handle_level_irq, "level");
irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
handle_level_irq, "level");
set_irq_chained_handler(hook_irq, bcsr_csc_handler);
irq_set_chained_handler(hook_irq, bcsr_csc_handler);
}

2
arch/mips/alchemy/devboards/db1200/setup.c
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@@ -63,7 +63,7 @@ void __init board_setup(void)
static int __init db1200_arch_init(void)
{
/* GPIO7 is low-level triggered CPLD cascade */
set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
/* insert/eject pairs: one of both is always screaming. To avoid

50
arch/mips/alchemy/devboards/db1x00/board_setup.c
View File

@@ -215,35 +215,35 @@ void __init board_setup(void)
static int __init db1x00_init_irq(void)
{
#if defined(CONFIG_MIPS_MIRAGE)
set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
#elif defined(CONFIG_MIPS_DB1550)
set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW); /* CD1# */
irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW); /* CARD0# */
irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1500)
set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1100)
set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#elif defined(CONFIG_MIPS_DB1000)
set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
#endif
return 0;
}

2
arch/mips/alchemy/devboards/pb1000/board_setup.c
View File

@@ -197,7 +197,7 @@ void __init board_setup(void)
static int __init pb1000_init_irq(void)
{
set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
return 0;
}
arch_initcall(pb1000_init_irq);

8
arch/mips/alchemy/devboards/pb1100/board_setup.c
View File

@@ -117,10 +117,10 @@ void __init board_setup(void)
static int __init pb1100_init_irq(void)
{
set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
return 0;
}

2
arch/mips/alchemy/devboards/pb1200/board_setup.c
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@@ -142,7 +142,7 @@ static int __init pb1200_init_irq(void)
panic("Game over. Your score is 0.");
}
set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
return 0;

16
arch/mips/alchemy/devboards/pb1500/board_setup.c
View File

@@ -134,14 +134,14 @@ void __init board_setup(void)
static int __init pb1500_init_irq(void)
{
set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW); /* CD0# */
irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW); /* CARD0 */
irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
return 0;
}

6
arch/mips/alchemy/devboards/pb1550/board_setup.c
View File

@@ -73,9 +73,9 @@ void __init board_setup(void)
static int __init pb1550_init_irq(void)
{
set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
/* enable both PCMCIA card irqs in the shared line */
alchemy_gpio2_enable_int(201);

10
arch/mips/alchemy/mtx-1/board_setup.c
View File

@@ -123,11 +123,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
static int __init mtx1_init_irq(void)
{
set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
return 0;
}

24
arch/mips/alchemy/xxs1500/board_setup.c
View File

@@ -85,19 +85,19 @@ void __init board_setup(void)
static int __init xxs1500_init_irq(void)
{
set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
return 0;
}

4
arch/mips/ar7/irq.c
View File

@@ -119,11 +119,11 @@ static void __init ar7_irq_init(int base)
for (i = 0; i < 40; i++) {
writel(i, REG(CHNL_OFFSET(i)));
/* Primary IRQ's */
set_irq_chip_and_handler(base + i, &ar7_irq_type,
irq_set_chip_and_handler(base + i, &ar7_irq_type,
handle_level_irq);
/* Secondary IRQ's */
if (i < 32)
set_irq_chip_and_handler(base + i + 40,
irq_set_chip_and_handler(base + i + 40,
&ar7_sec_irq_type,
handle_level_irq);
}

4
arch/mips/ath79/irq.c
View File

@@ -124,11 +124,11 @@ static void __init ath79_misc_irq_init(void)
for (i = ATH79_MISC_IRQ_BASE;
i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
handle_level_irq);
}
set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
}
asmlinkage void plat_irq_dispatch(void)

4
arch/mips/bcm63xx/irq.c
View File

@@ -230,11 +230,11 @@ void __init arch_init_irq(void)
mips_cpu_irq_init();
for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
handle_level_irq);
for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
handle_edge_irq);
setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);

4
arch/mips/dec/ioasic-irq.c
View File

@@ -68,10 +68,10 @@ void __init init_ioasic_irqs(int base)
fast_iob();
for (i = base; i < base + IO_INR_DMA; i++)
set_irq_chip_and_handler(i, &ioasic_irq_type,
irq_set_chip_and_handler(i, &ioasic_irq_type,
handle_level_irq);
for (; i < base + IO_IRQ_LINES; i++)
set_irq_chip(i, &ioasic_dma_irq_type);
irq_set_chip(i, &ioasic_dma_irq_type);
ioasic_irq_base = base;
}

2
arch/mips/dec/kn02-irq.c
View File

@@ -73,7 +73,7 @@ void __init init_kn02_irqs(int base)
iob();
for (i = base; i < base + KN02_IRQ_LINES; i++)
set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
kn02_irq_base = base;
}

6
arch/mips/emma/markeins/irq.c
View File

@@ -69,7 +69,7 @@ void emma2rh_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
&emma2rh_irq_controller,
handle_level_irq, "level");
}
@@ -105,7 +105,7 @@ void emma2rh_sw_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
&emma2rh_sw_irq_controller,
handle_level_irq, "level");
}
@@ -162,7 +162,7 @@ void emma2rh_gpio_irq_init(void)
u32 i;
for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller,
handle_edge_irq, "edge");
}

2
arch/mips/jazz/irq.c
View File

@@ -56,7 +56,7 @@ void __init init_r4030_ints(void)
int i;
for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */

14
arch/mips/jz4740/gpio.c
View File

@@ -306,7 +306,7 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
uint32_t flag;
unsigned int gpio_irq;
unsigned int gpio_bank;
struct jz_gpio_chip *chip = get_irq_desc_data(desc);
struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
gpio_bank = JZ4740_IRQ_GPIO0 - irq;
@@ -416,7 +416,7 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
chip->wakeup &= ~IRQ_TO_BIT(data->irq);
spin_unlock(&chip->lock);
set_irq_wake(chip->irq, on);
irq_set_irq_wake(chip->irq, on);
return 0;
}
@@ -510,14 +510,14 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
gpiochip_add(&chip->gpio_chip);
chip->irq = JZ4740_IRQ_INTC_GPIO(id);
set_irq_data(chip->irq, chip);
set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
irq_set_handler_data(chip->irq, chip);
irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
irq_set_lockdep_class(irq, &gpio_lock_class);
set_irq_chip_data(irq, chip);
set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
handle_level_irq);
irq_set_chip_data(irq, chip);
irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
handle_level_irq);
}
return 0;

4
arch/mips/jz4740/irq.c
View File

@@ -104,8 +104,8 @@ void __init arch_init_irq(void)
writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
set_irq_chip_data(i, (void *)IRQ_BIT(i));
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
irq_set_chip_data(i, (void *)IRQ_BIT(i));
irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
}
setup_irq(2, &jz4740_cascade_action);

6
arch/mips/kernel/i8259.c
View File

@@ -110,7 +110,7 @@ int i8259A_irq_pending(unsigned int irq)
void make_8259A_irq(unsigned int irq)
{
disable_irq_nosync(irq);
set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
enable_irq(irq);
}
@@ -336,8 +336,8 @@ void __init init_i8259_irqs(void)
init_8259A(0);
for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
set_irq_probe(i);
irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
irq_set_probe(i);
}
setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);

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