mirror of
https://github.com/armbian/linux.git
synced 2026-01-06 10:13:00 -08:00
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (36 commits) powerpc/gc/wii: Remove get_irq_desc() powerpc/gc/wii: hlwd-pic: convert irq_desc.lock to raw_spinlock powerpc/gamecube/wii: Fix off-by-one error in ugecon/usbgecko_udbg powerpc/mpic: Fix problem that affinity is not updated powerpc/mm: Fix stupid bug in subpge protection handling powerpc/iseries: use DECLARE_COMPLETION_ONSTACK for non-constant completion powerpc: Fix MSI support on U4 bridge PCIe slot powerpc: Handle VSX alignment faults correctly in little-endian mode powerpc/mm: Fix typo of cpumask_clear_cpu() powerpc/mm: Fix hash_utils_64.c compile errors with DEBUG enabled. powerpc: Convert BUG() to use unreachable() powerpc/pseries: Make declarations of cpu_hotplug_driver_lock() ANSI compatible. powerpc/pseries: Don't panic when H_PROD fails during cpu-online. powerpc/mm: Fix a WARN_ON() with CONFIG_DEBUG_PAGEALLOC and CONFIG_DEBUG_VM powerpc/defconfigs: Set HZ=100 on pseries and ppc64 defconfigs powerpc/defconfigs: Disable token ring in powerpc defconfigs powerpc/defconfigs: Reduce 64bit vmlinux by making acenic and cramfs modules powerpc/pseries: Select XICS and PCI_MSI PSERIES powerpc/85xx: Wrong variable returned on error powerpc/iseries: Convert to proc_fops ...
This commit is contained in:
Linus Torvalds
42
Documentation/powerpc/dts-bindings/fsl/mpic.txt
Normal file
42
Documentation/powerpc/dts-bindings/fsl/mpic.txt
Normal file
@@ -0,0 +1,42 @@
|
||||
* OpenPIC and its interrupt numbers on Freescale's e500/e600 cores
|
||||
|
||||
The OpenPIC specification does not specify which interrupt source has to
|
||||
become which interrupt number. This is up to the software implementation
|
||||
of the interrupt controller. The only requirement is that every
|
||||
interrupt source has to have an unique interrupt number / vector number.
|
||||
To accomplish this the current implementation assigns the number zero to
|
||||
the first source, the number one to the second source and so on until
|
||||
all interrupt sources have their unique number.
|
||||
Usually the assigned vector number equals the interrupt number mentioned
|
||||
in the documentation for a given core / CPU. This is however not true
|
||||
for the e500 cores (MPC85XX CPUs) where the documentation distinguishes
|
||||
between internal and external interrupt sources and starts counting at
|
||||
zero for both of them.
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|
||||
So what to write for external interrupt source X or internal interrupt
|
||||
source Y into the device tree? Here is an example:
|
||||
|
||||
The memory map for the interrupt controller in the MPC8544[0] shows,
|
||||
that the first interrupt source starts at 0x5_0000 (PIC Register Address
|
||||
Map-Interrupt Source Configuration Registers). This source becomes the
|
||||
number zero therefore:
|
||||
External interrupt 0 = interrupt number 0
|
||||
External interrupt 1 = interrupt number 1
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||||
External interrupt 2 = interrupt number 2
|
||||
...
|
||||
Every interrupt number allocates 0x20 bytes register space. So to get
|
||||
its number it is sufficient to shift the lower 16bits to right by five.
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So for the external interrupt 10 we have:
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0x0140 >> 5 = 10
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|
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After the external sources, the internal sources follow. The in core I2C
|
||||
controller on the MPC8544 for instance has the internal source number
|
||||
27. Oo obtain its interrupt number we take the lower 16bits of its memory
|
||||
address (0x5_0560) and shift it right:
|
||||
0x0560 >> 5 = 43
|
||||
|
||||
Therefore the I2C device node for the MPC8544 CPU has to have the
|
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interrupt number 43 specified in the device tree.
|
||||
|
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[0] MPC8544E PowerQUICCTM III, Integrated Host Processor Family Reference Manual
|
||||
MPC8544ERM Rev. 1 10/2007
|
||||
@@ -108,12 +108,19 @@
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||||
dcr-reg = <0x00c 0x002>;
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||||
};
|
||||
|
||||
MQ0: mq {
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||||
compatible = "ibm,mq-440spe";
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||||
dcr-reg = <0x040 0x020>;
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||||
};
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||||
|
||||
plb {
|
||||
compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
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||||
#address-cells = <2>;
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#size-cells = <1>;
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||||
/* addr-child addr-parent size */
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ranges = <0x4 0xe0000000 0x4 0xe0000000 0x20000000
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ranges = <0x4 0x00100000 0x4 0x00100000 0x00001000
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0x4 0x00200000 0x4 0x00200000 0x00000400
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0x4 0xe0000000 0x4 0xe0000000 0x20000000
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0xc 0x00000000 0xc 0x00000000 0x20000000
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||||
0xd 0x00000000 0xd 0x00000000 0x80000000
|
||||
0xd 0x80000000 0xd 0x80000000 0x80000000
|
||||
@@ -400,6 +407,49 @@
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||||
0x0 0x0 0x0 0x3 &UIC3 0xa 0x4 /* swizzled int C */
|
||||
0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
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||||
};
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||||
|
||||
I2O: i2o@400100000 {
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||||
compatible = "ibm,i2o-440spe";
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reg = <0x00000004 0x00100000 0x100>;
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dcr-reg = <0x060 0x020>;
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||||
};
|
||||
|
||||
DMA0: dma0@400100100 {
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||||
compatible = "ibm,dma-440spe";
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||||
cell-index = <0>;
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reg = <0x00000004 0x00100100 0x100>;
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dcr-reg = <0x060 0x020>;
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||||
interrupt-parent = <&DMA0>;
|
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interrupts = <0 1>;
|
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#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <
|
||||
0 &UIC0 0x14 4
|
||||
1 &UIC1 0x16 4>;
|
||||
};
|
||||
|
||||
DMA1: dma1@400100200 {
|
||||
compatible = "ibm,dma-440spe";
|
||||
cell-index = <1>;
|
||||
reg = <0x00000004 0x00100200 0x100>;
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||||
dcr-reg = <0x060 0x020>;
|
||||
interrupt-parent = <&DMA1>;
|
||||
interrupts = <0 1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = <
|
||||
0 &UIC0 0x16 4
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||||
1 &UIC1 0x16 4>;
|
||||
};
|
||||
|
||||
xor-accel@400200000 {
|
||||
compatible = "amcc,xor-accelerator";
|
||||
reg = <0x00000004 0x00200000 0x400>;
|
||||
interrupt-parent = <&UIC1>;
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||||
interrupts = <0x1f 4>;
|
||||
};
|
||||
};
|
||||
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||||
chosen {
|
||||
|
||||
@@ -204,6 +204,7 @@
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interrupt-parent = <&ipic>;
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||||
tbi-handle = <&tbi0>;
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||||
phy-handle = < &phy0 >;
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fsl,magic-packet;
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||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
@@ -246,6 +247,7 @@
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi1>;
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phy-handle = < &phy1 >;
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fsl,magic-packet;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
@@ -309,6 +311,22 @@
|
||||
interrupt-parent = <&ipic>;
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||||
};
|
||||
|
||||
gtm1: timer@500 {
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||||
compatible = "fsl,mpc8315-gtm", "fsl,gtm";
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||||
reg = <0x500 0x100>;
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||||
interrupts = <90 8 78 8 84 8 72 8>;
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||||
interrupt-parent = <&ipic>;
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||||
clock-frequency = <133333333>;
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||||
};
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||||
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timer@600 {
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compatible = "fsl,mpc8315-gtm", "fsl,gtm";
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reg = <0x600 0x100>;
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interrupts = <91 8 79 8 85 8 73 8>;
|
||||
interrupt-parent = <&ipic>;
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||||
clock-frequency = <133333333>;
|
||||
};
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||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
@@ -337,6 +355,15 @@
|
||||
0x59 0x8>;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
pmc: power@b00 {
|
||||
compatible = "fsl,mpc8315-pmc", "fsl,mpc8313-pmc",
|
||||
"fsl,mpc8349-pmc";
|
||||
reg = <0xb00 0x100 0xa00 0x100>;
|
||||
interrupts = <80 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
fsl,mpc8313-wakeup-timer = <>m1>;
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
|
||||
@@ -63,6 +63,24 @@
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||||
reg = <0x200 0x100>;
|
||||
};
|
||||
|
||||
gpio1: gpio-controller@c00 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <74 0x8>;
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||||
interrupt-parent = <&ipic>;
|
||||
gpio-controller;
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||||
};
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||||
|
||||
gpio2: gpio-controller@d00 {
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||||
#gpio-cells = <2>;
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||||
compatible = "fsl,mpc8349-gpio";
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||||
reg = <0xd00 0x100>;
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||||
interrupts = <75 0x8>;
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||||
interrupt-parent = <&ipic>;
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||||
gpio-controller;
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||||
};
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|
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i2c@3000 {
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||||
#address-cells = <1>;
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#size-cells = <0>;
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||||
@@ -72,6 +90,12 @@
|
||||
interrupts = <14 0x8>;
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||||
interrupt-parent = <&ipic>;
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||||
dfsrr;
|
||||
|
||||
eeprom: at24@50 {
|
||||
compatible = "st-micro,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
@@ -91,6 +115,25 @@
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
pcf1: iexp@38 {
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||||
#gpio-cells = <2>;
|
||||
compatible = "ti,pcf8574a";
|
||||
reg = <0x38>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
pcf2: iexp@39 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "ti,pcf8574a";
|
||||
reg = <0x39>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
spd: at24@51 {
|
||||
compatible = "at24,spd";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
mcu_pio: mcu@a {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mc9s08qg8-mpc8349emitx",
|
||||
@@ -275,6 +318,24 @@
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
green {
|
||||
label = "Green";
|
||||
gpios = <&pcf1 0 1>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
yellow {
|
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label = "Yellow";
|
||||
gpios = <&pcf1 1 1>;
|
||||
/* linux,default-trigger = "heartbeat"; */
|
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default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pci@e0008500 {
|
||||
@@ -331,7 +392,26 @@
|
||||
compatible = "fsl,mpc8349e-localbus",
|
||||
"fsl,pq2pro-localbus";
|
||||
reg = <0xe0005000 0xd8>;
|
||||
ranges = <0x3 0x0 0xf0000000 0x210>;
|
||||
ranges = <0x0 0x0 0xfe000000 0x1000000 /* flash */
|
||||
0x1 0x0 0xf8000000 0x20000 /* VSC 7385 */
|
||||
0x2 0x0 0xf9000000 0x200000 /* exp slot */
|
||||
0x3 0x0 0xf0000000 0x210>; /* CF slot */
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
flash@0,800000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x800000 0x800000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
pata@3,0 {
|
||||
compatible = "fsl,mpc8349emitx-pata", "ata-generic";
|
||||
|
||||
@@ -146,7 +146,7 @@
|
||||
|
||||
fpga@2,4000 {
|
||||
compatible = "pika,fpga-sd";
|
||||
reg = <0x00000002 0x00004000 0x00000A00>;
|
||||
reg = <0x00000002 0x00004000 0x00004000>;
|
||||
};
|
||||
|
||||
nor@0,0 {
|
||||
|
||||
@@ -86,7 +86,7 @@ static void ug_putc(char ch)
|
||||
|
||||
while (!ug_is_txfifo_ready() && count--)
|
||||
barrier();
|
||||
if (count)
|
||||
if (count >= 0)
|
||||
ug_raw_putc(ch);
|
||||
}
|
||||
|
||||
|
||||
@@ -757,7 +757,7 @@ CONFIG_SUNGEM=y
|
||||
# CONFIG_B44 is not set
|
||||
# CONFIG_ATL2 is not set
|
||||
CONFIG_NETDEV_1000=y
|
||||
CONFIG_ACENIC=y
|
||||
CONFIG_ACENIC=m
|
||||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
# CONFIG_DL2K is not set
|
||||
CONFIG_E1000=y
|
||||
@@ -794,8 +794,8 @@ CONFIG_NETDEV_10000=y
|
||||
# CONFIG_BNX2X is not set
|
||||
# CONFIG_QLGE is not set
|
||||
# CONFIG_SFC is not set
|
||||
CONFIG_TR=y
|
||||
CONFIG_IBMOL=y
|
||||
# CONFIG_TR is not set
|
||||
# CONFIG_IBMOL is not set
|
||||
# CONFIG_3C359 is not set
|
||||
# CONFIG_TMS380TR is not set
|
||||
|
||||
|
||||
@@ -714,8 +714,8 @@ CONFIG_NETDEV_10000=y
|
||||
# CONFIG_BNX2X is not set
|
||||
# CONFIG_QLGE is not set
|
||||
# CONFIG_SFC is not set
|
||||
CONFIG_TR=y
|
||||
CONFIG_IBMOL=y
|
||||
# CONFIG_TR is not set
|
||||
# CONFIG_IBMOL is not set
|
||||
# CONFIG_3C359 is not set
|
||||
# CONFIG_TMS380TR is not set
|
||||
|
||||
|
||||
@@ -304,11 +304,11 @@ CONFIG_TICK_ONESHOT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_HZ_100=y
|
||||
# CONFIG_HZ_250 is not set
|
||||
# CONFIG_HZ_300 is not set
|
||||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_HZ=100
|
||||
CONFIG_SCHED_HRTICK=y
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
@@ -980,7 +980,7 @@ CONFIG_E100=y
|
||||
# CONFIG_SC92031 is not set
|
||||
# CONFIG_ATL2 is not set
|
||||
CONFIG_NETDEV_1000=y
|
||||
CONFIG_ACENIC=y
|
||||
CONFIG_ACENIC=m
|
||||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
# CONFIG_DL2K is not set
|
||||
CONFIG_E1000=y
|
||||
@@ -1023,8 +1023,8 @@ CONFIG_PASEMI_MAC=y
|
||||
# CONFIG_BNX2X is not set
|
||||
# CONFIG_QLGE is not set
|
||||
# CONFIG_SFC is not set
|
||||
CONFIG_TR=y
|
||||
CONFIG_IBMOL=y
|
||||
# CONFIG_TR is not set
|
||||
# CONFIG_IBMOL is not set
|
||||
# CONFIG_3C359 is not set
|
||||
# CONFIG_TMS380TR is not set
|
||||
|
||||
@@ -1863,7 +1863,7 @@ CONFIG_HFSPLUS_FS=m
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_CRAMFS=m
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_OMFS_FS is not set
|
||||
|
||||
@@ -1008,8 +1008,8 @@ CONFIG_IXGB=m
|
||||
# CONFIG_QLGE is not set
|
||||
# CONFIG_SFC is not set
|
||||
# CONFIG_BE2NET is not set
|
||||
CONFIG_TR=y
|
||||
CONFIG_IBMOL=y
|
||||
# CONFIG_TR is not set
|
||||
# CONFIG_IBMOL is not set
|
||||
# CONFIG_3C359 is not set
|
||||
# CONFIG_TMS380TR is not set
|
||||
CONFIG_WLAN=y
|
||||
|
||||
@@ -230,11 +230,11 @@ CONFIG_TICK_ONESHOT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_HZ_100=y
|
||||
# CONFIG_HZ_250 is not set
|
||||
# CONFIG_HZ_300 is not set
|
||||
# CONFIG_HZ_1000 is not set
|
||||
CONFIG_HZ=250
|
||||
CONFIG_HZ=100
|
||||
CONFIG_SCHED_HRTICK=y
|
||||
CONFIG_PREEMPT_NONE=y
|
||||
# CONFIG_PREEMPT_VOLUNTARY is not set
|
||||
@@ -796,7 +796,7 @@ CONFIG_E100=y
|
||||
# CONFIG_NET_POCKET is not set
|
||||
# CONFIG_ATL2 is not set
|
||||
CONFIG_NETDEV_1000=y
|
||||
CONFIG_ACENIC=y
|
||||
CONFIG_ACENIC=m
|
||||
CONFIG_ACENIC_OMIT_TIGON_I=y
|
||||
# CONFIG_DL2K is not set
|
||||
CONFIG_E1000=y
|
||||
@@ -834,8 +834,8 @@ CONFIG_S2IO=m
|
||||
# CONFIG_BNX2X is not set
|
||||
# CONFIG_QLGE is not set
|
||||
# CONFIG_SFC is not set
|
||||
CONFIG_TR=y
|
||||
CONFIG_IBMOL=y
|
||||
# CONFIG_TR is not set
|
||||
# CONFIG_IBMOL is not set
|
||||
# CONFIG_3C359 is not set
|
||||
# CONFIG_TMS380TR is not set
|
||||
|
||||
@@ -1494,7 +1494,7 @@ CONFIG_CONFIGFS_FS=m
|
||||
# CONFIG_BEFS_FS is not set
|
||||
# CONFIG_BFS_FS is not set
|
||||
# CONFIG_EFS_FS is not set
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_CRAMFS=m
|
||||
# CONFIG_VXFS_FS is not set
|
||||
# CONFIG_MINIX_FS is not set
|
||||
# CONFIG_OMFS_FS is not set
|
||||
|
||||
@@ -68,7 +68,7 @@
|
||||
_EMIT_BUG_ENTRY \
|
||||
: : "i" (__FILE__), "i" (__LINE__), \
|
||||
"i" (0), "i" (sizeof(struct bug_entry))); \
|
||||
for(;;) ; \
|
||||
unreachable(); \
|
||||
} while (0)
|
||||
|
||||
#define BUG_ON(x) do { \
|
||||
|
||||
@@ -38,12 +38,9 @@ static inline int gpio_cansleep(unsigned int gpio)
|
||||
return __gpio_cansleep(gpio);
|
||||
}
|
||||
|
||||
/*
|
||||
* Not implemented, yet.
|
||||
*/
|
||||
static inline int gpio_to_irq(unsigned int gpio)
|
||||
{
|
||||
return -ENOSYS;
|
||||
return __gpio_to_irq(gpio);
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned int irq)
|
||||
|
||||
@@ -642,10 +642,14 @@ static int emulate_spe(struct pt_regs *regs, unsigned int reg,
|
||||
*/
|
||||
static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
|
||||
unsigned int areg, struct pt_regs *regs,
|
||||
unsigned int flags, unsigned int length)
|
||||
unsigned int flags, unsigned int length,
|
||||
unsigned int elsize)
|
||||
{
|
||||
char *ptr;
|
||||
unsigned long *lptr;
|
||||
int ret = 0;
|
||||
int sw = 0;
|
||||
int i, j;
|
||||
|
||||
flush_vsx_to_thread(current);
|
||||
|
||||
@@ -654,19 +658,35 @@ static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
|
||||
else
|
||||
ptr = (char *) ¤t->thread.vr[reg - 32];
|
||||
|
||||
if (flags & ST)
|
||||
ret = __copy_to_user(addr, ptr, length);
|
||||
else {
|
||||
if (flags & SPLT){
|
||||
ret = __copy_from_user(ptr, addr, length);
|
||||
ptr += length;
|
||||
lptr = (unsigned long *) ptr;
|
||||
|
||||
if (flags & SW)
|
||||
sw = elsize-1;
|
||||
|
||||
for (j = 0; j < length; j += elsize) {
|
||||
for (i = 0; i < elsize; ++i) {
|
||||
if (flags & ST)
|
||||
ret |= __put_user(ptr[i^sw], addr + i);
|
||||
else
|
||||
ret |= __get_user(ptr[i^sw], addr + i);
|
||||
}
|
||||
ret |= __copy_from_user(ptr, addr, length);
|
||||
ptr += elsize;
|
||||
addr += elsize;
|
||||
}
|
||||
if (flags & U)
|
||||
regs->gpr[areg] = regs->dar;
|
||||
if (ret)
|
||||
|
||||
if (!ret) {
|
||||
if (flags & U)
|
||||
regs->gpr[areg] = regs->dar;
|
||||
|
||||
/* Splat load copies the same data to top and bottom 8 bytes */
|
||||
if (flags & SPLT)
|
||||
lptr[1] = lptr[0];
|
||||
/* For 8 byte loads, zero the top 8 bytes */
|
||||
else if (!(flags & ST) && (8 == length))
|
||||
lptr[1] = 0;
|
||||
} else
|
||||
return -EFAULT;
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
@@ -767,16 +787,25 @@ int fix_alignment(struct pt_regs *regs)
|
||||
|
||||
#ifdef CONFIG_VSX
|
||||
if ((instruction & 0xfc00003e) == 0x7c000018) {
|
||||
/* Additional register addressing bit (64 VSX vs 32 FPR/GPR */
|
||||
unsigned int elsize;
|
||||
|
||||
/* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
|
||||
reg |= (instruction & 0x1) << 5;
|
||||
/* Simple inline decoder instead of a table */
|
||||
/* VSX has only 8 and 16 byte memory accesses */
|
||||
nb = 8;
|
||||
if (instruction & 0x200)
|
||||
nb = 16;
|
||||
else if (instruction & 0x080)
|
||||
nb = 8;
|
||||
else
|
||||
nb = 4;
|
||||
|
||||
/* Vector stores in little-endian mode swap individual
|
||||
elements, so process them separately */
|
||||
elsize = 4;
|
||||
if (instruction & 0x80)
|
||||
elsize = 8;
|
||||
|
||||
flags = 0;
|
||||
if (regs->msr & MSR_LE)
|
||||
flags |= SW;
|
||||
if (instruction & 0x100)
|
||||
flags |= ST;
|
||||
if (instruction & 0x040)
|
||||
@@ -787,7 +816,7 @@ int fix_alignment(struct pt_regs *regs)
|
||||
nb = 8;
|
||||
}
|
||||
PPC_WARN_ALIGNMENT(vsx, regs);
|
||||
return emulate_vsx(addr, reg, areg, regs, flags, nb);
|
||||
return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
|
||||
}
|
||||
#endif
|
||||
/* A size of 0 indicates an instruction we don't support, with
|
||||
|
||||
@@ -340,7 +340,7 @@ static int __init htab_dt_scan_page_sizes(unsigned long node,
|
||||
else
|
||||
def->tlbiel = 0;
|
||||
|
||||
DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
|
||||
DBG(" %d: shift=%02x, sllp=%04lx, avpnm=%08lx, "
|
||||
"tlbiel=%d, penc=%d\n",
|
||||
idx, shift, def->sllp, def->avpnm, def->tlbiel,
|
||||
def->penc);
|
||||
@@ -663,7 +663,7 @@ static void __init htab_initialize(void)
|
||||
base = (unsigned long)__va(lmb.memory.region[i].base);
|
||||
size = lmb.memory.region[i].size;
|
||||
|
||||
DBG("creating mapping for region: %lx..%lx (prot: %x)\n",
|
||||
DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
|
||||
base, size, prot);
|
||||
|
||||
#ifdef CONFIG_U3_DART
|
||||
@@ -879,7 +879,7 @@ static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
|
||||
*/
|
||||
int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
|
||||
{
|
||||
void *pgdir;
|
||||
pgd_t *pgdir;
|
||||
unsigned long vsid;
|
||||
struct mm_struct *mm;
|
||||
pte_t *ptep;
|
||||
@@ -1025,7 +1025,7 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
|
||||
else
|
||||
#endif /* CONFIG_PPC_HAS_HASH_64K */
|
||||
{
|
||||
int spp = subpage_protection(pgdir, ea);
|
||||
int spp = subpage_protection(mm, ea);
|
||||
if (access & spp)
|
||||
rc = -2;
|
||||
else
|
||||
@@ -1115,7 +1115,7 @@ void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
|
||||
{
|
||||
unsigned long hash, index, shift, hidx, slot;
|
||||
|
||||
DBG_LOW("flush_hash_page(va=%016x)\n", va);
|
||||
DBG_LOW("flush_hash_page(va=%016lx)\n", va);
|
||||
pte_iterate_hashed_subpages(pte, psize, va, index, shift) {
|
||||
hash = hpt_hash(va, shift, ssize);
|
||||
hidx = __rpte_to_hidx(pte, index);
|
||||
@@ -1123,7 +1123,7 @@ void flush_hash_page(unsigned long va, real_pte_t pte, int psize, int ssize,
|
||||
hash = ~hash;
|
||||
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
|
||||
slot += hidx & _PTEIDX_GROUP_IX;
|
||||
DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index, slot, hidx);
|
||||
DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
|
||||
ppc_md.hpte_invalidate(slot, va, psize, ssize, local);
|
||||
} pte_iterate_hashed_end();
|
||||
}
|
||||
|
||||
@@ -353,7 +353,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
|
||||
read_lock(&tasklist_lock);
|
||||
for_each_process(p) {
|
||||
if (p->mm)
|
||||
cpu_mask_clear_cpu(cpu, mm_cpumask(p->mm));
|
||||
cpumask_clear_cpu(cpu, mm_cpumask(p->mm));
|
||||
}
|
||||
read_unlock(&tasklist_lock);
|
||||
break;
|
||||
|
||||
@@ -382,7 +382,7 @@ static int __change_page_attr(struct page *page, pgprot_t prot)
|
||||
return 0;
|
||||
if (!get_pteptr(&init_mm, address, &kpte, &kpmd))
|
||||
return -EINVAL;
|
||||
set_pte_at(&init_mm, address, kpte, mk_pte(page, prot));
|
||||
__set_pte_at(&init_mm, address, kpte, mk_pte(page, prot), 0);
|
||||
wmb();
|
||||
#ifdef CONFIG_PPC_STD_MMU
|
||||
flush_hash_pages(0, address, pmd_val(*kpmd), 1);
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
#define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
|
||||
#define PMCCR1_NEXT_STATE_SHIFT 2
|
||||
#define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
|
||||
#define IMMR_SYSCR_OFFSET 0x100
|
||||
#define IMMR_RCW_OFFSET 0x900
|
||||
#define RCW_PCI_HOST 0x80000000
|
||||
|
||||
@@ -78,6 +79,22 @@ struct mpc83xx_clock {
|
||||
u32 sccr;
|
||||
};
|
||||
|
||||
struct mpc83xx_syscr {
|
||||
__be32 sgprl;
|
||||
__be32 sgprh;
|
||||
__be32 spridr;
|
||||
__be32 :32;
|
||||
__be32 spcr;
|
||||
__be32 sicrl;
|
||||
__be32 sicrh;
|
||||
};
|
||||
|
||||
struct mpc83xx_saved {
|
||||
u32 sicrl;
|
||||
u32 sicrh;
|
||||
u32 sccr;
|
||||
};
|
||||
|
||||
struct pmc_type {
|
||||
int has_deep_sleep;
|
||||
};
|
||||
@@ -87,6 +104,8 @@ static int has_deep_sleep, deep_sleeping;
|
||||
static int pmc_irq;
|
||||
static struct mpc83xx_pmc __iomem *pmc_regs;
|
||||
static struct mpc83xx_clock __iomem *clock_regs;
|
||||
static struct mpc83xx_syscr __iomem *syscr_regs;
|
||||
static struct mpc83xx_saved saved_regs;
|
||||
static int is_pci_agent, wake_from_pci;
|
||||
static phys_addr_t immrbase;
|
||||
static int pci_pm_state;
|
||||
@@ -137,6 +156,20 @@ static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mpc83xx_suspend_restore_regs(void)
|
||||
{
|
||||
out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
|
||||
out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
|
||||
out_be32(&clock_regs->sccr, saved_regs.sccr);
|
||||
}
|
||||
|
||||
static void mpc83xx_suspend_save_regs(void)
|
||||
{
|
||||
saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
|
||||
saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
|
||||
saved_regs.sccr = in_be32(&clock_regs->sccr);
|
||||
}
|
||||
|
||||
static int mpc83xx_suspend_enter(suspend_state_t state)
|
||||
{
|
||||
int ret = -EAGAIN;
|
||||
@@ -166,6 +199,8 @@ static int mpc83xx_suspend_enter(suspend_state_t state)
|
||||
*/
|
||||
|
||||
if (deep_sleeping) {
|
||||
mpc83xx_suspend_save_regs();
|
||||
|
||||
out_be32(&pmc_regs->mask, PMCER_ALL);
|
||||
|
||||
out_be32(&pmc_regs->config1,
|
||||
@@ -179,6 +214,8 @@ static int mpc83xx_suspend_enter(suspend_state_t state)
|
||||
in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
|
||||
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
|
||||
mpc83xx_suspend_restore_regs();
|
||||
} else {
|
||||
out_be32(&pmc_regs->mask, PMCER_PMCI);
|
||||
|
||||
@@ -194,7 +231,7 @@ out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mpc83xx_suspend_finish(void)
|
||||
static void mpc83xx_suspend_end(void)
|
||||
{
|
||||
deep_sleeping = 0;
|
||||
}
|
||||
@@ -278,7 +315,7 @@ static struct platform_suspend_ops mpc83xx_suspend_ops = {
|
||||
.valid = mpc83xx_suspend_valid,
|
||||
.begin = mpc83xx_suspend_begin,
|
||||
.enter = mpc83xx_suspend_enter,
|
||||
.finish = mpc83xx_suspend_finish,
|
||||
.end = mpc83xx_suspend_end,
|
||||
};
|
||||
|
||||
static int pmc_probe(struct of_device *ofdev,
|
||||
@@ -333,12 +370,23 @@ static int pmc_probe(struct of_device *ofdev,
|
||||
goto out_pmc;
|
||||
}
|
||||
|
||||
if (has_deep_sleep) {
|
||||
syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
|
||||
sizeof(*syscr_regs));
|
||||
if (!syscr_regs) {
|
||||
ret = -ENOMEM;
|
||||
goto out_syscr;
|
||||
}
|
||||
}
|
||||
|
||||
if (is_pci_agent)
|
||||
mpc83xx_set_agent();
|
||||
|
||||
suspend_set_ops(&mpc83xx_suspend_ops);
|
||||
return 0;
|
||||
|
||||
out_syscr:
|
||||
iounmap(clock_regs);
|
||||
out_pmc:
|
||||
iounmap(pmc_regs);
|
||||
out:
|
||||
|
||||
@@ -86,7 +86,7 @@ static int mpc8568_fixup_125_clock(struct phy_device *phydev)
|
||||
scr = phy_read(phydev, MV88E1111_SCR);
|
||||
|
||||
if (scr < 0)
|
||||
return err;
|
||||
return scr;
|
||||
|
||||
err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
|
||||
|
||||
|
||||
@@ -102,7 +102,7 @@ static int flipper_pic_map(struct irq_host *h, unsigned int virq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
set_irq_chip_data(virq, h->host_data);
|
||||
get_irq_desc(virq)->status |= IRQ_LEVEL;
|
||||
irq_to_desc(virq)->status |= IRQ_LEVEL;
|
||||
set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
|
||||
return 0;
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user