mirror of
https://github.com/armbian/linux.git
synced 2026-01-06 10:13:00 -08:00
add rk29 sdio mmc
This commit is contained in:
lhh
@@ -720,7 +720,34 @@ CONFIG_DUMMY_CONSOLE=y
|
||||
# CONFIG_SOUND is not set
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_DEBUG=y
|
||||
# CONFIG_MMC_UNSAFE_RESUME is not set
|
||||
# CONFIG_MMC_EMBEDDED_SDIO is not set
|
||||
# CONFIG_MMC_PARANOID_SD_INIT is not set
|
||||
|
||||
#
|
||||
# MMC/SD/SDIO Card Drivers
|
||||
#
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_BOUNCE=y
|
||||
# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set
|
||||
# CONFIG_SDIO_UART is not set
|
||||
# CONFIG_MMC_TEST is not set
|
||||
|
||||
#
|
||||
# MMC/SD/SDIO Host Controller Drivers
|
||||
#
|
||||
CONFIG_SDMMC_RK29=y
|
||||
|
||||
#
|
||||
# Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1.
|
||||
#
|
||||
CONFIG_SDMMC0_RK29=y
|
||||
CONFIG_SDMMC1_RK29=y
|
||||
# CONFIG_MMC_SDHCI is not set
|
||||
# CONFIG_MMC_AT91 is not set
|
||||
# CONFIG_MMC_ATMELMCI is not set
|
||||
# CONFIG_MEMSTICK is not set
|
||||
# CONFIG_NEW_LEDS is not set
|
||||
# CONFIG_SWITCH is not set
|
||||
|
||||
@@ -288,10 +288,107 @@ struct rk29fb_info rk29_fb_info = {
|
||||
};
|
||||
|
||||
|
||||
/*****************************************************************************************
|
||||
* SDMMC devices
|
||||
*****************************************************************************************/
|
||||
#ifdef CONFIG_SDMMC0_RK29
|
||||
void rk29_sdmmc0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
|
||||
rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
|
||||
rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
|
||||
rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
|
||||
rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
|
||||
rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
|
||||
rk29_mux_api_set(GPIO2A2_SDMMC0DETECTN_NAME, GPIO2L_SDMMC0_DETECT_N);
|
||||
}
|
||||
|
||||
#define CONFIG_SDMMC0_USE_DMA
|
||||
struct rk29_sdmmc_platform_data default_sdmmc0_data = {
|
||||
.num_slots = 1,
|
||||
.host_ocr_avail = (MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30|
|
||||
MMC_VDD_30_31|MMC_VDD_31_32|MMC_VDD_32_33|
|
||||
MMC_VDD_33_34|MMC_VDD_34_35| MMC_VDD_35_36),
|
||||
.host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
|
||||
.io_init = rk29_sdmmc0_cfg_gpio,
|
||||
.dma_name = "sd_mmc",
|
||||
#ifdef CONFIG_SDMMC0_USE_DMA
|
||||
.use_dma = 1,
|
||||
#else
|
||||
.use_dma = 0,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_SDMMC1_RK29
|
||||
#define CONFIG_SDMMC1_USE_DMA
|
||||
void rk29_sdmmc1_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
|
||||
rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
|
||||
rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
|
||||
rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
|
||||
rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
|
||||
rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
|
||||
}
|
||||
|
||||
struct rk29_sdmmc_platform_data default_sdmmc1_data = {
|
||||
.num_slots = 1,
|
||||
.host_ocr_avail = (MMC_VDD_26_27|MMC_VDD_27_28|MMC_VDD_28_29|
|
||||
MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32|
|
||||
MMC_VDD_32_33|MMC_VDD_33_34),
|
||||
.host_caps = (MMC_CAP_4_BIT_DATA|MMC_CAP_SDIO_IRQ|
|
||||
MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
|
||||
.io_init = rk29_sdmmc1_cfg_gpio,
|
||||
.dma_name = "sdio",
|
||||
#ifdef CONFIG_SDMMC1_USE_DMA
|
||||
.use_dma = 1,
|
||||
#else
|
||||
.use_dma = 0,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
static void __init rk29_board_iomux_init(void)
|
||||
{
|
||||
#ifdef CONFIG_UART0_RK29
|
||||
rk29_mux_api_set(GPIO1B7_UART0SOUT_NAME, GPIO1L_UART0_SOUT);
|
||||
rk29_mux_api_set(GPIO1B6_UART0SIN_NAME, GPIO1L_UART0_SIN);
|
||||
#ifdef CONFIG_UART0_CTS_RTS_RK29
|
||||
rk29_mux_api_set(GPIO1C1_UART0RTSN_SDMMC1WRITEPRT_NAME, GPIO1H_UART0_RTS_N);
|
||||
rk29_mux_api_set(GPIO1C0_UART0CTSN_SDMMC1DETECTN_NAME, GPIO1H_UART0_CTS_N);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_UART1_RK29
|
||||
rk29_mux_api_set(GPIO2A5_UART1SOUT_NAME, GPIO2L_UART1_SOUT);
|
||||
rk29_mux_api_set(GPIO2A4_UART1SIN_NAME, GPIO2L_UART1_SIN);
|
||||
#endif
|
||||
#ifdef CONFIG_UART2_RK29
|
||||
rk29_mux_api_set(GPIO2B1_UART2SOUT_NAME, GPIO2L_UART2_SOUT);
|
||||
rk29_mux_api_set(GPIO2B0_UART2SIN_NAME, GPIO2L_UART2_SIN);
|
||||
#ifdef CONFIG_UART2_CTS_RTS_RK29
|
||||
rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
|
||||
rk29_mux_api_set(GPIO2A6_UART2CTSN_NAME, GPIO2L_UART2_CTS_N);
|
||||
#endif
|
||||
#endif
|
||||
#ifdef CONFIG_UART3_RK29
|
||||
rk29_mux_api_set(GPIO2B3_UART3SOUT_NAME, GPIO2L_UART3_SOUT);
|
||||
rk29_mux_api_set(GPIO2B2_UART3SIN_NAME, GPIO2L_UART3_SIN);
|
||||
#ifdef CONFIG_UART3_CTS_RTS_RK29
|
||||
rk29_mux_api_set(GPIO2B5_UART3RTSN_I2C3SCL_NAME, GPIO2L_UART3_RTS_N);
|
||||
rk29_mux_api_set(GPIO2B4_UART3CTSN_I2C3SDA_NAME, GPIO2L_UART3_CTS_N);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
#ifdef CONFIG_UART1_RK29
|
||||
&rk29_device_uart1,
|
||||
#endif
|
||||
#ifdef CONFIG_SDMMC0_RK29
|
||||
&rk29_device_sdmmc0,
|
||||
#endif
|
||||
#ifdef CONFIG_SDMMC1_RK29
|
||||
&rk29_device_sdmmc1,
|
||||
#endif
|
||||
#ifdef CONFIG_MTD_NAND_RK29
|
||||
&rk29_device_nand,
|
||||
#endif
|
||||
@@ -321,6 +418,7 @@ static void __init machine_rk29_init_irq(void)
|
||||
static void __init machine_rk29_board_init(void)
|
||||
{
|
||||
platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
rk29_board_iomux_init();
|
||||
}
|
||||
|
||||
static void __init machine_rk29_mapio(void)
|
||||
|
||||
@@ -19,9 +19,59 @@
|
||||
#include <linux/delay.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/rk29_iomap.h>
|
||||
|
||||
#include "devices.h"
|
||||
|
||||
#include "devices.h"
|
||||
|
||||
#ifdef CONFIG_SDMMC0_RK29
|
||||
static struct resource resources_sdmmc0[] = {
|
||||
{
|
||||
.start = IRQ_SDMMC,
|
||||
.end = IRQ_SDMMC,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = RK29_SDMMC0_PHYS,
|
||||
.end = RK29_SDMMC0_PHYS + RK29_SDMMC0_SIZE -1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_SDMMC1_RK29
|
||||
static struct resource resources_sdmmc1[] = {
|
||||
{
|
||||
.start = IRQ_SDIO,
|
||||
.end = IRQ_SDIO,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
.start = RK29_SDMMC1_PHYS,
|
||||
.end = RK29_SDMMC1_PHYS + RK29_SDMMC1_SIZE -1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
}
|
||||
};
|
||||
#endif
|
||||
/* sdmmc */
|
||||
#ifdef CONFIG_SDMMC0_RK29
|
||||
struct platform_device rk29_device_sdmmc0 = {
|
||||
.name = "rk29_sdmmc",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(resources_sdmmc0),
|
||||
.resource = resources_sdmmc0,
|
||||
.dev = {
|
||||
.platform_data = &default_sdmmc0_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#ifdef CONFIG_SDMMC1_RK29
|
||||
struct platform_device rk29_device_sdmmc1 = {
|
||||
.name = "rk29_sdmmc",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(resources_sdmmc1),
|
||||
.resource = resources_sdmmc1,
|
||||
.dev = {
|
||||
.platform_data = &default_sdmmc1_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
/*
|
||||
* rk29 4 uarts device
|
||||
*/
|
||||
@@ -34,7 +84,7 @@ static struct resource resources_uart0[] = {
|
||||
},
|
||||
{
|
||||
.start = RK29_UART0_PHYS,
|
||||
.end = RK29_UART0_PHYS + SZ_1K - 1,
|
||||
.end = RK29_UART0_PHYS + RK29_UART0_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
@@ -48,7 +98,7 @@ static struct resource resources_uart1[] = {
|
||||
},
|
||||
{
|
||||
.start = RK29_UART1_PHYS,
|
||||
.end = RK29_UART1_PHYS + SZ_1K - 1,
|
||||
.end = RK29_UART1_PHYS + RK29_UART1_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
@@ -62,7 +112,7 @@ static struct resource resources_uart2[] = {
|
||||
},
|
||||
{
|
||||
.start = RK29_UART2_PHYS,
|
||||
.end = RK29_UART2_PHYS + SZ_1K - 1,
|
||||
.end = RK29_UART2_PHYS + RK29_UART2_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
@@ -76,7 +126,7 @@ static struct resource resources_uart3[] = {
|
||||
},
|
||||
{
|
||||
.start = RK29_UART3_PHYS,
|
||||
.end = RK29_UART3_PHYS + SZ_1K - 1,
|
||||
.end = RK29_UART3_PHYS + RK29_UART3_SIZE - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -25,5 +25,9 @@ extern struct platform_device rk29_device_uart3;
|
||||
extern struct platform_device rk29_device_gpu;
|
||||
extern struct platform_device rk29_device_fb;
|
||||
extern struct platform_device rk29_device_nand;
|
||||
extern struct rk29_sdmmc_platform_data default_sdmmc0_data;
|
||||
extern struct rk29_sdmmc_platform_data default_sdmmc1_data;
|
||||
extern struct platform_device rk29_device_sdmmc0;
|
||||
extern struct platform_device rk29_device_sdmmc1;
|
||||
|
||||
#endif
|
||||
@@ -500,7 +500,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
|
||||
unsigned char __iomem *gpioRegBase;
|
||||
u32 isr;
|
||||
|
||||
rk29_gpio = get_irq_chip_data(irq);
|
||||
rk29_gpio = get_irq_chip_data(irq+14);
|
||||
gpioRegBase = rk29_gpio->regbase;
|
||||
|
||||
//屏蔽中断6或7
|
||||
@@ -602,6 +602,7 @@ void __init rk29_gpio_irq_setup(void)
|
||||
irq = IRQ_GPIO6;
|
||||
break;
|
||||
}
|
||||
set_irq_chip_data(NR_AIC_IRQS+this->bank->id,this);
|
||||
set_irq_chained_handler(irq, gpio_irq_handler);
|
||||
this += 1;
|
||||
pin += 32;
|
||||
|
||||
@@ -49,6 +49,18 @@ struct rk29fb_info{
|
||||
int (*io_deinit)(void);
|
||||
};
|
||||
|
||||
struct rk29_sdmmc_platform_data {
|
||||
unsigned int num_slots;
|
||||
unsigned int host_caps;
|
||||
unsigned int host_ocr_avail;
|
||||
unsigned int use_dma:1;
|
||||
char dma_name[8];
|
||||
int (*io_init)(void);
|
||||
int (*io_deinit)(void);
|
||||
int (*status)(struct device *);
|
||||
int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
|
||||
};
|
||||
|
||||
void __init rk29_map_common_io(void);
|
||||
void __init rk29_clock_init(void);
|
||||
|
||||
|
||||
@@ -14,7 +14,8 @@
|
||||
*/
|
||||
#ifndef __ARCH_ARM_MACH_RK29_GPIO_H
|
||||
#define __ARCH_ARM_MACH_RK29_GPIO_H
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
typedef enum eGPIOPinLevel
|
||||
{
|
||||
GPIO_LOW=0,
|
||||
@@ -60,236 +61,236 @@ typedef enum GPIOIntType {
|
||||
#define PIN_BASE 0
|
||||
#define MAX_BANK 7
|
||||
|
||||
#define RK29_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN0_PA0 (0*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN0_PA1 (0*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN0_PA2 (0*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN0_PA3 (0*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN0_PA4 (0*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN0_PA5 (0*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN0_PA6 (0*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN0_PA7 (0*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN0_PB0 (0*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN0_PB1 (0*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN0_PB2 (0*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN0_PB3 (0*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN0_PB4 (0*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN0_PB5 (0*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN0_PB6 (0*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN0_PB7 (0*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN0_PC0 (0*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN0_PC1 (0*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN0_PC2 (0*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN0_PC3 (0*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN0_PC4 (0*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN0_PC5 (0*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN0_PC6 (0*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN0_PC7 (0*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN0_PD0 (0*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN0_PD1 (0*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN0_PD2 (0*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN0_PD3 (0*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN0_PD4 (0*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN0_PD5 (0*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN0_PD6 (0*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN0_PD7 (0*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define RK29_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN1_PA0 (1*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN1_PA1 (1*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN1_PA2 (1*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN1_PA3 (1*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN1_PA4 (1*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN1_PA5 (1*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN1_PA6 (1*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN1_PA7 (1*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN1_PB0 (1*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN1_PB1 (1*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN1_PB2 (1*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN1_PB3 (1*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN1_PB4 (1*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN1_PB5 (1*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN1_PB6 (1*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN1_PB7 (1*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN1_PC0 (1*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN1_PC1 (1*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN1_PC2 (1*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN1_PC3 (1*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN1_PC4 (1*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN1_PC5 (1*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN1_PC6 (1*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN1_PC7 (1*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN1_PD0 (1*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN1_PD1 (1*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN1_PD2 (1*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN1_PD3 (1*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN1_PD4 (1*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN1_PD5 (1*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN1_PD6 (1*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN1_PD7 (1*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define RK29_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN2_PA0 (2*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN2_PA1 (2*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN2_PA2 (2*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN2_PA3 (2*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN2_PA4 (2*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN2_PA5 (2*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN2_PA6 (2*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN2_PA7 (2*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN2_PB0 (2*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN2_PB1 (2*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN2_PB2 (2*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN2_PB3 (2*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN2_PB4 (2*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN2_PB5 (2*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN2_PB6 (2*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN2_PB7 (2*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN2_PC0 (2*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN2_PC1 (2*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN2_PC2 (2*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN2_PC3 (2*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN2_PC4 (2*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN2_PC5 (2*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN2_PC6 (2*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN2_PC7 (2*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN2_PD0 (2*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN2_PD1 (2*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN2_PD2 (2*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN2_PD3 (2*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN2_PD4 (2*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN2_PD5 (2*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN2_PD6 (2*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN2_PD7 (2*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define RK29_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN3_PA0 (3*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN3_PA1 (3*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN3_PA2 (3*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN3_PA3 (3*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN3_PA4 (3*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN3_PA5 (3*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN3_PA6 (3*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN3_PA7 (3*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN3_PB0 (3*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN3_PB1 (3*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN3_PB2 (3*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN3_PB3 (3*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN3_PB4 (3*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN3_PB5 (3*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN3_PB6 (3*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN3_PB7 (3*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN3_PC0 (3*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN3_PC1 (3*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN3_PC2 (3*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN3_PC3 (3*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN3_PC4 (3*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN3_PC5 (3*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN3_PC6 (3*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN3_PC7 (3*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN3_PD0 (3*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN3_PD1 (3*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN3_PD2 (3*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN3_PD3 (3*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN3_PD4 (3*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN3_PD5 (3*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN3_PD6 (3*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN3_PD7 (3*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define RK29_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN4_PA0 (4*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN4_PA1 (4*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN4_PA2 (4*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN4_PA3 (4*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN4_PA4 (4*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN4_PA5 (4*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN4_PA6 (4*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN4_PA7 (4*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN4_PB0 (4*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN4_PB1 (4*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN4_PB2 (4*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN4_PB3 (4*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN4_PB4 (4*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN4_PB5 (4*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN4_PB6 (4*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN4_PB7 (4*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN4_PC0 (4*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN4_PC1 (4*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN4_PC2 (4*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN4_PC3 (4*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN4_PC4 (4*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN4_PC5 (4*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN4_PC6 (4*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN4_PC7 (4*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN4_PD0 (4*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN4_PD1 (4*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN4_PD2 (4*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN4_PD3 (4*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN4_PD4 (4*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN4_PD5 (4*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN4_PD6 (4*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN4_PD7 (4*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define RK29_PIN5_PA0 (5*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN5_PA1 (5*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN5_PA2 (5*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN5_PA3 (5*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN5_PA4 (5*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN5_PA5 (5*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN5_PA6 (5*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN5_PA7 (5*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN5_PB0 (5*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN5_PB1 (5*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN5_PB2 (5*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN5_PB3 (5*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN5_PB4 (5*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN5_PB5 (5*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN5_PB6 (5*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN5_PB7 (5*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN5_PC0 (5*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN5_PC1 (5*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN5_PC2 (5*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN5_PC3 (5*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN5_PC4 (5*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN5_PC5 (5*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN5_PC6 (5*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN5_PC7 (5*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN5_PD0 (5*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN5_PD1 (5*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN5_PD2 (5*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN5_PD3 (5*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN5_PD4 (5*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN5_PD5 (5*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN5_PD6 (5*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN5_PD7 (5*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN5_PA0 (5*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN5_PA1 (5*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN5_PA2 (5*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN5_PA3 (5*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN5_PA4 (5*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN5_PA5 (5*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN5_PA6 (5*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN5_PA7 (5*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN5_PB0 (5*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN5_PB1 (5*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN5_PB2 (5*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN5_PB3 (5*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN5_PB4 (5*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN5_PB5 (5*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN5_PB6 (5*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN5_PB7 (5*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN5_PC0 (5*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN5_PC1 (5*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN5_PC2 (5*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN5_PC3 (5*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN5_PC4 (5*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN5_PC5 (5*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN5_PC6 (5*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN5_PC7 (5*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN5_PD0 (5*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN5_PD1 (5*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN5_PD2 (5*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN5_PD3 (5*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN5_PD4 (5*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN5_PD5 (5*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN5_PD6 (5*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN5_PD7 (5*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define RK29_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0);
|
||||
#define RK29_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1);
|
||||
#define RK29_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2);
|
||||
#define RK29_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3);
|
||||
#define RK29_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4);
|
||||
#define RK29_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5);
|
||||
#define RK29_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6);
|
||||
#define RK29_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7);
|
||||
#define RK29_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8);
|
||||
#define RK29_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9);
|
||||
#define RK29_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10);
|
||||
#define RK29_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11);
|
||||
#define RK29_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12);
|
||||
#define RK29_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13);
|
||||
#define RK29_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14);
|
||||
#define RK29_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15);
|
||||
#define RK29_PIN6_PC0 (6*NUM_GROUP + PIN_BASE + 16);
|
||||
#define RK29_PIN6_PC1 (6*NUM_GROUP + PIN_BASE + 17);
|
||||
#define RK29_PIN6_PC2 (6*NUM_GROUP + PIN_BASE + 18);
|
||||
#define RK29_PIN6_PC3 (6*NUM_GROUP + PIN_BASE + 19);
|
||||
#define RK29_PIN6_PC4 (6*NUM_GROUP + PIN_BASE + 20);
|
||||
#define RK29_PIN6_PC5 (6*NUM_GROUP + PIN_BASE + 21);
|
||||
#define RK29_PIN6_PC6 (6*NUM_GROUP + PIN_BASE + 22);
|
||||
#define RK29_PIN6_PC7 (6*NUM_GROUP + PIN_BASE + 23);
|
||||
#define RK29_PIN6_PD0 (6*NUM_GROUP + PIN_BASE + 24);
|
||||
#define RK29_PIN6_PD1 (6*NUM_GROUP + PIN_BASE + 25);
|
||||
#define RK29_PIN6_PD2 (6*NUM_GROUP + PIN_BASE + 26);
|
||||
#define RK29_PIN6_PD3 (6*NUM_GROUP + PIN_BASE + 27);
|
||||
#define RK29_PIN6_PD4 (6*NUM_GROUP + PIN_BASE + 28);
|
||||
#define RK29_PIN6_PD5 (6*NUM_GROUP + PIN_BASE + 29);
|
||||
#define RK29_PIN6_PD6 (6*NUM_GROUP + PIN_BASE + 30);
|
||||
#define RK29_PIN6_PD7 (6*NUM_GROUP + PIN_BASE + 31);
|
||||
#define RK29_PIN6_PA0 (6*NUM_GROUP + PIN_BASE + 0)
|
||||
#define RK29_PIN6_PA1 (6*NUM_GROUP + PIN_BASE + 1)
|
||||
#define RK29_PIN6_PA2 (6*NUM_GROUP + PIN_BASE + 2)
|
||||
#define RK29_PIN6_PA3 (6*NUM_GROUP + PIN_BASE + 3)
|
||||
#define RK29_PIN6_PA4 (6*NUM_GROUP + PIN_BASE + 4)
|
||||
#define RK29_PIN6_PA5 (6*NUM_GROUP + PIN_BASE + 5)
|
||||
#define RK29_PIN6_PA6 (6*NUM_GROUP + PIN_BASE + 6)
|
||||
#define RK29_PIN6_PA7 (6*NUM_GROUP + PIN_BASE + 7)
|
||||
#define RK29_PIN6_PB0 (6*NUM_GROUP + PIN_BASE + 8)
|
||||
#define RK29_PIN6_PB1 (6*NUM_GROUP + PIN_BASE + 9)
|
||||
#define RK29_PIN6_PB2 (6*NUM_GROUP + PIN_BASE + 10)
|
||||
#define RK29_PIN6_PB3 (6*NUM_GROUP + PIN_BASE + 11)
|
||||
#define RK29_PIN6_PB4 (6*NUM_GROUP + PIN_BASE + 12)
|
||||
#define RK29_PIN6_PB5 (6*NUM_GROUP + PIN_BASE + 13)
|
||||
#define RK29_PIN6_PB6 (6*NUM_GROUP + PIN_BASE + 14)
|
||||
#define RK29_PIN6_PB7 (6*NUM_GROUP + PIN_BASE + 15)
|
||||
#define RK29_PIN6_PC0 (6*NUM_GROUP + PIN_BASE + 16)
|
||||
#define RK29_PIN6_PC1 (6*NUM_GROUP + PIN_BASE + 17)
|
||||
#define RK29_PIN6_PC2 (6*NUM_GROUP + PIN_BASE + 18)
|
||||
#define RK29_PIN6_PC3 (6*NUM_GROUP + PIN_BASE + 19)
|
||||
#define RK29_PIN6_PC4 (6*NUM_GROUP + PIN_BASE + 20)
|
||||
#define RK29_PIN6_PC5 (6*NUM_GROUP + PIN_BASE + 21)
|
||||
#define RK29_PIN6_PC6 (6*NUM_GROUP + PIN_BASE + 22)
|
||||
#define RK29_PIN6_PC7 (6*NUM_GROUP + PIN_BASE + 23)
|
||||
#define RK29_PIN6_PD0 (6*NUM_GROUP + PIN_BASE + 24)
|
||||
#define RK29_PIN6_PD1 (6*NUM_GROUP + PIN_BASE + 25)
|
||||
#define RK29_PIN6_PD2 (6*NUM_GROUP + PIN_BASE + 26)
|
||||
#define RK29_PIN6_PD3 (6*NUM_GROUP + PIN_BASE + 27)
|
||||
#define RK29_PIN6_PD4 (6*NUM_GROUP + PIN_BASE + 28)
|
||||
#define RK29_PIN6_PD5 (6*NUM_GROUP + PIN_BASE + 29)
|
||||
#define RK29_PIN6_PD6 (6*NUM_GROUP + PIN_BASE + 30)
|
||||
#define RK29_PIN6_PD7 (6*NUM_GROUP + PIN_BASE + 31)
|
||||
|
||||
#define ARCH_NR_GPIOS (NUM_GROUP*MAX_BANK)
|
||||
|
||||
@@ -317,12 +318,12 @@ extern void __init rk29_gpio_irq_setup(void);
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
{
|
||||
return gpio;
|
||||
return (gpio + NR_AIC_IRQS);
|
||||
}
|
||||
|
||||
static inline int irq_to_gpio(unsigned irq)
|
||||
{
|
||||
return irq;
|
||||
return (irq - NR_AIC_IRQS);
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@@ -235,11 +235,9 @@ static u32 get_card_status(struct mmc_card *card, struct request *req)
|
||||
cmd.arg = card->rca << 16;
|
||||
cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
|
||||
err = mmc_wait_for_cmd(card->host, &cmd, 0);
|
||||
#if 0 //[xjh] not printk,save time
|
||||
if (err)
|
||||
printk(KERN_ERR "%s: error %d sending status comand",
|
||||
req->rq_disk->disk_name, err);
|
||||
#endif
|
||||
return cmd.resp[0];
|
||||
}
|
||||
|
||||
@@ -378,9 +376,7 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
|
||||
* until later as we need to wait for the card to leave
|
||||
* programming mode even when things go wrong.
|
||||
*/
|
||||
#if 1/*[xjh] do not retry with cmd17*/
|
||||
if (brq.cmd.error || brq.data.error || brq.stop.error) {
|
||||
|
||||
if (brq.data.blocks > 1 && rq_data_dir(req) == READ) {
|
||||
/* Redo read one sector at a time */
|
||||
printk(KERN_WARNING "%s: retrying using single "
|
||||
@@ -388,14 +384,11 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
|
||||
disable_multi = 1;
|
||||
continue;
|
||||
}
|
||||
|
||||
status = get_card_status(card, req);
|
||||
} else if (disable_multi == 1) {
|
||||
disable_multi = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0 //[xjh] not printk,save time
|
||||
if (brq.cmd.error) {
|
||||
printk(KERN_ERR "%s: error %d sending read/write "
|
||||
"command, response %#x, card status %#x\n",
|
||||
@@ -420,7 +413,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
|
||||
req->rq_disk->disk_name, brq.stop.error,
|
||||
brq.stop.resp[0], status);
|
||||
}
|
||||
#endif
|
||||
|
||||
if (!mmc_host_is_spi(card->host) && rq_data_dir(req) != READ) {
|
||||
do {
|
||||
@@ -453,7 +445,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
|
||||
}
|
||||
|
||||
if (brq.cmd.error || brq.stop.error || brq.data.error) {
|
||||
#if 1/*[xjh] do not retry with cmd17*/
|
||||
if (rq_data_dir(req) == READ) {
|
||||
/*
|
||||
* After an error, we redo I/O one sector at a
|
||||
@@ -465,7 +456,6 @@ static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
|
||||
spin_unlock_irq(&md->lock);
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
goto cmd_err;
|
||||
}
|
||||
|
||||
|
||||
@@ -268,7 +268,6 @@ int mmc_add_card(struct mmc_card *card)
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern int sdmmc0_disable_Irq_ForRemoval;
|
||||
/*
|
||||
* Unregister a new MMC card with the driver model, and
|
||||
* (eventually) free it.
|
||||
@@ -278,7 +277,6 @@ void mmc_remove_card(struct mmc_card *card)
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
mmc_remove_card_debugfs(card);
|
||||
#endif
|
||||
unsigned long flags;
|
||||
|
||||
if (mmc_card_present(card)) {
|
||||
if (mmc_host_is_spi(card->host)) {
|
||||
@@ -288,13 +286,6 @@ void mmc_remove_card(struct mmc_card *card)
|
||||
printk(KERN_INFO "%s: card %04x removed\n",
|
||||
mmc_hostname(card->host), card->rca);
|
||||
}
|
||||
|
||||
if( !strncmp( mmc_hostname(card->host) ,"mmc0" , strlen("mmc0")) )
|
||||
{
|
||||
local_irq_save(flags);
|
||||
sdmmc0_disable_Irq_ForRemoval = 1; //close the IRQ for insertion or removal
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
device_del(&card->dev);
|
||||
}
|
||||
|
||||
|
||||
@@ -1059,7 +1059,7 @@ void mmc_detect_change(struct mmc_host *host, unsigned long delay)
|
||||
|
||||
EXPORT_SYMBOL(mmc_detect_change);
|
||||
|
||||
#if 0
|
||||
|
||||
void mmc_rescan(struct work_struct *work)
|
||||
{
|
||||
struct mmc_host *host =
|
||||
@@ -1154,102 +1154,6 @@ out:
|
||||
if (host->caps & MMC_CAP_NEEDS_POLL)
|
||||
mmc_schedule_delayed_work(&host->detect, HZ);
|
||||
}
|
||||
#else
|
||||
void mmc_rescan(struct work_struct *work)
|
||||
{
|
||||
struct mmc_host *host =
|
||||
container_of(work, struct mmc_host, detect.work);
|
||||
u32 ocr;
|
||||
int err;
|
||||
int extend_wakelock = 0;
|
||||
|
||||
mmc_bus_get(host);
|
||||
if(host->bus_ops == NULL)
|
||||
{
|
||||
/* detect a newly inserted card */
|
||||
|
||||
/*
|
||||
* Only we can add a new handler, so it's safe to
|
||||
* release the lock here.
|
||||
*/
|
||||
mmc_bus_put(host);
|
||||
|
||||
if (host->ops->get_cd && host->ops->get_cd(host) == 0)
|
||||
goto out;
|
||||
|
||||
mmc_claim_host(host);
|
||||
|
||||
mmc_power_up(host);
|
||||
mmc_go_idle(host);
|
||||
|
||||
mmc_send_if_cond(host, host->ocr_avail);
|
||||
|
||||
/*
|
||||
* First we search for SDIO...
|
||||
*/
|
||||
err = mmc_send_io_op_cond(host, 0, &ocr);
|
||||
if (!err) {
|
||||
if (mmc_attach_sdio(host, ocr))
|
||||
mmc_power_off(host);
|
||||
extend_wakelock = 1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* ...then normal SD...
|
||||
*/
|
||||
err = mmc_send_app_op_cond(host, 0, &ocr);
|
||||
if (!err) {
|
||||
if (mmc_attach_sd(host, ocr))
|
||||
mmc_power_off(host);
|
||||
extend_wakelock = 1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* ...and finally MMC.
|
||||
*/
|
||||
err = mmc_send_op_cond(host, 0, &ocr);
|
||||
if (!err) {
|
||||
if (mmc_attach_mmc(host, ocr))
|
||||
mmc_power_off(host);
|
||||
extend_wakelock = 1;
|
||||
goto out;
|
||||
}
|
||||
|
||||
mmc_release_host(host);
|
||||
mmc_power_off(host);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* if there is a card registered, check whether it is still present */
|
||||
if ((host->bus_ops != NULL) && host->bus_ops->detect && !host->bus_dead)
|
||||
host->bus_ops->detect(host);
|
||||
|
||||
/* If the card was removed the bus will be marked
|
||||
* as dead - extend the wakelock so userspace
|
||||
* can respond */
|
||||
if (host->bus_dead)
|
||||
extend_wakelock = 1;
|
||||
|
||||
mmc_bus_put(host);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
out:
|
||||
if (extend_wakelock)
|
||||
wake_lock_timeout(&mmc_delayed_work_wake_lock, HZ / 2);
|
||||
else
|
||||
wake_unlock(&mmc_delayed_work_wake_lock);
|
||||
|
||||
if (host->caps & MMC_CAP_NEEDS_POLL)
|
||||
mmc_schedule_delayed_work(&host->detect, HZ);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void mmc_start_host(struct mmc_host *host)
|
||||
{
|
||||
|
||||
@@ -660,9 +660,6 @@ static void mmc_attach_bus_ops(struct mmc_host *host)
|
||||
int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
|
||||
{
|
||||
int err;
|
||||
|
||||
unsigned long flags;
|
||||
extern int sdmmc0_disable_Irq_ForRemoval;
|
||||
|
||||
BUG_ON(!host);
|
||||
WARN_ON(!host->claimed);
|
||||
@@ -711,10 +708,6 @@ int mmc_attach_mmc(struct mmc_host *host, u32 ocr)
|
||||
err = mmc_add_card(host->card);
|
||||
if (err)
|
||||
goto remove_card;
|
||||
|
||||
local_irq_save(flags);
|
||||
sdmmc0_disable_Irq_ForRemoval = 0; //close the IRQ for insertion or removal
|
||||
local_irq_restore(flags);
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
@@ -27,6 +27,29 @@ if SDMMC_RK2818
|
||||
This supports the use of the SDMMC1 controller on rk2818 processors.
|
||||
endif
|
||||
|
||||
config SDMMC_RK29
|
||||
tristate "RK29 SDMMC controller suppport"
|
||||
depends on ARCH_RK29
|
||||
help
|
||||
This selects the RK29 SDMMC controller.
|
||||
SDMMC0 used for sd/mmc card, and SDMMC1 used for sdio.
|
||||
if SDMMC_RK29
|
||||
comment "Now, there are two SDMMC controllers selected, SDMMC0 and SDMMC1."
|
||||
config SDMMC0_RK29
|
||||
tristate "RK29 SDMMC0 controller support(sdmmc)"
|
||||
default y
|
||||
depends on ARCH_RK29
|
||||
help
|
||||
This supports the use of the SDMMC0 controller on Rk29 processors.
|
||||
|
||||
config SDMMC1_RK29
|
||||
tristate "RK29 SDMMC1 controller support(sdio)"
|
||||
default y
|
||||
depends on ARCH_RK29
|
||||
help
|
||||
This supports the use of the SDMMC1 controller on Rk29 processors.
|
||||
endif
|
||||
|
||||
config MMC_ARMMMCI
|
||||
tristate "ARM AMBA Multimedia Card Interface support"
|
||||
depends on ARM_AMBA
|
||||
|
||||
@@ -6,6 +6,7 @@ ifeq ($(CONFIG_MMC_DEBUG),y)
|
||||
EXTRA_CFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_SDMMC_RK29) += rk29_sdmmc.o
|
||||
obj-$(CONFIG_SDMMC_RK2818) += rk2818-sdmmc.o
|
||||
obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
|
||||
obj-$(CONFIG_MMC_PXA) += pxamci.o
|
||||
|
||||
@@ -126,7 +126,7 @@
|
||||
|
||||
/* Specifies how often in millisecs to poll for card removal-insertion changes
|
||||
* when the timer switch is open */
|
||||
#define RK28_SDMMC0_SWITCH_POLL_DELAY 3500
|
||||
#define RK_SDMMC0_SWITCH_POLL_DELAY 3500
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
1484
drivers/mmc/host/rk29_sdmmc.c
Normal file
1484
drivers/mmc/host/rk29_sdmmc.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user