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Merge branch 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: sh: Fix up the SH-3 build for recent TLB changes. sh: export return_address() symbol. sh: Enable the mmu in start_secondary() sh: Fix FDPIC binary loader arch/sh/kernel: Use set_cpus_allowed_ptr sh: Update ecovec_defconfig USB gadget r8a66597-udc.c: duplicated include sh: update the TLB replacement counter for entry wiring.
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File diff suppressed because it is too large
Load Diff
@@ -211,7 +211,9 @@ extern void __kernel_vsyscall;
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#define VSYSCALL_AUX_ENT \
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if (vdso_enabled) \
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NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
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NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE); \
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else \
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NEW_AUX_ENT(AT_IGNORE, 0);
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#else
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#define VSYSCALL_AUX_ENT
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#endif /* CONFIG_VSYSCALL */
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@@ -219,7 +221,7 @@ extern void __kernel_vsyscall;
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#ifdef CONFIG_SH_FPU
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#define FPU_AUX_ENT NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT)
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#else
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#define FPU_AUX_ENT
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#define FPU_AUX_ENT NEW_AUX_ENT(AT_IGNORE, 0)
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#endif
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extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
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@@ -30,6 +30,8 @@
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#define MMUCR_URB 0x00FC0000
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#define MMUCR_URB_SHIFT 18
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#define MMUCR_URB_NENTRIES 64
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#define MMUCR_URC 0x0000FC00
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#define MMUCR_URC_SHIFT 10
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#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
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#define MMUCR_SE (1 << 4)
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@@ -48,7 +48,7 @@ static int sh_cpufreq_target(struct cpufreq_policy *policy,
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return -ENODEV;
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cpus_allowed = current->cpus_allowed;
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set_cpus_allowed(current, cpumask_of_cpu(cpu));
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set_cpus_allowed_ptr(current, cpumask_of(cpu));
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BUG_ON(smp_processor_id() != cpu);
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@@ -66,7 +66,7 @@ static int sh_cpufreq_target(struct cpufreq_policy *policy,
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freqs.flags = 0;
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cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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set_cpus_allowed(current, cpus_allowed);
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set_cpus_allowed_ptr(current, &cpus_allowed);
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clk_set_rate(cpuclk, freq);
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cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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@@ -9,6 +9,7 @@
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <asm/dwarf.h>
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#ifdef CONFIG_DWARF_UNWINDER
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@@ -52,3 +53,5 @@ void *return_address(unsigned int depth)
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}
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#endif
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EXPORT_SYMBOL_GPL(return_address);
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@@ -69,6 +69,7 @@ asmlinkage void __cpuinit start_secondary(void)
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unsigned int cpu;
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struct mm_struct *mm = &init_mm;
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enable_mmu();
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atomic_inc(&mm->mm_count);
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atomic_inc(&mm->mm_users);
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current->active_mm = mm;
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@@ -77,3 +77,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
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__raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT);
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back_to_cached();
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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int i;
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/*
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* Flush all the TLB.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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status = __raw_readl(MMUCR);
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status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
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if (status == 0)
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status = MMUCR_URB_NENTRIES;
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for (i = 0; i < status; i++)
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__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
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for (i = 0; i < 4; i++)
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__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
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back_to_cached();
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ctrl_barrier();
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local_irq_restore(flags);
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}
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@@ -77,3 +77,22 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
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for (i = 0; i < ways; i++)
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__raw_writel(data, addr + (i << 8));
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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/*
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* Flush all the TLB.
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*
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* Write to the MMU control register's bit:
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* TF-bit for SH-3, TI-bit for SH-4.
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* It's same position, bit #2.
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*/
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local_irq_save(flags);
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status = __raw_readl(MMUCR);
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status |= 0x04;
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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@@ -80,3 +80,31 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
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__raw_writel(data, addr);
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back_to_cached();
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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int i;
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/*
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* Flush all the TLB.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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status = __raw_readl(MMUCR);
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status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
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if (status == 0)
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status = MMUCR_URB_NENTRIES;
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for (i = 0; i < status; i++)
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__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
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for (i = 0; i < 4; i++)
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__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
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back_to_cached();
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ctrl_barrier();
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local_irq_restore(flags);
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}
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@@ -24,13 +24,9 @@ void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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local_irq_save(flags);
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/* Load the entry into the TLB */
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__update_tlb(vma, addr, pte);
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/* ... and wire it up. */
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status = __raw_readl(MMUCR);
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urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
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status &= ~MMUCR_URB;
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status &= ~MMUCR_URC;
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/*
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* Make sure we're not trying to wire the last TLB entry slot.
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@@ -39,7 +35,23 @@ void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
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urb = urb % MMUCR_URB_NENTRIES;
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/*
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* Insert this entry into the highest non-wired TLB slot (via
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* the URC field).
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*/
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status |= (urb << MMUCR_URC_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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/* Load the entry into the TLB */
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__update_tlb(vma, addr, pte);
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/* ... and wire it up. */
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status = __raw_readl(MMUCR);
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status &= ~MMUCR_URB;
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status |= (urb << MMUCR_URB_SHIFT);
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__raw_writel(status, MMUCR);
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ctrl_barrier();
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@@ -119,31 +119,3 @@ void local_flush_tlb_mm(struct mm_struct *mm)
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_all(void)
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{
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unsigned long flags, status;
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int i;
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/*
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* Flush all the TLB.
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*/
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local_irq_save(flags);
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jump_to_uncached();
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status = __raw_readl(MMUCR);
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status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
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if (status == 0)
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status = MMUCR_URB_NENTRIES;
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for (i = 0; i < status; i++)
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__raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
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for (i = 0; i < 4; i++)
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__raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
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back_to_cached();
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ctrl_barrier();
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local_irq_restore(flags);
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}
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@@ -23,7 +23,6 @@
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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