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Merge remote-tracking branch 'last/develop-3.0' into develop-3.0

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This commit is contained in:
黄涛
2011-11-25 17:47:39 +08:00
parent adc8abbd99 4c6d24c23b
commit bb81a72d22
153 changed files with 30630 additions and 18887 deletions
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2069
arch/arm/configs/rk29_ddr3sdk_defconfig
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2653
arch/arm/configs/rk29_k97_defconfig Normal file
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File diff suppressed because it is too large Load Diff

6
arch/arm/configs/rk29_phonesdk_defconfig
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@@ -1066,6 +1066,7 @@ CONFIG_GPIOLIB=y
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
CONFIG_GPIO_WM831X=y
CONFIG_GPIO_WM8994=y
#
# PCI GPIO expanders:
@@ -1128,13 +1129,13 @@ CONFIG_MFD_CORE=y
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_WM8400 is not set
CONFIG_MFD_WM831X=y
# CONFIG_MFD_WM831X_I2C is not set
CONFIG_MFD_WM831X_SPI=y
# CONFIG_MFD_WM831X_SPI_A22 is not set
# CONFIG_MFD_WM8350_I2C is not set
CONFIG_MFD_WM8994=y
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
@@ -1147,6 +1148,7 @@ CONFIG_REGULATOR=y
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
CONFIG_REGULATOR_WM831X=y
CONFIG_REGULATOR_WM8994=y
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
@@ -1660,7 +1662,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y
#
# MMC/SD/SDIO Host Controller Drivers
#
CONFIG_SDMMC_RK29_OLD=y
# CONFIG_SDMMC_RK29_OLD=y
CONFIG_SDMMC_RK29=y
#

2162
arch/arm/configs/rk29_td8801_v2_defconfig Normal file
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12
arch/arm/mach-rk29/Kconfig
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@@ -23,6 +23,12 @@ config MACH_RK29WINACCORD
help
Support for the ROCKCHIP Board For Rk29 Winaccord.
config MACH_RK29_K97
depends on ARCH_RK29
bool "ROCKCHIP Board Rk29 For K97"
help
Support for the ROCKCHIP Board For Rk29 K97.
config MACH_RK29FIH
depends on ARCH_RK29
bool "ROCKCHIP Board Rk29 For FIH"
@@ -47,6 +53,12 @@ config MACH_RK29_A22
help
Support for the ROCKCHIP Board For A22.
config MACH_RK29_TD8801_V2
depends on ARCH_RK29
bool "ROCKCHIP Board Rk29 For TD8801_v2"
help
Support for the ROCKCHIP Board For TD8801_v2.
config MACH_RK29_PHONEPADSDK
depends on ARCH_RK29
bool "ROCKCHIP Board Rk29 For Phone Pad Sdk"

2
arch/arm/mach-rk29/Makefile
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@@ -21,6 +21,8 @@ obj-$(CONFIG_MACH_RK29_MALATA) += board-malata.o board-rk29malata-key.o board-rk
obj-$(CONFIG_MACH_RK29_PHONESDK) += board-rk29-phonesdk.o board-rk29-phonesdk-key.o board-rk29-phonesdk-rfkill.o
obj-$(CONFIG_MACH_RK29FIH) += board-rk29-fih.o board-rk29-fih-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o
obj-$(CONFIG_MACH_RK29_A22) += board-rk29-a22.o board-rk29-a22-key.o board-rk29-a22-rfkill.o
obj-$(CONFIG_MACH_RK29_TD8801_V2) += board-rk29-td8801_v2.o board-rk29-td8801_v2-key.o board-rk29-td8801_v2-rfkill.o
obj-$(CONFIG_MACH_RK29_PHONEPADSDK) += board-rk29phonepadsdk.o board-rk29phonepadsdk-key.o board-rk29phonepadsdk-rfkill.o board-rk29phonepadsdk-power.o
obj-$(CONFIG_MACH_RK29_newton) += board-rk29-newton.o board-rk29-newton-key.o board-newton-rfkill.o board-rk29sdk-power.o
obj-$(CONFIG_MACH_RK29_K97) += board-rk29-k97.o board-rk29k97-key.o board-rk29sdk-rfkill.o board-rk29sdk-power.o

15
arch/arm/mach-rk29/board-rk29-ddr3sdk.c
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@@ -71,6 +71,7 @@
#define CONFIG_SENSOR_0 RK29_CAM_SENSOR_OV5642 /* back camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_0 0x78
#define CONFIG_SENSOR_IIC_ADAPTER_ID_0 1
#define CONFIG_SENSOR_ORIENTATION_0 0
#define CONFIG_SENSOR_POWER_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_0 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_0 RK29_PIN6_PB7
@@ -83,6 +84,7 @@
#define CONFIG_SENSOR_1 RK29_CAM_SENSOR_OV2659 /* front camera sensor */
#define CONFIG_SENSOR_IIC_ADDR_1 0x60
#define CONFIG_SENSOR_IIC_ADAPTER_ID_1 1
#define CONFIG_SENSOR_ORIENTATION_1 0
#define CONFIG_SENSOR_POWER_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_RESET_PIN_1 INVALID_GPIO
#define CONFIG_SENSOR_POWERDN_PIN_1 RK29_PIN5_PD7
@@ -1411,14 +1413,14 @@ static struct i2c_board_info __initdata board_i2c0_devices[] = {
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_alc5621)
#if defined (CONFIG_SND_SOC_RT5621)
{
.type = "ALC5621",
.type = "rt5621",
.addr = 0x1a,
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_alc5631)
#if defined (CONFIG_SND_SOC_RT5631)
{
.type = "rt5631",
.addr = 0x1a,
@@ -1432,6 +1434,13 @@ static struct i2c_board_info __initdata board_i2c0_devices[] = {
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_WM8988)
{
.type = "wm8988",
.addr = 0x1A,
.flags = 0,
},
#endif
#if defined (CONFIG_SND_SOC_WM8900)
{
.type = "wm8900",

3075
arch/arm/mach-rk29/board-rk29-k97.c Executable file
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File diff suppressed because it is too large Load Diff

293
arch/arm/mach-rk29/board-rk29-phonesdk.c
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@@ -51,8 +51,6 @@
#include <linux/mfd/wm831x/pdata.h>
#include <linux/mfd/wm831x/core.h>
#include <linux/mfd/wm831x/gpio.h>
#include <linux/mfd/wm8994/pdata.h>
#include <linux/mfd/wm8994/registers.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
@@ -79,7 +77,7 @@
#include "../../../drivers/input/touchscreen/xpt2046_cbn_ts.h"
#endif
#include "../../../drivers/misc/gps/rk29_gps.h"
#include "../../../drivers/serial/sc8800.h"
#include "../../../drivers/tty/serial/sc8800.h"
#ifdef CONFIG_VIDEO_RK29
/*---------------- Camera Sensor Macro Define Begin ------------------------*/
/*---------------- Camera Sensor Configuration Macro Begin ------------------------*/
@@ -160,6 +158,8 @@
#define WLAN_SECTION_SIZE_3 (PREALLOC_WLAN_BUF_NUM * 1024)
#define WLAN_SKB_BUF_NUM 16
#define UNLOCK_SECURITY_KEY ~(0x1<<5)
#define LOCK_SECURITY_KEY 0x00
static struct sk_buff *wlan_static_skb[WLAN_SKB_BUF_NUM];
@@ -712,9 +712,14 @@ int wm831x_pre_init(struct wm831x *parm)
wm831x_reg_write(parm, WM831X_POWER_STATE, (ret&0xfff8) | 0x04);
//BATT_FET_ENA = 1
wm831x_set_bits(parm, WM831X_RESET_CONTROL,0x1000,0x1000);
ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff;
printk("%s:WM831X_RESET_CONTROL=0x%x\n",__FUNCTION__,ret);
wm831x_reg_write(parm,WM831X_SECURITY_KEY,0x9716); // unlock security key
wm831x_set_bits(parm, WM831X_RESET_CONTROL,0x1000,0x1000);
ret = wm831x_reg_read(parm, WM831X_RESET_CONTROL) & 0xffff&UNLOCK_SECURITY_KEY;// enternal reset active in sleep
printk("%s:WM831X_RESET_CONTROL=0x%x\n",__FUNCTION__,ret);
wm831x_reg_write(parm, WM831X_RESET_CONTROL, ret);
wm831x_reg_write(parm,WM831X_SECURITY_KEY,LOCK_SECURITY_KEY); // lock securit
#if 0
wm831x_set_bits(parm, WM831X_LDO_ENABLE, (1 << 3), 0);
@@ -1689,35 +1694,6 @@ struct platform_device rk29_device_gps = {
};
#endif
/*****************************************************************************************
* wm8994 codec
* author: qjb@rock-chips.com
*****************************************************************************************/
struct wm8994_pdata wm8994_platdata = {
.BB_input_diff = 0,
.BB_class = NO_PCM_BB,
.no_earpiece = 0,
.sp_hp_same_channel = 0,
.PA_control_pin = 0,
.Power_EN_Pin = RK29_PIN5_PA1,
.speaker_incall_vol = 0,
.speaker_incall_mic_vol = -9,
.speaker_normal_vol = 6,
.earpiece_incall_vol = 0,
.headset_incall_vol = 6,
.headset_incall_mic_vol = -6,
.headset_normal_vol = -6,
.BT_incall_vol = 0,
.BT_incall_mic_vol = 0,
.recorder_vol = 30,
};
#ifdef CONFIG_RK_HEADSET_DET
#define HEADSET_GPIO RK29_PIN4_PD2
struct rk_headset_pdata rk_headset_info = {
@@ -1928,9 +1904,6 @@ static struct i2c_board_info __initdata board_i2c0_devices[] = {
.type = "wm8994",
.addr = 0x1a,
.flags = 0,
// #if defined(CONFIG_MFD_WM8994)
.platform_data = &wm8994_platdata,
// #endif
},
#endif
#if defined (CONFIG_BATTERY_STC3100)
@@ -2312,10 +2285,239 @@ struct platform_device rk2818_device_mtk23d = {
};
#endif
/*****************************************************************************************
* SDMMC devices
*****************************************************************************************/
#if !defined(CONFIG_SDMMC_RK29_OLD)
static void rk29_sdmmc_gpio_open(int device_id, int on)
{
switch(device_id)
{
case 0://mmc0
{
#ifdef CONFIG_SDMMC0_RK29
if(on)
{
gpio_direction_output(RK29_PIN1_PD0,GPIO_HIGH);//set mmc0-clk to high
gpio_direction_output(RK29_PIN1_PD1,GPIO_HIGH);//set mmc0-cmd to high.
gpio_direction_output(RK29_PIN1_PD2,GPIO_HIGH);//set mmc0-data0 to high.
gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);//set mmc0-data1 to high.
gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);//set mmc0-data2 to high.
gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);//set mmc0-data3 to high.
mdelay(30);
}
else
{
rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_GPIO1_D0);
gpio_request(RK29_PIN1_PD0, "mmc0-clk");
gpio_direction_output(RK29_PIN1_PD0,GPIO_LOW);//set mmc0-clk to low.
rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_GPIO1_D1);
gpio_request(RK29_PIN1_PD1, "mmc0-cmd");
gpio_direction_output(RK29_PIN1_PD1,GPIO_LOW);//set mmc0-cmd to low.
rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_GPIO1D2);
gpio_request(RK29_PIN1_PD2, "mmc0-data0");
gpio_direction_output(RK29_PIN1_PD2,GPIO_LOW);//set mmc0-data0 to low.
rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
gpio_request(RK29_PIN1_PD3, "mmc0-data1");
gpio_direction_output(RK29_PIN1_PD3,GPIO_LOW);//set mmc0-data1 to low.
rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
gpio_request(RK29_PIN1_PD4, "mmc0-data2");
gpio_direction_output(RK29_PIN1_PD4,GPIO_LOW);//set mmc0-data2 to low.
rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
gpio_request(RK29_PIN1_PD5, "mmc0-data3");
gpio_direction_output(RK29_PIN1_PD5,GPIO_LOW);//set mmc0-data3 to low.
mdelay(30);
}
#endif
}
break;
case 1://mmc1
{
#ifdef CONFIG_SDMMC1_RK29
if(on)
{
gpio_direction_output(RK29_PIN1_PC7,GPIO_HIGH);//set mmc1-clk to high
gpio_direction_output(RK29_PIN1_PC2,GPIO_HIGH);//set mmc1-cmd to high.
gpio_direction_output(RK29_PIN1_PC3,GPIO_HIGH);//set mmc1-data0 to high.
gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);//set mmc1-data1 to high.
gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);//set mmc1-data2 to high.
gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);//set mmc1-data3 to high.
mdelay(100);
}
else
{
rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_GPIO1C7);
gpio_request(RK29_PIN1_PC7, "mmc1-clk");
gpio_direction_output(RK29_PIN1_PC7,GPIO_LOW);//set mmc1-clk to low.
rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_GPIO1C2);
gpio_request(RK29_PIN1_PC2, "mmc1-cmd");
gpio_direction_output(RK29_PIN1_PC2,GPIO_LOW);//set mmc1-cmd to low.
rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_GPIO1C3);
gpio_request(RK29_PIN1_PC3, "mmc1-data0");
gpio_direction_output(RK29_PIN1_PC3,GPIO_LOW);//set mmc1-data0 to low.
mdelay(100);
}
#endif
}
break;
case 2: //mmc2
break;
default:
break;
}
}
static void rk29_sdmmc_set_iomux_mmc0(unsigned int bus_width)
{
switch (bus_width)
{
case 1://SDMMC_CTYPE_4BIT:
{
rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_SDMMC0_DATA1);
rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_SDMMC0_DATA2);
rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_SDMMC0_DATA3);
}
break;
case 0x10000://SDMMC_CTYPE_8BIT:
break;
case 0xFFFF: //gpio_reset
{
rk29_mux_api_set(GPIO5D5_SDMMC0PWREN_NAME, GPIO5H_GPIO5D5);
gpio_request(RK29_PIN5_PD5,"sdmmc-power");
gpio_direction_output(RK29_PIN5_PD5,GPIO_HIGH); //power-off
rk29_sdmmc_gpio_open(0, 0);
gpio_direction_output(RK29_PIN5_PD5,GPIO_LOW); //power-on
rk29_sdmmc_gpio_open(0, 1);
}
break;
default: //case 0://SDMMC_CTYPE_1BIT:
{
rk29_mux_api_set(GPIO1D1_SDMMC0CMD_NAME, GPIO1H_SDMMC0_CMD);
rk29_mux_api_set(GPIO1D0_SDMMC0CLKOUT_NAME, GPIO1H_SDMMC0_CLKOUT);
rk29_mux_api_set(GPIO1D2_SDMMC0DATA0_NAME, GPIO1H_SDMMC0_DATA0);
rk29_mux_api_set(GPIO1D3_SDMMC0DATA1_NAME, GPIO1H_GPIO1D3);
gpio_request(RK29_PIN1_PD3, "mmc0-data1");
gpio_direction_output(RK29_PIN1_PD3,GPIO_HIGH);
rk29_mux_api_set(GPIO1D4_SDMMC0DATA2_NAME, GPIO1H_GPIO1D4);
gpio_request(RK29_PIN1_PD4, "mmc0-data2");
gpio_direction_output(RK29_PIN1_PD4,GPIO_HIGH);
rk29_mux_api_set(GPIO1D5_SDMMC0DATA3_NAME, GPIO1H_GPIO1D5);
gpio_request(RK29_PIN1_PD5, "mmc0-data3");
gpio_direction_output(RK29_PIN1_PD5,GPIO_HIGH);
}
break;
}
}
static void rk29_sdmmc_set_iomux_mmc1(unsigned int bus_width)
{
#if 0
switch (bus_width)
{
case 1://SDMMC_CTYPE_4BIT:
{
rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
}
break;
case 0x10000://SDMMC_CTYPE_8BIT:
break;
case 0xFFFF:
{
rk29_sdmmc_gpio_open(1, 0);
rk29_sdmmc_gpio_open(1, 1);
}
break;
default: //case 0://SDMMC_CTYPE_1BIT:
{
rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_GPIO1C4);
gpio_request(RK29_PIN1_PC4, "mmc1-data1");
gpio_direction_output(RK29_PIN1_PC4,GPIO_HIGH);
rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_GPIO1C5);
gpio_request(RK29_PIN1_PC5, "mmc1-data2");
gpio_direction_output(RK29_PIN1_PC5,GPIO_HIGH);
rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_GPIO1C6);
gpio_request(RK29_PIN1_PC6, "mmc1-data3");
gpio_direction_output(RK29_PIN1_PC6,GPIO_HIGH);
}
break;
}
#else
rk29_mux_api_set(GPIO1C2_SDMMC1CMD_NAME, GPIO1H_SDMMC1_CMD);
rk29_mux_api_set(GPIO1C7_SDMMC1CLKOUT_NAME, GPIO1H_SDMMC1_CLKOUT);
rk29_mux_api_set(GPIO1C3_SDMMC1DATA0_NAME, GPIO1H_SDMMC1_DATA0);
rk29_mux_api_set(GPIO1C4_SDMMC1DATA1_NAME, GPIO1H_SDMMC1_DATA1);
rk29_mux_api_set(GPIO1C5_SDMMC1DATA2_NAME, GPIO1H_SDMMC1_DATA2);
rk29_mux_api_set(GPIO1C6_SDMMC1DATA3_NAME, GPIO1H_SDMMC1_DATA3);
#endif
}
static void rk29_sdmmc_set_iomux_mmc2(unsigned int bus_width)
{
;//
}
static void rk29_sdmmc_set_iomux(int device_id, unsigned int bus_width)
{
switch(device_id)
{
case 0:
#ifdef CONFIG_SDMMC0_RK29
rk29_sdmmc_set_iomux_mmc0(bus_width);
#endif
break;
case 1:
#ifdef CONFIG_SDMMC1_RK29
rk29_sdmmc_set_iomux_mmc1(bus_width);
#endif
break;
case 2:
rk29_sdmmc_set_iomux_mmc2(bus_width);
break;
default:
break;
}
}
#endif
#ifdef CONFIG_SDMMC0_RK29
static int rk29_sdmmc0_cfg_gpio(void)
{
@@ -2350,6 +2552,9 @@ struct rk29_sdmmc_platform_data default_sdmmc0_data = {
.use_dma = 1,
#else
.use_dma = 0,
#endif
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
.detect_irq = RK29_PIN2_PA2, // INVALID_GPIO
.enable_sd_wakeup = 0,
@@ -2384,6 +2589,9 @@ struct rk29_sdmmc_platform_data default_sdmmc1_data = {
MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED),
.io_init = rk29_sdmmc1_cfg_gpio,
.dma_name = "sdio",
#if !defined(CONFIG_SDMMC_RK29_OLD)
.set_iomux = rk29_sdmmc_set_iomux,
#endif
#ifdef CONFIG_SDMMC1_USE_DMA
.use_dma = 1,
#else
@@ -3199,8 +3407,12 @@ static int rk29xx_virtual_keys_init(void)
static void __init rk29_gic_init_irq(void)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38))
gic_init(0, 32, (void __iomem *)RK29_GICPERI_BASE, (void __iomem *)RK29_GICCPU_BASE);
#else
gic_dist_init(0, (void __iomem *)RK29_GICPERI_BASE, 32);
gic_cpu_init(0, (void __iomem *)RK29_GICCPU_BASE);
#endif
}
static void __init machine_rk29_init_irq(void)
@@ -3312,8 +3524,11 @@ static void __init machine_rk29_mapio(void)
MACHINE_START(RK29, "RK29board")
/* UART for LL DEBUG */
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 37))
/* UART for LL DEBUG */
.phys_io = RK29_UART1_PHYS & 0xfff00000,
.io_pg_offst = ((RK29_UART1_BASE) >> 18) & 0xfffc,
#endif
.boot_params = RK29_SDRAM_PHYS + 0x88000,
.fixup = machine_rk29_fixup,
.map_io = machine_rk29_mapio,

105
arch/arm/mach-rk29/board-rk29-td8801_v2-key.c Normal file
View File

@@ -0,0 +1,105 @@
#include <mach/key.h>
#include <mach/gpio.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "menu",
.code = EV_MENU,
.gpio = RK29_PIN6_PA0,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = RK29_PIN6_PA1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = RK29_PIN6_PA2,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.gpio = RK29_PIN6_PA3,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "search",
.code = KEY_SEARCH,
.gpio = RK29_PIN6_PA4,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_BACK,
.gpio = RK29_PIN6_PA5,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "sensor",
.code = KEY_CAMERA,
.gpio = RK29_PIN6_PA6,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK29_PIN6_PA7,
.active_low = PRESS_LEV_LOW,
.wakeup = 1,
},
#if 0
{
.desc = "vol+",
.code = KEY_VOLUMEDOWN,
.adc_value = 95,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEUP,
.adc_value = 249,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "menu",
.code = EV_MENU,
.adc_value = 406,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.code_long_press = KEY_F4,
.adc_value = 561,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_ESC,
.adc_value = 726,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "adkey6",
.code = KEY_BACK,
.code_long_press = EV_ENCALL,
.adc_value = 899,
.active_low = PRESS_LEV_LOW,
},
#endif
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

313
arch/arm/mach-rk29/board-rk29-td8801_v2-rfkill.c Normal file
View File

@@ -0,0 +1,313 @@
/*
* Copyright (C) 2010 ROCKCHIP, Inc.
* Author: roger_chen <cz@rock-chips.com>
*
* This program is the bluetooth device bcm4329's driver,
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/rfkill.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/wakelock.h>
#include <linux/fs.h>
#include <asm/uaccess.h>
#include <mach/gpio.h>
#include <asm/irq.h>
#include <mach/iomux.h>
#include <linux/wakelock.h>
#include <linux/timer.h>
#include <mach/board.h>
#if 0
#define DBG(x...) printk(KERN_INFO x)
#else
#define DBG(x...)
#endif
#define BT_WAKE_HOST_SUPPORT 1
struct bt_ctrl
{
struct rfkill *bt_rfk;
#if BT_WAKE_HOST_SUPPORT
struct timer_list tl;
bool b_HostWake;
struct wake_lock bt_wakelock;
#endif
};
#define BT_GPIO_POWER RK29_PIN5_PD6
#define IOMUX_BT_GPIO_POWER rk29_mux_api_set(GPIO5D6_SDMMC1PWREN_NAME, GPIO5H_GPIO5D6);
#define BT_GPIO_RESET RK29_PIN6_PC7
#define BT_GPIO_WAKE_UP RK29_PIN6_PD0
#define BT_GPIO_WAKE_UP_HOST RK29_PIN4_PD4
#define IOMUX_BT_GPIO_WAKE_UP_HOST() rk29_mux_api_set(GPIO4D4_CPUTRACECLK_NAME,GPIO4H_GPIO4D4);
//bt cts paired to uart rts
#define UART_RTS RK29_PIN2_PA7
#define IOMUX_UART_RTS_GPIO rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_GPIO2A7);
#define IOMUX_UART_RTS rk29_mux_api_set(GPIO2A7_UART2RTSN_NAME, GPIO2L_UART2_RTS_N);
#define BT_WAKE_LOCK_TIMEOUT 10 //s
static const char bt_name[] = "bcm4329";
extern int rk29sdk_bt_power_state;
extern int rk29sdk_wifi_power_state;
struct bt_ctrl gBtCtrl;
#if BT_WAKE_HOST_SUPPORT
void resetBtHostSleepTimer(void)
{
mod_timer(&(gBtCtrl.tl),jiffies + BT_WAKE_LOCK_TIMEOUT*HZ);//再重新设置超时值。
}
void btWakeupHostLock(void)
{
if(gBtCtrl.b_HostWake == false){
DBG("*************************Lock\n");
wake_lock(&(gBtCtrl.bt_wakelock));
gBtCtrl.b_HostWake = true;
}
}
void btWakeupHostUnlock(void)
{
if(gBtCtrl.b_HostWake == true){
DBG("*************************UnLock\n");
wake_unlock(&(gBtCtrl.bt_wakelock)); //让系统睡眠
gBtCtrl.b_HostWake = false;
}
}
static void timer_hostSleep(unsigned long arg)
{
DBG("%s---b_HostWake=%d\n",__FUNCTION__,gBtCtrl.b_HostWake);
btWakeupHostUnlock();
}
#ifdef CONFIG_PM
static int bcm4329_rfkill_suspend(struct platform_device *pdev, pm_message_t state)
{
DBG("%s\n",__FUNCTION__);
//To prevent uart to receive bt data when suspended
IOMUX_UART_RTS_GPIO;
gpio_request(UART_RTS, "uart_rts");
gpio_direction_output(UART_RTS, 0);
gpio_set_value(UART_RTS, GPIO_HIGH);
return 0;
}
static int bcm4329_rfkill_resume(struct platform_device *pdev)
{
DBG("%s\n",__FUNCTION__);
btWakeupHostLock();
resetBtHostSleepTimer();
gpio_set_value(UART_RTS, GPIO_LOW);
IOMUX_UART_RTS;
return 0;
}
#else
#define bcm4329_rfkill_suspend NULL
#define bcm4329_rfkill_resume NULL
#endif
static irqreturn_t bcm4329_wake_host_irq(int irq, void *dev)
{
DBG("%s\n",__FUNCTION__);
btWakeupHostLock();
resetBtHostSleepTimer();
return IRQ_HANDLED;
}
#endif
#ifdef CONFIG_BT_HCIBCM4325
int bcm4325_sleep(int bSleep)
{
// printk("*************bt enter sleep***************\n");
if (bSleep)
gpio_set_value(BT_GPIO_WAKE_UP, GPIO_LOW); //low represent bt device may enter sleep
else
gpio_set_value(BT_GPIO_WAKE_UP, GPIO_HIGH); //high represent bt device must be awake
//printk("sleep=%d\n",bSleep);
}
#endif
static int bcm4329_set_block(void *data, bool blocked)
{
DBG("%s---blocked :%d\n", __FUNCTION__, blocked);
IOMUX_BT_GPIO_POWER;
if (false == blocked) {
gpio_set_value(BT_GPIO_POWER, GPIO_HIGH); /* bt power on */
gpio_set_value(BT_GPIO_RESET, GPIO_LOW);
mdelay(200);
gpio_set_value(BT_GPIO_RESET, GPIO_HIGH); /* bt reset deactive*/
mdelay(200);
#if BT_WAKE_HOST_SUPPORT
btWakeupHostLock();
#endif
pr_info("bt turn on power\n");
}
else {
#if BT_WAKE_HOST_SUPPORT
btWakeupHostUnlock();
#endif
if (!rk29sdk_wifi_power_state) {
gpio_set_value(BT_GPIO_POWER, GPIO_LOW); /* bt power off */
mdelay(20);
pr_info("bt shut off power\n");
}else {
pr_info("bt shouldn't shut off power, wifi is using it!\n");
}
gpio_set_value(BT_GPIO_RESET, GPIO_LOW); /* bt reset active*/
mdelay(20);
}
rk29sdk_bt_power_state = !blocked;
return 0;
}
static const struct rfkill_ops bcm4329_rfk_ops = {
.set_block = bcm4329_set_block,
};
static int __devinit bcm4329_rfkill_probe(struct platform_device *pdev)
{
int rc = 0;
bool default_state = true;
DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
/* default to bluetooth off */
bcm4329_set_block(NULL, default_state); /* blocked -> bt off */
gBtCtrl.bt_rfk = rfkill_alloc(bt_name,
NULL,
RFKILL_TYPE_BLUETOOTH,
&bcm4329_rfk_ops,
NULL);
if (!gBtCtrl.bt_rfk)
{
printk("fail to rfkill_allocate************\n");
return -ENOMEM;
}
rfkill_set_states(gBtCtrl.bt_rfk, default_state, false);
rc = rfkill_register(gBtCtrl.bt_rfk);
if (rc)
{
printk("failed to rfkill_register,rc=0x%x\n",rc);
rfkill_destroy(gBtCtrl.bt_rfk);
}
gpio_request(BT_GPIO_POWER, NULL);
gpio_request(BT_GPIO_RESET, NULL);
gpio_request(BT_GPIO_WAKE_UP, NULL);
#if BT_WAKE_HOST_SUPPORT
init_timer(&(gBtCtrl.tl));
gBtCtrl.tl.expires = jiffies + BT_WAKE_LOCK_TIMEOUT*HZ;
gBtCtrl.tl.function = timer_hostSleep;
add_timer(&(gBtCtrl.tl));
gBtCtrl.b_HostWake = false;
wake_lock_init(&(gBtCtrl.bt_wakelock), WAKE_LOCK_SUSPEND, "bt_wake");
rc = gpio_request(BT_GPIO_WAKE_UP_HOST, "bt_wake");
if (rc) {
printk("%s:failed to request RAHO_BT_WAKE_UP_HOST\n",__FUNCTION__);
}
IOMUX_BT_GPIO_WAKE_UP_HOST();
gpio_pull_updown(BT_GPIO_WAKE_UP_HOST,GPIOPullUp);
rc = request_irq(gpio_to_irq(BT_GPIO_WAKE_UP_HOST),bcm4329_wake_host_irq,IRQF_TRIGGER_FALLING,NULL,NULL);
if(rc)
{
printk("%s:failed to request RAHO_BT_WAKE_UP_HOST irq\n",__FUNCTION__);
gpio_free(BT_GPIO_WAKE_UP_HOST);
}
enable_irq_wake(gpio_to_irq(BT_GPIO_WAKE_UP_HOST)); // so RAHO_BT_WAKE_UP_HOST can wake up system
printk(KERN_INFO "bcm4329 module has been initialized,rc=0x%x\n",rc);
#endif
return rc;
}
static int __devexit bcm4329_rfkill_remove(struct platform_device *pdev)
{
if (gBtCtrl.bt_rfk)
rfkill_unregister(gBtCtrl.bt_rfk);
gBtCtrl.bt_rfk = NULL;
#if BT_WAKE_HOST_SUPPORT
del_timer(&(gBtCtrl.tl));//删掉定时器
btWakeupHostUnlock();
wake_lock_destroy(&(gBtCtrl.bt_wakelock));
#endif
platform_set_drvdata(pdev, NULL);
DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
return 0;
}
static struct platform_driver bcm4329_rfkill_driver = {
.probe = bcm4329_rfkill_probe,
.remove = __devexit_p(bcm4329_rfkill_remove),
.driver = {
.name = "rk29sdk_rfkill",
.owner = THIS_MODULE,
},
#if BT_WAKE_HOST_SUPPORT
.suspend = bcm4329_rfkill_suspend,
.resume = bcm4329_rfkill_resume,
#endif
};
/*
* Module initialization
*/
static int __init bcm4329_mod_init(void)
{
int ret;
DBG("Enter::%s,line=%d\n",__FUNCTION__,__LINE__);
ret = platform_driver_register(&bcm4329_rfkill_driver);
printk("ret=0x%x\n", ret);
return ret;
}
static void __exit bcm4329_mod_exit(void)
{
platform_driver_unregister(&bcm4329_rfkill_driver);
}
module_init(bcm4329_mod_init);
module_exit(bcm4329_mod_exit);
MODULE_DESCRIPTION("bcm4329 Bluetooth driver");
MODULE_AUTHOR("roger_chen cz@rock-chips.com");
MODULE_LICENSE("GPL");

3659
arch/arm/mach-rk29/board-rk29-td8801_v2.c Executable file
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File diff suppressed because it is too large Load Diff

108
arch/arm/mach-rk29/board-rk29k97-key.c Executable file
View File

@@ -0,0 +1,108 @@
#include <mach/key.h>
#include <mach/gpio.h>
#include <mach/board.h>
#define EV_ENCALL KEY_F4
#define EV_MENU KEY_F1
#define PRESS_LEV_LOW 1
#define PRESS_LEV_HIGH 0
static struct rk29_keys_button key_button[] = {
{
.desc = "menu",
.code = EV_MENU,
.gpio = RK29_PIN6_PA4,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol+",
.code = KEY_VOLUMEUP,
.gpio = RK29_PIN6_PA1,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEDOWN,
.gpio = RK29_PIN6_PA2,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.gpio = RK29_PIN6_PA3,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_BACK,
.gpio = RK29_PIN6_PA0,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "sensor",
.code = KEY_CAMERA,
.gpio = RK29_PIN6_PA6,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "play",
.code = KEY_POWER,
.gpio = RK29_PIN6_PA7,
.active_low = PRESS_LEV_LOW,
//.code_long_press = EV_ENCALL,
.wakeup = 1,
},
#if 0
{
.desc = "vol+",
.code = KEY_VOLUMEDOWN,
.adc_value = 95,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "vol-",
.code = KEY_VOLUMEUP,
.adc_value = 249,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "menu",
.code = EV_MENU,
.adc_value = 406,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "home",
.code = KEY_HOME,
.code_long_press = KEY_F4,
.adc_value = 561,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "esc",
.code = KEY_ESC,
.adc_value = 726,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
{
.desc = "adkey6",
.code = KEY_BACK,
.code_long_press = EV_ENCALL,
.adc_value = 899,
.gpio = INVALID_GPIO,
.active_low = PRESS_LEV_LOW,
},
#endif
};
struct rk29_keys_platform_data rk29_keys_pdata = {
.buttons = key_button,
.nbuttons = ARRAY_SIZE(key_button),
.chn = -1, //chn: 0-7, if do not use ADC,set 'chn' -1
};

107
arch/arm/mach-rk29/ddr.c
View File

@@ -7,6 +7,11 @@
* Author:
* hcy@rock-chips.com
* yk@rock-chips.com
*
* v2.02
* reset DRAM DLL at update_mr
* adjust ZQCR0, MR0,MR1,MR2 for ODT and driver strengh
*
* v2.01
* disable DFTCMP
*/
@@ -261,6 +266,7 @@
#define DDR3_MR1_RTT_NOM(n) (((n&1)<<2)|((n&2)<<5)|((n&4)<<7))
//mr2 for ddr3
#define DDR3_MR2_RTT_WR(n) ((n&0x3)<<9)
#define DDR3_MR2_CWL(n) (((n-5)&0x7)<<3)
//EMR; //Extended Mode Register
@@ -532,7 +538,6 @@ static __sramdata uint32_t tWR_MR0;
static __sramdata uint32_t cl;
static __sramdata uint32_t cwl;
static __sramdata uint32_t cpu_freq;
static __sramdata uint32_t ddr_freq;
static __sramdata volatile uint32_t ddr_stop;
@@ -543,17 +548,17 @@ Cpu highest frequency is 1.2 GHz
1 cycle = 1/1.2 ns
1 us = 1000 ns = 1000 * 1.2 cycles = 1200 cycles
*****************************************************************************/
//static
void __sramlocalfunc delayus(uint32_t us)
{
uint32_t count;
if(cpu_freq == 24)
count = us * 6;//533;
else
count = us*200;
while(count--) // 3 cycles
barrier();
static __sramdata uint32_t loops_per_us;
#define LPJ_100MHZ 499728UL
/*static*/ void __sramlocalfunc delayus(uint32_t us)
{
uint32_t count;
count = loops_per_us*us;
while(count--) // 3 cycles
barrier();
}
static uint32_t __sramlocalfunc ddr_get_parameter(uint32_t nMHz)
@@ -926,7 +931,7 @@ static uint32_t __sramlocalfunc ddr_update_timing(void)
pDDR_Reg->TPR[1] = value | TFAW(tFAW);
// ddr3 tCKE should be tCKESR=tCKE+1nCK
pDDR_Reg->TPR[2] = TXS(tXS) | TXP(tXP) | TCKE(4);//0x198c8;//
pDDR_Reg->ZQCR[0] = 0x10039d29;//(pDDR_Reg->ZQSR & (0x3FF)) | (0x6<<10) | (0x6<<15) | (0x1<<28);
}
else if(mem_type == DDRII)
{
@@ -965,9 +970,20 @@ static uint32_t __sramlocalfunc ddr_update_mr(void)
if(mem_type == DDR3)
{
pDDR_Reg->TPR3 = value | CL(cl) | CWL(cwl) | WR(tWR);
pDDR_Reg->MR = DDR3_BL8 | DDR3_CL(cl) | DDR3_MR0_WR(tWR_MR0)/*15 ns*/;
pDDR_Reg->MR = DDR3_BL8 | DDR3_CL(cl) | DDR3_MR0_DLL_RESET | DDR3_MR0_WR(tWR_MR0)/*15 ns*/;
delayus(1);
pDDR_Reg->EMR2 = DDR3_MR2_CWL(cwl);
/*
* DIC:Output Driver Impedance Control,0, RZQ(240)/6
* Rtt_Nom:2 RZQ(240)/2
*/
pDDR_Reg->EMR = DDR3_MR1_DIC(0) | DDR3_MR1_AL(0) | DDR3_MR1_RTT_NOM(2);
delayus(1);
/* DDR3 :CWL=5
* RTT_WR: 1, RZQ(240)/4
*/
pDDR_Reg->EMR2 = DDR3_MR2_RTT_WR(1)|DDR3_MR2_CWL(cwl);
delayus(1);
pDDR_Reg->EMR3 = 0x0;
}
else if(mem_type == DDRII)
{
@@ -1047,7 +1063,7 @@ static uint32_t __sramlocalfunc ddr_set_pll(uint32_t nMHz, uint32_t set)
delayus(1); //delay at least 500ns
pSCU_Reg->CRU_DPLL_CON &= ~(0x1<<15);
delayus(2000); // 7.2us*140=1.008ms
delayus(500); // wait for DPLL stable
// ddr pll normal
pSCU_Reg->CRU_MODE_CON |= 0x1<<6;
@@ -1087,7 +1103,7 @@ void __sramlocalfunc ddr_selfrefresh_enter(void)
pSCU_Reg->CRU_SOFTRST_CON[0] |= (0x1F<<19); //reset DLL
delayus(1);
pSCU_Reg->CRU_CLKGATE_CON[0] |= (0x1<<18); //close DDR PHY clock
delayus(10);
delayus(1);
pDDR_Reg->DLLCR09[0] =0x80000000;
pDDR_Reg->DLLCR09[9] =0x80000000;
pDDR_Reg->DLLCR09[1] =0x80000000;
@@ -1105,13 +1121,13 @@ void __sramlocalfunc ddr_selfrefresh_exit(void)
6. Re-enables all host ports
*/
pSCU_Reg->CRU_CLKGATE_CON[0] &= ~(0x1<<18); //open DDR PHY clock
delayus(10);
delayus(1);
pSCU_Reg->CRU_SOFTRST_CON[0] &= ~(0x1F<<19); //de-reset DLL
delayus(1000);
delayus(10);
pDDR_Reg->CCR &= ~ITMRST; //ITM reset
delayus(500);
delayus(5);
pDDR_Reg->DCR = (pDDR_Reg->DCR & (~((0x1<<24) | (0x1<<13) | (0xF<<27) | (0x1<<31)))) | ((0x1<<13) | (0x7<<27) | (0x1<<31)); //exit
delayus(1000);
delayus(10);
ddr_update_mr();
delayus(1);
@@ -1120,8 +1136,8 @@ refresh:
pDDR_Reg->DRR |= RD;
delayus(1);
pDDR_Reg->CCR |= DTT;
//delayus(15);
dsb();
delayus(10);
do
{
delayus(1);
@@ -1148,16 +1164,22 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
volatile u32 n;
unsigned long flags;
volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
uint32_t regvalue = pSCU_Reg->CRU_APLL_CON;
uint32_t freq;
if((pSCU_Reg->CRU_MODE_CON & 0x03) == 0x03)
cpu_freq = 24;
else
cpu_freq = clk_get_rate(clk_get(NULL,"core"))/1000000;
// freq = (Fin/NR)*NF/OD
if((pSCU_Reg->CRU_MODE_CON&3) == 1) // CPLL Normal mode
freq = 24 *((((regvalue>>3)&0x7f)+1)<<1) // NF = 2*(CLKF+1)
/(((regvalue>>10)&0x1f)+1) // NR = CLKR+1
*(2<<((regvalue>>1)&3)); // OD = 2^CLKOD
else
freq = 24;
loops_per_us = LPJ_100MHZ*freq / 1000000;
ret = ddr_set_pll(nMHz, 0);
ddr_get_parameter(ret);
/** 1. Make sure there is no host access */
#if 1
local_irq_save(flags);
flush_cache_all();
__cpuc_flush_kern_all();
@@ -1175,7 +1197,6 @@ uint32_t __sramfunc ddr_change_freq(uint32_t nMHz)
n= pDDR_Reg->CCR;
n= pSCU_Reg->CRU_SOFTRST_CON[0];
dsb();
#endif
/** 2. ddr enter self-refresh mode or precharge power-down mode */
ddr_selfrefresh_enter();
@@ -1237,9 +1258,19 @@ void __sramfunc ddr_suspend(void)
{
uint32_t n;
volatile unsigned int * temp=(volatile unsigned int *)SRAM_CODE_OFFSET;
uint32_t regvalue = pSCU_Reg->CRU_APLL_CON;
uint32_t freq;
// freq = (Fin/NR)*NF/OD
if((pSCU_Reg->CRU_MODE_CON&3) == 1) // CPLL Normal mode
freq = 24 *((((regvalue>>3)&0x7f)+1)<<1) // NF = 2*(CLKF+1)
/(((regvalue>>10)&0x1f)+1) // NR = CLKR+1
*(2<<((regvalue>>1)&3)); // OD = 2^CLKOD
else
freq = 24;
loops_per_us = LPJ_100MHZ*freq / 1000000;
cpu_freq = 24;
/** 1. Make sure there is no host access */
flush_cache_all();
__cpuc_flush_kern_all();
@@ -1321,10 +1352,12 @@ void __sramfunc ddr_resume(void)
delayus(1);
#endif
#if 1
pSCU_Reg->CRU_DPLL_CON &= ~(0x1 << 15); //power on DPLL
// while(!(pGRF_Reg->GRF_SOC_CON[0] & (1<<28)));
delayus(500); // 7.2us*140=1.008ms // Ëø¶¨pll
pSCU_Reg->CRU_DPLL_CON &= ~(0x1 << 15); //power on DPLL
delayus(300); // Ëø¶¨pll
do
{
delayus(3);
}while(!(pGRF_Reg->GRF_SOC_CON[0] & (1<<28))); //wait pll lock
// ddr pll normal
value = pSCU_Reg->CRU_MODE_CON;
value &=~(0x3<<6);
@@ -1338,7 +1371,6 @@ void __sramfunc ddr_resume(void)
pSCU_Reg->CRU_CLKGATE_CON[1] &= ~(0x1<<6); //close DDR PERIPH AXI clock
pSCU_Reg->CRU_CLKGATE_CON[0] &= ~(0x1<<18); //enable DDR PHY clock
delayus(1);
#endif
ddr_selfrefresh_exit();
dsb();
@@ -1372,7 +1404,6 @@ typedef struct _dtt_cnt_t
uint32_t cnt;
}dtt_cnt_t;
//static int __init ddr_probe(void)
int ddr_init(uint32_t dram_type, uint32_t freq)
{
volatile uint32_t value = 0;
@@ -1383,7 +1414,7 @@ int ddr_init(uint32_t dram_type, uint32_t freq)
uint32_t bank = 0;
uint32_t n;
ddr_print("version 2.01 20110504 \n");
ddr_print("version 2.02 20111109 \n");
mem_type = (pDDR_Reg->DCR & 0x3);
ddr_type = dram_type;//DDR3_TYPE;//
@@ -1450,6 +1481,8 @@ int ddr_init(uint32_t dram_type, uint32_t freq)
}
pDDR_Reg->DTAR = value;
pDDR_Reg->CCR &= ~(DFTCMP);
pDDR_Reg->IOCR = AUTO_CMD_IOPD(3) | AUTO_DATA_IOPD(3) | DQ_ODT | DQS_ODT | DQRTT | DQSRTT;
//pDDR_Reg->CCR |= DQSCFG;// passive windowing mode
if((mem_type == DDRII) || (mem_type == DDR3))
@@ -1492,8 +1525,6 @@ int ddr_init(uint32_t dram_type, uint32_t freq)
}
EXPORT_SYMBOL(ddr_init);
//core_initcall_sync(ddr_probe);
#ifdef CONFIG_DDR_RECONFIG
#include "ddr_reconfig.c"
#endif

10
arch/arm/mach-rk29/devices.c
View File

@@ -221,6 +221,16 @@ struct platform_device rk29_device_backlight = {
}
};
#endif
#ifdef CONFIG_BUTTON_LIGHT
struct platform_device rk29_device_buttonlight = {
.name = "rk29_button_light",
.id = -1,
.dev = {
.platform_data = &rk29_button_light_info,
}
};
#endif
#ifdef CONFIG_SDMMC0_RK29
#ifndef CONFIG_EMMC_RK29
static struct resource resources_sdmmc0[] = {

2
arch/arm/mach-rk29/devices.h
View File

@@ -65,7 +65,9 @@ extern struct platform_device rk29_device_sdmmc1;
extern struct platform_device rk29_device_adc;
extern struct platform_device rk29_device_vmac;
extern struct rk29_bl_info rk29_bl_info;
extern struct rk29_button_light_info rk29_button_light_info;
extern struct platform_device rk29_device_backlight;
extern struct platform_device rk29_device_buttonlight;
extern struct platform_device rk29_device_usb20_otg;
extern struct platform_device rk29_device_usb20_host;
extern struct platform_device rk29_device_usb11_host;

14
arch/arm/mach-rk29/include/mach/board.h
View File

@@ -248,6 +248,17 @@ struct mma8452_platform_data {
int (*mma8452_platform_wakeup)(void);
void (*exit_platform_hw)(void);
};
struct bma023_platform_data {
u16 model;
u16 swap_xy;
u16 swap_xyz;
signed char orientation[9];
int (*get_pendown_state)(void);
int (*init_platform_hw)(void);
int (*mma8452_platform_sleep)(void);
int (*mma8452_platform_wakeup)(void);
void (*exit_platform_hw)(void);
};
struct cm3202_platform_data {
int CM3202_SD_IOPIN;
@@ -274,6 +285,9 @@ struct ft5406_platform_data {
};
struct goodix_platform_data {
int model ;
int rest_pin;
int irq_pin ;
int (*get_pendown_state)(void);
int (*init_platform_hw)(void);
int (*platform_sleep)(void);

1
arch/arm/mach-rk29/include/mach/rk29_camera.h
View File

@@ -160,6 +160,7 @@ struct rk29camera_gpio_res {
unsigned int gpio_flash;
unsigned int gpio_flag;
unsigned int gpio_init;
unsigned int orientation;
const char *dev_name;
};

27
arch/arm/mach-rk29/pm.c
View File

@@ -157,28 +157,21 @@ void __sramfunc ddr_testmode(void)
{
for (;;)
{
sram_printch(' ');
sram_printch('8');
sram_printch('8');
sram_printch('8');
sram_printch(' ');
sram_printascii("change freq\n");
g_crc1 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
nMHz = 333 + (random32()>>25);
if(nMHz > 402)
nMHz = 402;
nMHz = 333 + random32();
nMHz %= 490;
if(nMHz < 100)
nMHz = 100;
nMHz = ddr_change_freq(nMHz);
printhex(nMHz);
sram_printch(' ');
printhex(n++);
//ddr_print("%s change freq to: %d MHz\n", __func__, nMHz);
ddr_change_freq(nMHz);
sram_printch(' ');
g_crc2 = calc_crc32((u32)_stext, (size_t)(_etext-_stext));
if (g_crc1!=g_crc2)
{
sram_printch(' ');
sram_printch('f');
sram_printch('a');
sram_printch('i');
sram_printch('l');
sram_printascii("fail\n");
}
//ddr_print("check image crc32 success--crc value = 0x%x!, count:%d\n",g_crc1, n++);
// sram_printascii("change freq success\n");
@@ -253,7 +246,7 @@ static void __sramfunc rk29_sram_suspend(void)
{
u32 vol;
if ((ddr_debug == 1) || (ddr_debug == 2))
if (ddr_debug == 2)
ddr_testmode();
sram_printch('5');
@@ -418,7 +411,7 @@ static int rk29_pm_enter(suspend_state_t state)
#endif
// memory teseter
if (ddr_debug == 3)
if (ddr_debug != 2)
ddr_testmode();
// dump GPIO INTEN for debug

265
arch/arm/mach-rk29/spi_sram.c
View File

@@ -7,7 +7,21 @@
#include <asm/io.h>
#include <mach/gpio.h>
#include <asm/vfp.h>
#if 1
void __sramfunc sram_printch(char byte);
void __sramfunc printhex(unsigned int hex);
#define sram_printHX(a)
#else
#define sram_printch(a)
#define sram_printHX(a)
#endif
#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
#if defined(CONFIG_RK29_SPI_INSRAM)
@@ -17,7 +31,7 @@
#define SPI_SR_SPEED (2*SPI_MHZ)
#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)
#if defined(CONFIG_MACH_RK29_A22)||defined(CONFIG_MACH_RK29_PHONESDK)||defined(CONFIG_MACH_RK29_TD8801_V2)
#define SRAM_SPI_CH 1
#define SRAM_SPI_CS 1
@@ -85,15 +99,6 @@ SPI_BAUDR,
SPI_SER,
DATE_END,
};
#if 1
void __sramfunc sram_printch(char byte);
void __sramfunc printhex(unsigned int hex);
#define sram_printHX(a)
#else
#define sram_printch(a)
#define sram_printHX(a)
#endif
static u32 __sramdata spi_data[DATE_END]={};
#define sram_spi_dis() spi_writel(spi_readl(SPIM_ENR)&~(0x1<<0),SPIM_ENR)
@@ -105,10 +110,6 @@ void __sramfunc printhex(unsigned int hex);
#define spi_readl(offset) readl(SRAM_SPI_ADDRBASE + offset)
#define spi_writel(v, offset) writel(v, SRAM_SPI_ADDRBASE+ offset)
#define grf_readl(offset) readl(RK29_GRF_BASE + offset)
#define grf_writel(v, offset) do { writel(v, RK29_GRF_BASE + offset); readl(RK29_GRF_BASE + offset); } while (0)
#define sram_udelay(usecs,a) LOOP((usecs)*LOOPS_PER_USEC)
#define SPI_GATE1_MASK 0xCF
@@ -362,6 +363,10 @@ void __sramfunc rk29_suspend_voltage_resume(unsigned int vol)
#endif
/*******************************************gpio*********************************************/
#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
#define PM_GETGPIO_BASE(N) RK29_GPIO##N##_BASE
#define PM_GPIO_DR 0
#define PM_GPIO_DDR 0x4
#define PM_GPIO_INTEN 0x30
__sramdata u32 pm_gpio_base[7]=
{
RK29_GPIO0_BASE,
@@ -410,10 +415,240 @@ void __sramfunc pm_gpio_set(unsigned gpio,eGPIOPinDirection_t direction,eGPIOPin
}
}
#endif
/*****************************************gpio ctr*********************************************/
#if defined(CONFIG_RK29_GPIO_SUSPEND)
#define GRF_GPIO0_DIR 0x000
#define GRF_GPIO1_DIR 0x004
#define GRF_GPIO2_DIR 0x008
#define GRF_GPIO3_DIR 0x00c
#define GRF_GPIO4_DIR 0x010
#define GRF_GPIO5_DIR 0x014
#define GRF_GPIO0_DO 0x018
#define GRF_GPIO1_DO 0x01c
#define GRF_GPIO2_DO 0x020
#define GRF_GPIO3_DO 0x024
#define GRF_GPIO4_DO 0x028
#define GRF_GPIO5_DO 0x02c
#define GRF_GPIO0_EN 0x030
#define GRF_GPIO1_EN 0x034
#define GRF_GPIO2_EN 0x038
#define GRF_GPIO3_EN 0x03c
#define GRF_GPIO4_EN 0x040
#define GRF_GPIO5_EN 0x044
#define GRF_GPIO0L_IOMUX 0x048
#define GRF_GPIO0H_IOMUX 0x04c
#define GRF_GPIO1L_IOMUX 0x050
#define GRF_GPIO1H_IOMUX 0x054
#define GRF_GPIO2L_IOMUX 0x058
#define GRF_GPIO2H_IOMUX 0x05c
#define GRF_GPIO3L_IOMUX 0x060
#define GRF_GPIO3H_IOMUX 0x064
#define GRF_GPIO4L_IOMUX 0x068
#define GRF_GPIO4H_IOMUX 0x06c
#define GRF_GPIO5L_IOMUX 0x070
#define GRF_GPIO5H_IOMUX 0x074
typedef struct GPIO_IOMUX
{
unsigned int GPIOL_IOMUX;
unsigned int GPIOH_IOMUX;
}GPIO_IOMUX_PM;
//GRF Registers
typedef struct REG_FILE_GRF
{
unsigned int GRF_GPIO_DIR[6];
unsigned int GRF_GPIO_DO[6];
unsigned int GRF_GPIO_EN[6];
GPIO_IOMUX_PM GRF_GPIO_IOMUX[6];
unsigned int GRF_GPIO_PULL[7];
} GRF_REG_SAVE;
static GRF_REG_SAVE pm_grf;
int __sramdata crumode;
u32 __sramdata gpio2_pull,gpio6_pull;
//static GRF_REG_SAVE __sramdata pm_grf;
static void pm_keygpio_prepare(void)
{
gpio6_pull = grf_readl(GRF_GPIO6_PULL);
gpio2_pull = grf_readl(GRF_GPIO2_PULL);
}
void pm_keygpio_sdk_suspend(void)
{
pm_keygpio_prepare();
grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
grf_writel(gpio2_pull|0x00000f30,GRF_GPIO2_PULL);
}
void pm_keygpio_sdk_resume(void)
{
grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
grf_writel(gpio2_pull,GRF_GPIO2_PULL);
}
void pm_keygpio_a22_suspend(void)
{
pm_keygpio_prepare();
grf_writel(gpio6_pull|0x7f,GRF_GPIO6_PULL);//key pullup/pulldown disable
grf_writel(gpio2_pull|0x00000900,GRF_GPIO2_PULL);
}
void pm_keygpio_a22_resume(void)
{
grf_writel(gpio6_pull,GRF_GPIO6_PULL);//key pullup/pulldown enable
grf_writel(gpio2_pull,GRF_GPIO2_PULL);
}
static void pm_spi_gpio_prepare(void)
{
pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX = grf_readl(GRF_GPIO1L_IOMUX);
pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX = grf_readl(GRF_GPIO2H_IOMUX);
pm_grf.GRF_GPIO_PULL[1] = grf_readl(GRF_GPIO1_PULL);
pm_grf.GRF_GPIO_PULL[2] = grf_readl(GRF_GPIO2_PULL);
pm_grf.GRF_GPIO_EN[1] = grf_readl(GRF_GPIO1_EN);
pm_grf.GRF_GPIO_EN[2] = grf_readl(GRF_GPIO2_EN);
}
void pm_spi_gpio_suspend(void)
{
int io1L_iomux;
int io2H_iomux;
int io1_pull,io2_pull;
int io1_en,io2_en;
pm_spi_gpio_prepare();
io1L_iomux = grf_readl(GRF_GPIO1L_IOMUX);
io2H_iomux = grf_readl(GRF_GPIO2H_IOMUX);
grf_writel(io1L_iomux&(~((0x03<<6)|(0x03 <<8))), GRF_GPIO1L_IOMUX);
grf_writel(io2H_iomux&0xffff0000, GRF_GPIO2H_IOMUX);
io1_pull = grf_readl(GRF_GPIO1_PULL);
io2_pull = grf_readl(GRF_GPIO2_PULL);
grf_writel(io1_pull|0x18,GRF_GPIO1_PULL);
grf_writel(io2_pull|0x00ff0000,GRF_GPIO2_PULL);
io1_en = grf_readl(GRF_GPIO1_EN);
io2_en = grf_readl(GRF_GPIO2_EN);
grf_writel(io1_en|0x18,GRF_GPIO1_EN);
grf_writel(io2_en|0x00ff0000,GRF_GPIO2_EN);
}
void pm_spi_gpio_resume(void)
{
grf_writel(pm_grf.GRF_GPIO_EN[1],GRF_GPIO1_EN);
grf_writel(pm_grf.GRF_GPIO_EN[2],GRF_GPIO2_EN);
grf_writel(pm_grf.GRF_GPIO_PULL[1],GRF_GPIO1_PULL);
grf_writel(pm_grf.GRF_GPIO_PULL[2],GRF_GPIO2_PULL);
grf_writel(pm_grf.GRF_GPIO_IOMUX[1].GPIOL_IOMUX, GRF_GPIO1L_IOMUX);
grf_writel(pm_grf.GRF_GPIO_IOMUX[2].GPIOH_IOMUX, GRF_GPIO2H_IOMUX);
}
void pm_gpio_suspend(void)
{
pm_spi_gpio_suspend(); // spi pullup/pulldown disable....
#if defined(CONFIG_MACH_RK29_PHONESDK)
{ pm_keygpio_sdk_suspend();// key pullup/pulldown disable.....
}
#endif
#if defined(CONFIG_MACH_RK29_A22)
{ pm_keygpio_a22_suspend();// key pullup/pulldown disable.....
}
#endif
}
void pm_gpio_resume(void)
{
pm_spi_gpio_resume(); // spi pullup/pulldown enable.....
#if defined(CONFIG_MACH_RK29_PHONESDK)
{ pm_keygpio_sdk_resume();// key pullup/pulldown enable.....
}
#endif
#if defined(CONFIG_MACH_RK29_A22)
{ pm_keygpio_a22_resume();// key pullup/pulldown enable.....
}
#endif
}
#else
void pm_gpio_suspend(void)
{}
void pm_gpio_resume(void)
{}
#endif
/*************************************neon powerdomain******************************/
#define vfpreg(_vfp_) #_vfp_
#define fmrx(_vfp_) ({ \
u32 __v; \
asm("mrc p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
: "=r" (__v) : : "cc"); \
__v; \
})
#define fmxr(_vfp_,_var_) \
asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
: : "r" (_var_) : "cc")
#define pmu_read(offset) readl(RK29_PMU_BASE + (offset))
#define pmu_write(offset, value) writel((value), RK29_PMU_BASE + (offset))
#define PMU_PG_CON 0x10
extern void vfp_save_state(void *location, u32 fpexc);
extern void vfp_load_state(void *location, u32 fpexc);
static u64 __sramdata saveptr[33]={};
void neon_powerdomain_off(void)
{
int ret,i=0;
int *p;
p=&saveptr;
unsigned int fpexc = fmrx(FPEXC); //get neon Logic gate
fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
for(i=0;i<34;i++){
vfp_save_state(p,fpexc); //save neon reg,32 D reg,2 control reg
p++;
}
fmxr(FPEXC, fpexc & ~FPEXC_EN); //close neon Logic gate
ret=pmu_read(PMU_PG_CON); //get power domain state
pmu_write(PMU_PG_CON,ret|(0x1<<1)); //powerdomain off neon
}
void neon_powerdomain_on(void)
{
int ret,i=0;
int *p;
p=&saveptr;
ret=pmu_read(PMU_PG_CON); //get power domain state
pmu_write(PMU_PG_CON,ret&~(0x1<<1)); //powerdomain on neon
sram_udelay(5000,24);
unsigned int fpexc = fmrx(FPEXC); //get neon Logic gate
fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
for(i=0;i<34;i++){
vfp_load_state(p,fpexc); //recovery neon reg, 32 D reg,2 control reg
p++;
}
fmxr(FPEXC, fpexc | FPEXC_EN); //open neon Logic gate
}
/*************************************************32k**************************************/
#ifdef CONFIG_RK29_CLK_SWITCH_TO_32K
static int __sramdata crumode;
//static int __sramdata crumode;
void __sramfunc pm_clk_switch_32k(void)
{
int vol;

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