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phonepad:modify tps65910_pre_init to fix rtc bug
This commit is contained in:
lw@rock-chips.com
@@ -39,100 +39,99 @@ int tps65910_pre_init(struct tps65910 *tps65910){
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//gpio_request(PMU_POWER_SLEEP, "NULL");
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//gpio_direction_output(PMU_POWER_SLEEP, GPIO_HIGH);
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val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL2);
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val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL2);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DEVCTRL2 reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DEVCTRL2 reg\n");
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return val;
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}
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/* Set sleep state active high and allow device turn-off after PWRON long press */
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val |= (TPS65910_DEV2_SLEEPSIG_POL | TPS65910_DEV2_PWON_LP_OFF);
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val |= (DEVCTRL2_SLEEPSIG_POL_MASK | DEVCTRL2_PWON_LP_OFF_MASK);
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err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL2, val);
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err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL2, val);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL2 reg\n");
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printk(KERN_ERR "Unable to write TPS65910_DEVCTRL2 reg\n");
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return err;
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}
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#if 1
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/* set PSKIP=0 */
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val = tps65910_reg_read(tps65910, TPS65910_REG_DCDCCTRL);
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val = tps65910_reg_read(tps65910, TPS65910_DCDCCTRL);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return val;
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}
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//val &= ~(1 << 4);
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val &= 0xFC;
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// val |= 0x03;
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err = tps65910_reg_write(tps65910, TPS65910_REG_DCDCCTRL, val);
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val &= ~DEVCTRL_DEV_OFF_MASK;
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val &= ~DEVCTRL_DEV_SLP_MASK;
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err = tps65910_reg_write(tps65910, TPS65910_DCDCCTRL, val);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to write TPS65910_DCDCCTRL reg\n");
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return err;
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}
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#endif
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/* Set the maxinum load current */
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/* VDD1 */
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val = tps65910_reg_read(tps65910, TPS65910_REG_VDD1);
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val = tps65910_reg_read(tps65910, TPS65910_VDD1);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_VDD1 reg\n");
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printk(KERN_ERR "Unable to read TPS65910_VDD1 reg\n");
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return val;
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}
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val |= (1<<5);
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val |= (0x07<<2);
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err = tps65910_reg_write(tps65910, TPS65910_REG_VDD1, val);
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val |= (1<<5); //when 1: 1.5 A
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val |= (0x07<<2); //TSTEP[2:0] = 111 : 2.5 mV/¦Ìs(sampling 3 Mhz/5)
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err = tps65910_reg_write(tps65910, TPS65910_VDD1, val);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_VDD1 reg\n");
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printk(KERN_ERR "Unable to write TPS65910_VDD1 reg\n");
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return err;
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}
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/* VDD2 */
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val = tps65910_reg_read(tps65910, TPS65910_REG_VDD2);
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val = tps65910_reg_read(tps65910, TPS65910_VDD2);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_VDD2 reg\n");
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printk(KERN_ERR "Unable to read TPS65910_VDD2 reg\n");
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return val;
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}
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val |= (1<<5);
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err = tps65910_reg_write(tps65910, TPS65910_REG_VDD2, val);
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val |= (1<<5); //when 1: 1.5 A
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err = tps65910_reg_write(tps65910, TPS65910_VDD2, val);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_VDD2 reg\n");
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printk(KERN_ERR "Unable to write TPS65910_VDD2 reg\n");
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return err;
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}
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/* VIO */
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val = tps65910_reg_read(tps65910, TPS65910_REG_VIO);
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val = tps65910_reg_read(tps65910, TPS65910_VIO);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_VIO reg\n");
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printk(KERN_ERR "Unable to read TPS65910_VIO reg\n");
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return -EIO;
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}
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val |= (1<<6);
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err = tps65910_reg_write(tps65910, TPS65910_REG_VIO, val);
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val |= (1<<6); //when 01: 1.0 A
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err = tps65910_reg_write(tps65910, TPS65910_VIO, val);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_VIO reg\n");
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printk(KERN_ERR "Unable to write TPS65910_VIO reg\n");
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return err;
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}
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#if 1
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/* Mask ALL interrupts */
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err = tps65910_reg_write(tps65910,TPS65910_REG_INT_MSK, 0xFF);
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err = tps65910_reg_write(tps65910,TPS65910_INT_MSK, 0xFF);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK reg\n");
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printk(KERN_ERR "Unable to write TPS65910_INT_MSK reg\n");
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return err;
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}
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err = tps65910_reg_write(tps65910, TPS65910_REG_INT_MSK2, 0x03);
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err = tps65910_reg_write(tps65910, TPS65910_INT_MSK2, 0x03);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_INT_MSK2 reg\n");
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printk(KERN_ERR "Unable to write TPS65910_INT_MSK2 reg\n");
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return err;
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}
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/* Set RTC Power, disable Smart Reflex in DEVCTRL_REG */
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#if 1
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val = 0;
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val |= (TPS65910_SR_CTL_I2C_SEL);
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err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val);
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val |= (DEVCTRL_SR_CTL_I2C_SEL_MASK);
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err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
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if (err) {
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printk(KERN_ERR "Unable to write TPS65910_REG_DEVCTRL reg\n");
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printk(KERN_ERR "Unable to write TPS65910_DEVCTRL reg\n");
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return err;
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}
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printk(KERN_INFO "TPS65910 Set default voltage.\n");
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@@ -141,9 +140,9 @@ int tps65910_pre_init(struct tps65910 *tps65910){
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//read sleep control register for debug
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for(i=0; i<6; i++)
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{
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err = tps65910_reg_read(tps65910, &val, TPS65910_REG_DEVCTRL+i);
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err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return -EIO;
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}
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else
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@@ -154,65 +153,72 @@ int tps65910_pre_init(struct tps65910 *tps65910){
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#if 1
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//sleep control register
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/*set func when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL);
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val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return val;
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}
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val |= (1 << 1);
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err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_REG_VDIG1);
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return err;
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}
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/* open ldo when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_KEEP_LDO_ON);
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val |= (1 << 1);
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err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_VDIG1);
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return err;
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}
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/* open ldo when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_LDO_ON);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return val;
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}
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val &= 0;
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err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_KEEP_LDO_ON, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_REG_VDIG1);
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return err;
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}
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/*set dc mode when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_KEEP_RES_ON);
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val &= 0;
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err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_LDO_ON, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_VDIG1);
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return err;
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}
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/*set dc mode when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_SLEEP_KEEP_RES_ON);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return val;
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}
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val |= 0xff;
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err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_KEEP_RES_ON, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_REG_VDIG1);
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return err;
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}
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/*close ldo when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_REG_SLEEP_SET_LDO_OFF);
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val |= 0xff;
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err = tps65910_reg_write(tps65910, TPS65910_SLEEP_KEEP_RES_ON, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_VDIG1);
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return err;
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}
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/*close ldo when in sleep mode */
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val = tps65910_reg_read(tps65910, TPS65910_SLEEP_SET_LDO_OFF);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return val;
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}
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val |= 0x9B;
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err = tps65910_reg_write(tps65910, TPS65910_REG_SLEEP_SET_LDO_OFF, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_REG_VDIG1);
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return err;
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}
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val |= 0x9B;
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err = tps65910_reg_write(tps65910, TPS65910_SLEEP_SET_LDO_OFF, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_VDIG1);
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return err;
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}
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#endif
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#if 0
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//read sleep control register for debug
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for(i=0; i<6; i++)
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{
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err = tps65910_reg_read(tps65910, &val, TPS65910_REG_DEVCTRL+i);
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err = tps65910_reg_read(tps65910, &val, TPS65910_DEVCTRL+i);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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printk(KERN_ERR "Unable to read TPS65910_DCDCCTRL reg\n");
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return -EIO;
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}
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else
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@@ -620,6 +626,7 @@ static struct tps65910_board tps65910_data = {
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.tps65910_pmic_init_data[TPS65910_REG_VAUX2] = &tps65910_ldo4,
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.tps65910_pmic_init_data[TPS65910_REG_VAUX33] = &tps65910_ldo5,
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.tps65910_pmic_init_data[TPS65910_REG_VMMC] = &tps65910_ldo6,
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};
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@@ -69,7 +69,7 @@
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//定义GPIO的PIN口最大数目。CONFIG_SPI_FPGA_GPIO_NUM表示FPGA的PIN脚数。
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#define ARCH_NR_GPIOS (PIN_BASE + RK30_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM)
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#define ARCH_NR_GPIOS (PIN_BASE + RK30_TOTOL_GPIO_NUM + TCA6424_TOTOL_GPIO_NUM + WM831X_TOTOL_GPIO_NUM + CONFIG_SPI_FPGA_GPIO_NUM+CONFIG_GPIO_WM8994_NUM+CONFIG_GPIO_TPS65910_NUM)
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#define INVALID_GPIO -1
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@@ -239,7 +239,7 @@ static int tps65910_i2c_probe(struct i2c_client *i2c,
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struct tps65910_board *pmic_plat_data;
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struct tps65910_platform_data *init_data;
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int ret = 0;
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pmic_plat_data = dev_get_platdata(&i2c->dev);
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if (!pmic_plat_data)
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return -EINVAL;
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@@ -292,6 +292,7 @@ static int tps65910_i2c_probe(struct i2c_client *i2c,
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goto err;
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}
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}
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printk("%s:irq=%d,irq_base=%d,gpio_base=%d\n",__func__,init_data->irq,init_data->irq_base,pmic_plat_data->gpio_base);
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return ret;
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@@ -310,15 +311,15 @@ int tps65910_device_shutdown(void)
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printk("%s\n",__func__);
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val = tps65910_reg_read(tps65910, TPS65910_REG_DEVCTRL);
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val = tps65910_reg_read(tps65910, TPS65910_DEVCTRL);
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if (val<0) {
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printk(KERN_ERR "Unable to read TPS65910_REG_DCDCCTRL reg\n");
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return -EIO;
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}
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val |= (1 << 3)|(1 << 0);
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val &= ~(1 << 6); //keep rtc
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err = tps65910_reg_write(tps65910, TPS65910_REG_DEVCTRL, val);
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val |= DEVCTRL_DEV_OFF_MASK;
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val &= ~DEVCTRL_CK32K_CTRL_MASK; //keep rtc
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err = tps65910_reg_write(tps65910, TPS65910_DEVCTRL, val);
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if (err) {
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printk(KERN_ERR "Unable to read TPS65910 Reg at offset 0x%x= \
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\n", TPS65910_REG_VDIG1);
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@@ -368,7 +368,7 @@
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#define DCDCCTRL_DCDCCKSYNC_SHIFT 0
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/*Register DEVCTRL (0x80) register.RegisterDescription */
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/*Register DEVCTRL (0x3F) register.RegisterDescription */
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#define DEVCTRL_RTC_PWDN_MASK 0x40
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#define DEVCTRL_RTC_PWDN_SHIFT 6
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#define DEVCTRL_CK32K_CTRL_MASK 0x20
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@@ -385,7 +385,7 @@
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#define DEVCTRL_DEV_OFF_SHIFT 0
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/*Register DEVCTRL2 (0x80) register.RegisterDescription */
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/*Register DEVCTRL2 (0x40) register.RegisterDescription */
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#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
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#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
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#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
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@@ -790,157 +790,7 @@
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/*
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* ----------------------------------------------------------------------------
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* Registers, all 8 bits
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* ----------------------------------------------------------------------------
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*/
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#define TPS65910_REG_SECONDS 0x00
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#define TPS65910_REG_MINUTES 0x01
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#define TPS65910_REG_HOURS 0x02
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#define TPS65910_REG_DAYS 0x03
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#define TPS65910_REG_MONTHS 0x04
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#define TPS65910_REG_YEARS 0x05
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#define TPS65910_REG_WEEKS 0x06
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#define TPS65910_REG_ALARM_SECONDS 0x08
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#define TPS65910_REG_ALARM_MINUTES 0x09
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#define TPS65910_REG_ALARM_HOURS 0x0A
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#define TPS65910_REG_ALARM_DAYS 0x0B
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#define TPS65910_REG_ALARM_MONTHS 0x0C
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#define TPS65910_REG_ALARM_YEARS 0x0D
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#define TPS65910_REG_RTC_CTRL 0x10
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#define TPS65910_REG_RTC_STATUS 0x11
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#define TPS65910_REG_RTC_INTERRUPTS 0x12
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#define TPS65910_REG_RTC_COMP_LSB 0x13
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#define TPS65910_REG_RTC_COMP_MSB 0x14
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#define TPS65910_REG_RTC_RES_PROG 0x15
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#define TPS65910_REG_RTC_RESET_STATUS 0x16
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#define TPS65910_REG_BCK1 0x17
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#define TPS65910_REG_BCK2 0x18
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#define TPS65910_REG_BCK3 0x19
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#define TPS65910_REG_BCK4 0x1A
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#define TPS65910_REG_BCK5 0x1B
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#define TPS65910_REG_PUADEN 0x1C
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||||
#define TPS65910_REG_REF 0x1D
|
||||
|
||||
#define TPS65910_REG_THERM 0x38
|
||||
#define TPS65910_REG_BBCH 0x39
|
||||
|
||||
#define TPS65910_REG_DCDCCTRL 0x3E
|
||||
#define TPS65910_REG_DEVCTRL 0x3F
|
||||
#define TPS65910_REG_DEVCTRL2 0x40
|
||||
#define TPS65910_REG_SLEEP_KEEP_LDO_ON 0x41
|
||||
#define TPS65910_REG_SLEEP_KEEP_RES_ON 0x42
|
||||
#define TPS65910_REG_SLEEP_SET_LDO_OFF 0x43
|
||||
#define TPS65910_REG_SLEEP_SET_RES_OFF 0x44
|
||||
#define TPS65910_REG_EN1_LDO_ASS 0x45
|
||||
#define TPS65910_REG_EN1_SMPS_ASS 0x46
|
||||
#define TPS65910_REG_EN2_LDO_ASS 0x47
|
||||
#define TPS65910_REG_EN2_SMPS_ASS 0x48
|
||||
#define TPS65910_REG_EN3_LDO_ASS 0x49
|
||||
#define TPS65910_REG_SPARE 0x4A
|
||||
|
||||
#define TPS65910_REG_INT_STS 0x50
|
||||
#define TPS65910_REG_INT_MSK 0x51
|
||||
#define TPS65910_REG_INT_STS2 0x52
|
||||
#define TPS65910_REG_INT_MSK2 0x53
|
||||
#define TPS65910_REG_INT_STS3 0x54
|
||||
#define TPS65910_REG_INT_MSK3 0x55
|
||||
|
||||
#define TPS65910_REG_GPIO0 0x60
|
||||
|
||||
#define TPS65910_REG_JTAGVERNUM 0x80
|
||||
|
||||
/* TPS65910 GPIO Specific flags */
|
||||
#define TPS65910_GPIO_INT_FALLING 0
|
||||
#define TPS65910_GPIO_INT_RISING 1
|
||||
|
||||
#define TPS65910_DEBOUNCE_91_5_MS 0
|
||||
#define TPS65910_DEBOUNCE_150_MS 1
|
||||
|
||||
#define TPS65910_GPIO_PUDIS (1 << 3)
|
||||
#define TPS65910_GPIO_CFG_OUTPUT (1 << 2)
|
||||
|
||||
|
||||
|
||||
/* TPS65910 Interrupt events */
|
||||
|
||||
/* RTC Driver */
|
||||
#define TPS65910_RTC_ALARM_IT 0x80
|
||||
#define TPS65910_RTC_PERIOD_IT 0x40
|
||||
|
||||
/*Core Driver */
|
||||
#define TPS65910_HOT_DIE_IT 0x20
|
||||
#define TPS65910_PWRHOLD_IT 0x10
|
||||
#define TPS65910_PWRON_LP_IT 0x08
|
||||
#define TPS65910_PWRON_IT 0x04
|
||||
#define TPS65910_VMBHI_IT 0x02
|
||||
#define TPS65910_VMBGCH_IT 0x01
|
||||
|
||||
/* GPIO driver */
|
||||
#define TPS65910_GPIO_F_IT 0x02
|
||||
#define TPS65910_GPIO_R_IT 0x01
|
||||
|
||||
|
||||
#define TPS65910_VRTC_OFFMASK (1<<3)
|
||||
|
||||
/* Back-up battery charger control */
|
||||
#define TPS65910_BBCHEN 0x01
|
||||
|
||||
/* Back-up battery charger voltage */
|
||||
#define TPS65910_BBSEL_3P0 0x00
|
||||
#define TPS65910_BBSEL_2P52 0x02
|
||||
#define TPS65910_BBSEL_3P15 0x04
|
||||
#define TPS65910_BBSEL_VBAT 0x06
|
||||
|
||||
/* DEVCTRL_REG flags */
|
||||
#define TPS65910_RTC_PWDNN 0x40
|
||||
#define TPS65910_CK32K_CTRL 0x20
|
||||
#define TPS65910_SR_CTL_I2C_SEL 0x10
|
||||
#define TPS65910_DEV_OFF_RST 0x08
|
||||
#define TPS65910_DEV_ON 0x04
|
||||
#define TPS65910_DEV_SLP 0x02
|
||||
#define TPS65910_DEV_OFF 0x01
|
||||
|
||||
/* DEVCTRL2_REG flags */
|
||||
#define TPS65910_DEV2_TSLOT_LENGTH 0x30
|
||||
#define TPS65910_DEV2_SLEEPSIG_POL 0x08
|
||||
#define TPS65910_DEV2_PWON_LP_OFF 0x04
|
||||
#define TPS65910_DEV2_PWON_LP_RST 0x02
|
||||
#define TPS65910_DEV2_IT_POL 0x01
|
||||
|
||||
/* Number of step-down/up converters available */
|
||||
#define TPS65910_NUM_DCDC 4
|
||||
|
||||
/* Number of LDO voltage regulators available */
|
||||
#define TPS65910_NUM_LDO 9
|
||||
|
||||
/* Number of total regulators available */
|
||||
#define TPS65910_NUM_REGULATOR (TPS65910_NUM_DCDC + TPS65910_NUM_LDO)
|
||||
|
||||
|
||||
/* Regulator Supply state */
|
||||
#define SUPPLY_STATE_FLAG 0x03
|
||||
/* OFF States */
|
||||
#define TPS65910_REG_OFF_00 0x00
|
||||
#define TPS65910_REG_OFF_10 0x02
|
||||
/* OHP - on High Power */
|
||||
#define TPS65910_REG_OHP 0x01
|
||||
/* OLP - on Low Power */
|
||||
#define TPS65910_REG_OLP 0x03
|
||||
|
||||
#define TPS65910_MAX_IRQS 10
|
||||
#define TPS65910_VMBDCH_IRQ 0
|
||||
#define TPS65910_VMBHI_IRQ 1
|
||||
#define TPS65910_PWRON_IRQ 2
|
||||
#define TPS65910_PWRON_LP_IRQ 3
|
||||
#define TPS65910_PWRHOLD_IRQ 4
|
||||
#define TPS65910_HOTDIE_IRQ 5
|
||||
#define TPS65910_RTC_ALARM_IRQ 6
|
||||
#define TPS65910_RTC_PERIOD_IRQ 7
|
||||
#define TPS65910_GPIO0_R_IRQ 8
|
||||
#define TPS65910_GPIO0_F_IRQ 9
|
||||
|
||||
|
||||
/**
|
||||
|
||||
Reference in New Issue
Block a user