mirror of
https://github.com/armbian/linux.git
synced 2026-01-06 10:13:00 -08:00
Merge branch 'for-davem' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next
This commit is contained in:
@@ -42,7 +42,7 @@ obj-$(CONFIG_ADM8211) += adm8211.o
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obj-$(CONFIG_MWL8K) += mwl8k.o
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obj-$(CONFIG_IWLWIFI) += iwlwifi/
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obj-$(CONFIG_IWLWIFI_LEGACY) += iwlegacy/
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obj-$(CONFIG_IWLEGACY) += iwlegacy/
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obj-$(CONFIG_RT2X00) += rt2x00/
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obj-$(CONFIG_P54_COMMON) += p54/
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@@ -23,7 +23,7 @@
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obj-$(CONFIG_ATH6KL) := ath6kl.o
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ath6kl-y += debug.o
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ath6kl-y += htc_hif.o
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ath6kl-y += hif.o
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ath6kl-y += htc.o
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ath6kl-y += bmi.o
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ath6kl-y += cfg80211.o
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@@ -196,8 +196,6 @@ int ath6kl_bmi_done(struct ath6kl *ar)
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return ret;
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}
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ath6kl_bmi_cleanup(ar);
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return 0;
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}
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@@ -672,6 +670,11 @@ int ath6kl_bmi_fast_download(struct ath6kl *ar, u32 addr, u8 *buf, u32 len)
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return ret;
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}
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void ath6kl_bmi_reset(struct ath6kl *ar)
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{
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ar->bmi.done_sent = false;
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}
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int ath6kl_bmi_init(struct ath6kl *ar)
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{
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ar->bmi.cmd_buf = kzalloc(MAX_BMI_CMDBUF_SZ, GFP_ATOMIC);
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@@ -230,6 +230,8 @@ struct ath6kl_bmi_target_info {
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int ath6kl_bmi_init(struct ath6kl *ar);
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void ath6kl_bmi_cleanup(struct ath6kl *ar);
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void ath6kl_bmi_reset(struct ath6kl *ar);
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int ath6kl_bmi_done(struct ath6kl *ar);
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int ath6kl_bmi_get_target_info(struct ath6kl *ar,
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struct ath6kl_bmi_target_info *targ_info);
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File diff suppressed because it is too large
Load Diff
@@ -17,23 +17,41 @@
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#ifndef ATH6KL_CFG80211_H
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#define ATH6KL_CFG80211_H
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struct wireless_dev *ath6kl_cfg80211_init(struct device *dev);
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void ath6kl_cfg80211_deinit(struct ath6kl *ar);
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enum ath6kl_cfg_suspend_mode {
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ATH6KL_CFG_SUSPEND_DEEPSLEEP,
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ATH6KL_CFG_SUSPEND_CUTPOWER,
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ATH6KL_CFG_SUSPEND_WOW
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};
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void ath6kl_cfg80211_scan_complete_event(struct ath6kl *ar, int status);
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struct net_device *ath6kl_interface_add(struct ath6kl *ar, char *name,
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enum nl80211_iftype type,
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u8 fw_vif_idx, u8 nw_type);
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int ath6kl_register_ieee80211_hw(struct ath6kl *ar);
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struct ath6kl *ath6kl_core_alloc(struct device *dev);
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void ath6kl_deinit_ieee80211_hw(struct ath6kl *ar);
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void ath6kl_cfg80211_connect_event(struct ath6kl *ar, u16 channel,
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void ath6kl_cfg80211_scan_complete_event(struct ath6kl_vif *vif, bool aborted);
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void ath6kl_cfg80211_connect_event(struct ath6kl_vif *vif, u16 channel,
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u8 *bssid, u16 listen_intvl,
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u16 beacon_intvl,
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enum network_type nw_type,
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u8 beacon_ie_len, u8 assoc_req_len,
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u8 assoc_resp_len, u8 *assoc_info);
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void ath6kl_cfg80211_disconnect_event(struct ath6kl *ar, u8 reason,
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void ath6kl_cfg80211_disconnect_event(struct ath6kl_vif *vif, u8 reason,
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u8 *bssid, u8 assoc_resp_len,
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u8 *assoc_info, u16 proto_reason);
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void ath6kl_cfg80211_tkip_micerr_event(struct ath6kl *ar, u8 keyid,
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void ath6kl_cfg80211_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid,
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bool ismcast);
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int ath6kl_cfg80211_suspend(struct ath6kl *ar,
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enum ath6kl_cfg_suspend_mode mode,
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struct cfg80211_wowlan *wow);
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int ath6kl_cfg80211_resume(struct ath6kl *ar);
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void ath6kl_cfg80211_stop(struct ath6kl *ar);
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#endif /* ATH6KL_CFG80211_H */
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@@ -23,8 +23,6 @@
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extern int ath6kl_printk(const char *level, const char *fmt, ...);
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#define A_CACHE_LINE_PAD 128
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/*
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* Reflects the version of binary interface exposed by ATH6KL target
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* firmware. Needs to be incremented by 1 for any change in the firmware
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@@ -78,20 +76,10 @@ enum crypto_type {
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struct htc_endpoint_credit_dist;
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struct ath6kl;
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enum htc_credit_dist_reason;
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struct htc_credit_state_info;
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struct ath6kl_htc_credit_info;
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int ath6k_setup_credit_dist(void *htc_handle,
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struct htc_credit_state_info *cred_info);
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void ath6k_credit_distribute(struct htc_credit_state_info *cred_inf,
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struct list_head *epdist_list,
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enum htc_credit_dist_reason reason);
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void ath6k_credit_init(struct htc_credit_state_info *cred_inf,
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struct list_head *ep_list,
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int tot_credits);
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void ath6k_seek_credits(struct htc_credit_state_info *cred_inf,
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struct htc_endpoint_credit_dist *ep_dist);
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struct ath6kl *ath6kl_core_alloc(struct device *sdev);
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int ath6kl_core_init(struct ath6kl *ar);
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int ath6kl_unavail_ev(struct ath6kl *ar);
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void ath6kl_core_cleanup(struct ath6kl *ar);
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struct sk_buff *ath6kl_buf_alloc(int size);
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#endif /* COMMON_H */
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@@ -166,6 +166,7 @@ struct ath6kl_fw_ie {
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#define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1)
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#define ATH6KL_CONF_ENABLE_11N BIT(2)
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#define ATH6KL_CONF_ENABLE_TX_BURST BIT(3)
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#define ATH6KL_CONF_SUSPEND_CUTPOWER BIT(4)
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enum wlan_low_pwr_state {
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WLAN_POWER_STATE_ON,
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@@ -380,40 +381,33 @@ struct ath6kl_req_key {
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u8 key_len;
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};
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/* Flag info */
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||||
#define WMI_ENABLED 0
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||||
#define WMI_READY 1
|
||||
#define CONNECTED 2
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||||
#define STATS_UPDATE_PEND 3
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#define CONNECT_PEND 4
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||||
#define WMM_ENABLED 5
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#define NETQ_STOPPED 6
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#define WMI_CTRL_EP_FULL 7
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#define DTIM_EXPIRED 8
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#define DESTROY_IN_PROGRESS 9
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#define NETDEV_REGISTERED 10
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#define SKIP_SCAN 11
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#define WLAN_ENABLED 12
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#define TESTMODE 13
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#define CLEAR_BSSFILTER_ON_BEACON 14
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#define DTIM_PERIOD_AVAIL 15
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#define MAX_NUM_VIF 1
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struct ath6kl {
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struct device *dev;
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struct net_device *net_dev;
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struct ath6kl_bmi bmi;
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const struct ath6kl_hif_ops *hif_ops;
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struct wmi *wmi;
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int tx_pending[ENDPOINT_MAX];
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int total_tx_data_pend;
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struct htc_target *htc_target;
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void *hif_priv;
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spinlock_t lock;
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struct semaphore sem;
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/* vif flags info */
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enum ath6kl_vif_state {
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CONNECTED,
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CONNECT_PEND,
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WMM_ENABLED,
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NETQ_STOPPED,
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DTIM_EXPIRED,
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NETDEV_REGISTERED,
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CLEAR_BSSFILTER_ON_BEACON,
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DTIM_PERIOD_AVAIL,
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WLAN_ENABLED,
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STATS_UPDATE_PEND,
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};
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struct ath6kl_vif {
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struct list_head list;
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struct wireless_dev wdev;
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struct net_device *ndev;
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struct ath6kl *ar;
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/* Lock to protect vif specific net_stats and flags */
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spinlock_t if_lock;
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u8 fw_vif_idx;
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unsigned long flags;
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int ssid_len;
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u8 ssid[IEEE80211_MAX_SSID_LEN];
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u8 next_mode;
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u8 nw_type;
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u8 dot11_auth_mode;
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u8 auth_mode;
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u8 prwise_crypto;
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@@ -421,21 +415,83 @@ struct ath6kl {
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u8 grp_crypto;
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u8 grp_crypto_len;
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u8 def_txkey_index;
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struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
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u8 next_mode;
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u8 nw_type;
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u8 bssid[ETH_ALEN];
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u8 req_bssid[ETH_ALEN];
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u16 ch_hint;
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u16 bss_ch;
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struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
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struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
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struct aggr_info *aggr_cntxt;
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struct timer_list disconnect_timer;
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struct cfg80211_scan_request *scan_req;
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enum sme_state sme_state;
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int reconnect_flag;
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u32 last_roc_id;
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u32 last_cancel_roc_id;
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u32 send_action_id;
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bool probe_req_report;
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u16 next_chan;
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u16 assoc_bss_beacon_int;
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u8 assoc_bss_dtim_period;
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struct net_device_stats net_stats;
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struct target_stats target_stats;
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};
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#define WOW_LIST_ID 0
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#define WOW_HOST_REQ_DELAY 500 /* ms */
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/* Flag info */
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enum ath6kl_dev_state {
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WMI_ENABLED,
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WMI_READY,
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WMI_CTRL_EP_FULL,
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TESTMODE,
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DESTROY_IN_PROGRESS,
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SKIP_SCAN,
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ROAM_TBL_PEND,
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FIRST_BOOT,
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};
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enum ath6kl_state {
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ATH6KL_STATE_OFF,
|
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ATH6KL_STATE_ON,
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ATH6KL_STATE_DEEPSLEEP,
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||||
ATH6KL_STATE_CUTPOWER,
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||||
ATH6KL_STATE_WOW,
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};
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||||
|
||||
struct ath6kl {
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struct device *dev;
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struct wiphy *wiphy;
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enum ath6kl_state state;
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struct ath6kl_bmi bmi;
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const struct ath6kl_hif_ops *hif_ops;
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struct wmi *wmi;
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int tx_pending[ENDPOINT_MAX];
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int total_tx_data_pend;
|
||||
struct htc_target *htc_target;
|
||||
void *hif_priv;
|
||||
struct list_head vif_list;
|
||||
/* Lock to avoid race in vif_list entries among add/del/traverse */
|
||||
spinlock_t list_lock;
|
||||
u8 num_vif;
|
||||
u8 max_norm_iface;
|
||||
u8 avail_idx_map;
|
||||
spinlock_t lock;
|
||||
struct semaphore sem;
|
||||
u16 listen_intvl_b;
|
||||
u16 listen_intvl_t;
|
||||
u8 lrssi_roam_threshold;
|
||||
struct ath6kl_version version;
|
||||
u32 target_type;
|
||||
u8 tx_pwr;
|
||||
struct net_device_stats net_stats;
|
||||
struct target_stats target_stats;
|
||||
struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
|
||||
u8 ibss_ps_enable;
|
||||
bool ibss_if_active;
|
||||
u8 node_num;
|
||||
u8 next_ep_id;
|
||||
struct ath6kl_cookie *cookie_list;
|
||||
@@ -446,7 +502,7 @@ struct ath6kl {
|
||||
u8 hiac_stream_active_pri;
|
||||
u8 ep2ac_map[ENDPOINT_MAX];
|
||||
enum htc_endpoint_id ctrl_ep;
|
||||
struct htc_credit_state_info credit_state_info;
|
||||
struct ath6kl_htc_credit_info credit_state_info;
|
||||
u32 connect_ctrl_flags;
|
||||
u32 user_key_ctrl;
|
||||
u8 usr_bss_filter;
|
||||
@@ -456,18 +512,13 @@ struct ath6kl {
|
||||
struct sk_buff_head mcastpsq;
|
||||
spinlock_t mcastpsq_lock;
|
||||
u8 intra_bss;
|
||||
struct aggr_info *aggr_cntxt;
|
||||
struct wmi_ap_mode_stat ap_stats;
|
||||
u8 ap_country_code[3];
|
||||
struct list_head amsdu_rx_buffer_queue;
|
||||
struct timer_list disconnect_timer;
|
||||
u8 rx_meta_ver;
|
||||
struct wireless_dev *wdev;
|
||||
struct cfg80211_scan_request *scan_req;
|
||||
struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
|
||||
enum sme_state sme_state;
|
||||
enum wlan_low_pwr_state wlan_pwr_state;
|
||||
struct wmi_scan_params_cmd sc_params;
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
#define AR_MCAST_FILTER_MAC_ADDR_SIZE 4
|
||||
struct {
|
||||
void *rx_report;
|
||||
@@ -487,7 +538,6 @@ struct ath6kl {
|
||||
struct ath6kl_mbox_info mbox_info;
|
||||
|
||||
struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
|
||||
int reconnect_flag;
|
||||
unsigned long flag;
|
||||
|
||||
u8 *fw_board;
|
||||
@@ -508,13 +558,7 @@ struct ath6kl {
|
||||
|
||||
struct dentry *debugfs_phy;
|
||||
|
||||
u32 send_action_id;
|
||||
bool probe_req_report;
|
||||
u16 next_chan;
|
||||
|
||||
bool p2p;
|
||||
u16 assoc_bss_beacon_int;
|
||||
u8 assoc_bss_dtim_period;
|
||||
|
||||
#ifdef CONFIG_ATH6KL_DEBUG
|
||||
struct {
|
||||
@@ -529,23 +573,19 @@ struct ath6kl {
|
||||
struct {
|
||||
unsigned int invalid_rate;
|
||||
} war_stats;
|
||||
|
||||
u8 *roam_tbl;
|
||||
unsigned int roam_tbl_len;
|
||||
|
||||
u8 keepalive;
|
||||
u8 disc_timeout;
|
||||
} debug;
|
||||
#endif /* CONFIG_ATH6KL_DEBUG */
|
||||
};
|
||||
|
||||
static inline void *ath6kl_priv(struct net_device *dev)
|
||||
{
|
||||
return wdev_priv(dev->ieee80211_ptr);
|
||||
}
|
||||
|
||||
static inline void ath6kl_deposit_credit_to_ep(struct htc_credit_state_info
|
||||
*cred_info,
|
||||
struct htc_endpoint_credit_dist
|
||||
*ep_dist, int credits)
|
||||
{
|
||||
ep_dist->credits += credits;
|
||||
ep_dist->cred_assngd += credits;
|
||||
cred_info->cur_free_credits -= credits;
|
||||
return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
|
||||
}
|
||||
|
||||
static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
|
||||
@@ -561,7 +601,6 @@ static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
|
||||
return addr;
|
||||
}
|
||||
|
||||
void ath6kl_destroy(struct net_device *dev, unsigned int unregister);
|
||||
int ath6kl_configure_target(struct ath6kl *ar);
|
||||
void ath6kl_detect_error(unsigned long ptr);
|
||||
void disconnect_timer_handler(unsigned long ptr);
|
||||
@@ -579,10 +618,8 @@ int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
|
||||
int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
|
||||
int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
|
||||
int ath6kl_read_fwlogs(struct ath6kl *ar);
|
||||
void ath6kl_init_profile_info(struct ath6kl *ar);
|
||||
void ath6kl_init_profile_info(struct ath6kl_vif *vif);
|
||||
void ath6kl_tx_data_cleanup(struct ath6kl *ar);
|
||||
void ath6kl_stop_endpoint(struct net_device *dev, bool keep_profile,
|
||||
bool get_dbglogs);
|
||||
|
||||
struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
|
||||
void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
|
||||
@@ -598,40 +635,49 @@ struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
|
||||
void aggr_module_destroy(struct aggr_info *aggr_info);
|
||||
void aggr_reset_state(struct aggr_info *aggr_info);
|
||||
|
||||
struct ath6kl_sta *ath6kl_find_sta(struct ath6kl *ar, u8 * node_addr);
|
||||
struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 * node_addr);
|
||||
struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
|
||||
|
||||
void ath6kl_ready_event(void *devt, u8 * datap, u32 sw_ver, u32 abi_ver);
|
||||
int ath6kl_control_tx(void *devt, struct sk_buff *skb,
|
||||
enum htc_endpoint_id eid);
|
||||
void ath6kl_connect_event(struct ath6kl *ar, u16 channel,
|
||||
void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
|
||||
u8 *bssid, u16 listen_int,
|
||||
u16 beacon_int, enum network_type net_type,
|
||||
u8 beacon_ie_len, u8 assoc_req_len,
|
||||
u8 assoc_resp_len, u8 *assoc_info);
|
||||
void ath6kl_connect_ap_mode_bss(struct ath6kl *ar, u16 channel);
|
||||
void ath6kl_connect_ap_mode_sta(struct ath6kl *ar, u16 aid, u8 *mac_addr,
|
||||
void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
|
||||
void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
|
||||
u8 keymgmt, u8 ucipher, u8 auth,
|
||||
u8 assoc_req_len, u8 *assoc_info);
|
||||
void ath6kl_disconnect_event(struct ath6kl *ar, u8 reason,
|
||||
void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
|
||||
u8 *bssid, u8 assoc_resp_len,
|
||||
u8 *assoc_info, u16 prot_reason_status);
|
||||
void ath6kl_tkip_micerr_event(struct ath6kl *ar, u8 keyid, bool ismcast);
|
||||
void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
|
||||
void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
|
||||
void ath6kl_scan_complete_evt(struct ath6kl *ar, int status);
|
||||
void ath6kl_tgt_stats_event(struct ath6kl *ar, u8 *ptr, u32 len);
|
||||
void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
|
||||
void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
|
||||
void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
|
||||
enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
|
||||
|
||||
void ath6kl_pspoll_event(struct ath6kl *ar, u8 aid);
|
||||
void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
|
||||
|
||||
void ath6kl_dtimexpiry_event(struct ath6kl *ar);
|
||||
void ath6kl_disconnect(struct ath6kl *ar);
|
||||
void ath6kl_deep_sleep_enable(struct ath6kl *ar);
|
||||
void aggr_recv_delba_req_evt(struct ath6kl *ar, u8 tid);
|
||||
void aggr_recv_addba_req_evt(struct ath6kl *ar, u8 tid, u16 seq_no,
|
||||
void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
|
||||
void ath6kl_disconnect(struct ath6kl_vif *vif);
|
||||
void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
|
||||
void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
|
||||
u8 win_sz);
|
||||
void ath6kl_wakeup_event(void *dev);
|
||||
void ath6kl_target_failure(struct ath6kl *ar);
|
||||
|
||||
void ath6kl_reset_device(struct ath6kl *ar, u32 target_type,
|
||||
bool wait_fot_compltn, bool cold_reset);
|
||||
void ath6kl_init_control_info(struct ath6kl_vif *vif);
|
||||
void ath6kl_deinit_if_data(struct ath6kl_vif *vif);
|
||||
void ath6kl_core_free(struct ath6kl *ar);
|
||||
struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
|
||||
void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready);
|
||||
int ath6kl_init_hw_start(struct ath6kl *ar);
|
||||
int ath6kl_init_hw_stop(struct ath6kl *ar);
|
||||
void ath6kl_check_wow_status(struct ath6kl *ar);
|
||||
|
||||
#endif /* CORE_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -17,19 +17,19 @@
|
||||
#ifndef DEBUG_H
|
||||
#define DEBUG_H
|
||||
|
||||
#include "htc_hif.h"
|
||||
#include "hif.h"
|
||||
|
||||
enum ATH6K_DEBUG_MASK {
|
||||
ATH6KL_DBG_WLAN_CONNECT = BIT(0), /* wlan connect */
|
||||
ATH6KL_DBG_WLAN_SCAN = BIT(1), /* wlan scan */
|
||||
ATH6KL_DBG_CREDIT = BIT(0),
|
||||
/* hole */
|
||||
ATH6KL_DBG_WLAN_TX = BIT(2), /* wlan tx */
|
||||
ATH6KL_DBG_WLAN_RX = BIT(3), /* wlan rx */
|
||||
ATH6KL_DBG_BMI = BIT(4), /* bmi tracing */
|
||||
ATH6KL_DBG_HTC_SEND = BIT(5), /* htc send */
|
||||
ATH6KL_DBG_HTC_RECV = BIT(6), /* htc recv */
|
||||
ATH6KL_DBG_HTC = BIT(5),
|
||||
ATH6KL_DBG_HIF = BIT(6),
|
||||
ATH6KL_DBG_IRQ = BIT(7), /* interrupt processing */
|
||||
ATH6KL_DBG_PM = BIT(8), /* power management */
|
||||
ATH6KL_DBG_WLAN_NODE = BIT(9), /* general wlan node tracing */
|
||||
/* hole */
|
||||
/* hole */
|
||||
ATH6KL_DBG_WMI = BIT(10), /* wmi tracing */
|
||||
ATH6KL_DBG_TRC = BIT(11), /* generic func tracing */
|
||||
ATH6KL_DBG_SCATTER = BIT(12), /* hif scatter tracing */
|
||||
@@ -40,6 +40,7 @@ enum ATH6K_DEBUG_MASK {
|
||||
ATH6KL_DBG_SDIO_DUMP = BIT(17),
|
||||
ATH6KL_DBG_BOOT = BIT(18), /* driver init and fw boot */
|
||||
ATH6KL_DBG_WMI_DUMP = BIT(19),
|
||||
ATH6KL_DBG_SUSPEND = BIT(20),
|
||||
ATH6KL_DBG_ANY = 0xffffffff /* enable all logs */
|
||||
};
|
||||
|
||||
@@ -90,6 +91,10 @@ void ath6kl_dump_registers(struct ath6kl_device *dev,
|
||||
void dump_cred_dist_stats(struct htc_target *target);
|
||||
void ath6kl_debug_fwlog_event(struct ath6kl *ar, const void *buf, size_t len);
|
||||
void ath6kl_debug_war(struct ath6kl *ar, enum ath6kl_war war);
|
||||
int ath6kl_debug_roam_tbl_event(struct ath6kl *ar, const void *buf,
|
||||
size_t len);
|
||||
void ath6kl_debug_set_keepalive(struct ath6kl *ar, u8 keepalive);
|
||||
void ath6kl_debug_set_disconnect_timeout(struct ath6kl *ar, u8 timeout);
|
||||
int ath6kl_debug_init(struct ath6kl *ar);
|
||||
void ath6kl_debug_cleanup(struct ath6kl *ar);
|
||||
|
||||
@@ -125,6 +130,21 @@ static inline void ath6kl_debug_war(struct ath6kl *ar, enum ath6kl_war war)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath6kl_debug_roam_tbl_event(struct ath6kl *ar,
|
||||
const void *buf, size_t len)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ath6kl_debug_set_keepalive(struct ath6kl *ar, u8 keepalive)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void ath6kl_debug_set_disconnect_timeout(struct ath6kl *ar,
|
||||
u8 timeout)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int ath6kl_debug_init(struct ath6kl *ar)
|
||||
{
|
||||
return 0;
|
||||
|
||||
@@ -18,10 +18,16 @@
|
||||
#define HIF_OPS_H
|
||||
|
||||
#include "hif.h"
|
||||
#include "debug.h"
|
||||
|
||||
static inline int hif_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
|
||||
u32 len, u32 request)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF,
|
||||
"hif %s sync addr 0x%x buf 0x%p len %d request 0x%x\n",
|
||||
(request & HIF_WRITE) ? "write" : "read",
|
||||
addr, buf, len, request);
|
||||
|
||||
return ar->hif_ops->read_write_sync(ar, addr, buf, len, request);
|
||||
}
|
||||
|
||||
@@ -29,16 +35,24 @@ static inline int hif_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
|
||||
u32 length, u32 request,
|
||||
struct htc_packet *packet)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF,
|
||||
"hif write async addr 0x%x buf 0x%p len %d request 0x%x\n",
|
||||
address, buffer, length, request);
|
||||
|
||||
return ar->hif_ops->write_async(ar, address, buffer, length,
|
||||
request, packet);
|
||||
}
|
||||
static inline void ath6kl_hif_irq_enable(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif irq enable\n");
|
||||
|
||||
return ar->hif_ops->irq_enable(ar);
|
||||
}
|
||||
|
||||
static inline void ath6kl_hif_irq_disable(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif irq disable\n");
|
||||
|
||||
return ar->hif_ops->irq_disable(ar);
|
||||
}
|
||||
|
||||
@@ -69,9 +83,40 @@ static inline void ath6kl_hif_cleanup_scatter(struct ath6kl *ar)
|
||||
return ar->hif_ops->cleanup_scatter(ar);
|
||||
}
|
||||
|
||||
static inline int ath6kl_hif_suspend(struct ath6kl *ar)
|
||||
static inline int ath6kl_hif_suspend(struct ath6kl *ar,
|
||||
struct cfg80211_wowlan *wow)
|
||||
{
|
||||
return ar->hif_ops->suspend(ar);
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif suspend\n");
|
||||
|
||||
return ar->hif_ops->suspend(ar, wow);
|
||||
}
|
||||
|
||||
static inline int ath6kl_hif_resume(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif resume\n");
|
||||
|
||||
return ar->hif_ops->resume(ar);
|
||||
}
|
||||
|
||||
static inline int ath6kl_hif_power_on(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif power on\n");
|
||||
|
||||
return ar->hif_ops->power_on(ar);
|
||||
}
|
||||
|
||||
static inline int ath6kl_hif_power_off(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif power off\n");
|
||||
|
||||
return ar->hif_ops->power_off(ar);
|
||||
}
|
||||
|
||||
static inline void ath6kl_hif_stop(struct ath6kl *ar)
|
||||
{
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif stop\n");
|
||||
|
||||
ar->hif_ops->stop(ar);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -13,18 +13,19 @@
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
#include "hif.h"
|
||||
|
||||
#include "core.h"
|
||||
#include "target.h"
|
||||
#include "hif-ops.h"
|
||||
#include "htc_hif.h"
|
||||
#include "debug.h"
|
||||
|
||||
#define MAILBOX_FOR_BLOCK_SIZE 1
|
||||
|
||||
#define ATH6KL_TIME_QUANTUM 10 /* in ms */
|
||||
|
||||
static int ath6kldev_cp_scat_dma_buf(struct hif_scatter_req *req, bool from_dma)
|
||||
static int ath6kl_hif_cp_scat_dma_buf(struct hif_scatter_req *req,
|
||||
bool from_dma)
|
||||
{
|
||||
u8 *buf;
|
||||
int i;
|
||||
@@ -46,12 +47,11 @@ static int ath6kldev_cp_scat_dma_buf(struct hif_scatter_req *req, bool from_dma)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ath6kldev_rw_comp_handler(void *context, int status)
|
||||
int ath6kl_hif_rw_comp_handler(void *context, int status)
|
||||
{
|
||||
struct htc_packet *packet = context;
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_HTC_RECV,
|
||||
"ath6kldev_rw_comp_handler (pkt:0x%p , status: %d\n",
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif rw completion pkt 0x%p status %d\n",
|
||||
packet, status);
|
||||
|
||||
packet->status = status;
|
||||
@@ -59,30 +59,83 @@ int ath6kldev_rw_comp_handler(void *context, int status)
|
||||
|
||||
return 0;
|
||||
}
|
||||
#define REG_DUMP_COUNT_AR6003 60
|
||||
#define REGISTER_DUMP_LEN_MAX 60
|
||||
|
||||
static int ath6kldev_proc_dbg_intr(struct ath6kl_device *dev)
|
||||
static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar)
|
||||
{
|
||||
__le32 regdump_val[REGISTER_DUMP_LEN_MAX];
|
||||
u32 i, address, regdump_addr = 0;
|
||||
int ret;
|
||||
|
||||
if (ar->target_type != TARGET_TYPE_AR6003)
|
||||
return;
|
||||
|
||||
/* the reg dump pointer is copied to the host interest area */
|
||||
address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state));
|
||||
address = TARG_VTOP(ar->target_type, address);
|
||||
|
||||
/* read RAM location through diagnostic window */
|
||||
ret = ath6kl_diag_read32(ar, address, ®dump_addr);
|
||||
|
||||
if (ret || !regdump_addr) {
|
||||
ath6kl_warn("failed to get ptr to register dump area: %d\n",
|
||||
ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n",
|
||||
regdump_addr);
|
||||
regdump_addr = TARG_VTOP(ar->target_type, regdump_addr);
|
||||
|
||||
/* fetch register dump data */
|
||||
ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0],
|
||||
REG_DUMP_COUNT_AR6003 * (sizeof(u32)));
|
||||
if (ret) {
|
||||
ath6kl_warn("failed to get register dump: %d\n", ret);
|
||||
return;
|
||||
}
|
||||
|
||||
ath6kl_info("crash dump:\n");
|
||||
ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version,
|
||||
ar->wiphy->fw_version);
|
||||
|
||||
BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4);
|
||||
|
||||
for (i = 0; i < REG_DUMP_COUNT_AR6003 / 4; i++) {
|
||||
ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n",
|
||||
4 * i,
|
||||
le32_to_cpu(regdump_val[i]),
|
||||
le32_to_cpu(regdump_val[i + 1]),
|
||||
le32_to_cpu(regdump_val[i + 2]),
|
||||
le32_to_cpu(regdump_val[i + 3]));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static int ath6kl_hif_proc_dbg_intr(struct ath6kl_device *dev)
|
||||
{
|
||||
u32 dummy;
|
||||
int status;
|
||||
int ret;
|
||||
|
||||
ath6kl_err("target debug interrupt\n");
|
||||
|
||||
ath6kl_target_failure(dev->ar);
|
||||
ath6kl_warn("firmware crashed\n");
|
||||
|
||||
/*
|
||||
* read counter to clear the interrupt, the debug error interrupt is
|
||||
* counter 0.
|
||||
*/
|
||||
status = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS,
|
||||
ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS,
|
||||
(u8 *)&dummy, 4, HIF_RD_SYNC_BYTE_INC);
|
||||
if (status)
|
||||
WARN_ON(1);
|
||||
if (ret)
|
||||
ath6kl_warn("Failed to clear debug interrupt: %d\n", ret);
|
||||
|
||||
return status;
|
||||
ath6kl_hif_dump_fw_crash(dev->ar);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* mailbox recv message polling */
|
||||
int ath6kldev_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
|
||||
int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
|
||||
int timeout)
|
||||
{
|
||||
struct ath6kl_irq_proc_registers *rg;
|
||||
@@ -118,7 +171,7 @@ int ath6kldev_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
|
||||
|
||||
/* delay a little */
|
||||
mdelay(ATH6KL_TIME_QUANTUM);
|
||||
ath6kl_dbg(ATH6KL_DBG_HTC_RECV, "retry mbox poll : %d\n", i);
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif retry mbox poll try %d\n", i);
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
@@ -131,7 +184,7 @@ int ath6kldev_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
|
||||
* Target failure handler will be called in case of
|
||||
* an assert.
|
||||
*/
|
||||
ath6kldev_proc_dbg_intr(dev);
|
||||
ath6kl_hif_proc_dbg_intr(dev);
|
||||
}
|
||||
|
||||
return status;
|
||||
@@ -141,11 +194,14 @@ int ath6kldev_poll_mboxmsg_rx(struct ath6kl_device *dev, u32 *lk_ahd,
|
||||
* Disable packet reception (used in case the host runs out of buffers)
|
||||
* using the interrupt enable registers through the host I/F
|
||||
*/
|
||||
int ath6kldev_rx_control(struct ath6kl_device *dev, bool enable_rx)
|
||||
int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx)
|
||||
{
|
||||
struct ath6kl_irq_enable_reg regs;
|
||||
int status = 0;
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif rx %s\n",
|
||||
enable_rx ? "enable" : "disable");
|
||||
|
||||
/* take the lock to protect interrupt enable shadows */
|
||||
spin_lock_bh(&dev->lock);
|
||||
|
||||
@@ -168,7 +224,7 @@ int ath6kldev_rx_control(struct ath6kl_device *dev, bool enable_rx)
|
||||
return status;
|
||||
}
|
||||
|
||||
int ath6kldev_submit_scat_req(struct ath6kl_device *dev,
|
||||
int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
|
||||
struct hif_scatter_req *scat_req, bool read)
|
||||
{
|
||||
int status = 0;
|
||||
@@ -185,14 +241,14 @@ int ath6kldev_submit_scat_req(struct ath6kl_device *dev,
|
||||
dev->ar->mbox_info.htc_addr;
|
||||
}
|
||||
|
||||
ath6kl_dbg((ATH6KL_DBG_HTC_RECV | ATH6KL_DBG_HTC_SEND),
|
||||
"ath6kldev_submit_scat_req, entries: %d, total len: %d mbox:0x%X (mode: %s : %s)\n",
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF,
|
||||
"hif submit scatter request entries %d len %d mbox 0x%x %s %s\n",
|
||||
scat_req->scat_entries, scat_req->len,
|
||||
scat_req->addr, !read ? "async" : "sync",
|
||||
(read) ? "rd" : "wr");
|
||||
|
||||
if (!read && scat_req->virt_scat) {
|
||||
status = ath6kldev_cp_scat_dma_buf(scat_req, false);
|
||||
status = ath6kl_hif_cp_scat_dma_buf(scat_req, false);
|
||||
if (status) {
|
||||
scat_req->status = status;
|
||||
scat_req->complete(dev->ar->htc_target, scat_req);
|
||||
@@ -207,13 +263,13 @@ int ath6kldev_submit_scat_req(struct ath6kl_device *dev,
|
||||
scat_req->status = status;
|
||||
if (!status && scat_req->virt_scat)
|
||||
scat_req->status =
|
||||
ath6kldev_cp_scat_dma_buf(scat_req, true);
|
||||
ath6kl_hif_cp_scat_dma_buf(scat_req, true);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int ath6kldev_proc_counter_intr(struct ath6kl_device *dev)
|
||||
static int ath6kl_hif_proc_counter_intr(struct ath6kl_device *dev)
|
||||
{
|
||||
u8 counter_int_status;
|
||||
|
||||
@@ -232,12 +288,12 @@ static int ath6kldev_proc_counter_intr(struct ath6kl_device *dev)
|
||||
* the debug assertion counter interrupt.
|
||||
*/
|
||||
if (counter_int_status & ATH6KL_TARGET_DEBUG_INTR_MASK)
|
||||
return ath6kldev_proc_dbg_intr(dev);
|
||||
return ath6kl_hif_proc_dbg_intr(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ath6kldev_proc_err_intr(struct ath6kl_device *dev)
|
||||
static int ath6kl_hif_proc_err_intr(struct ath6kl_device *dev)
|
||||
{
|
||||
int status;
|
||||
u8 error_int_status;
|
||||
@@ -282,7 +338,7 @@ static int ath6kldev_proc_err_intr(struct ath6kl_device *dev)
|
||||
return status;
|
||||
}
|
||||
|
||||
static int ath6kldev_proc_cpu_intr(struct ath6kl_device *dev)
|
||||
static int ath6kl_hif_proc_cpu_intr(struct ath6kl_device *dev)
|
||||
{
|
||||
int status;
|
||||
u8 cpu_int_status;
|
||||
@@ -417,7 +473,7 @@ static int proc_pending_irqs(struct ath6kl_device *dev, bool *done)
|
||||
* we rapidly pull packets.
|
||||
*/
|
||||
status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt,
|
||||
&lk_ahd, &fetched);
|
||||
lk_ahd, &fetched);
|
||||
if (status)
|
||||
goto out;
|
||||
|
||||
@@ -436,21 +492,21 @@ static int proc_pending_irqs(struct ath6kl_device *dev, bool *done)
|
||||
|
||||
if (MS(HOST_INT_STATUS_CPU, host_int_status)) {
|
||||
/* CPU Interrupt */
|
||||
status = ath6kldev_proc_cpu_intr(dev);
|
||||
status = ath6kl_hif_proc_cpu_intr(dev);
|
||||
if (status)
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (MS(HOST_INT_STATUS_ERROR, host_int_status)) {
|
||||
/* Error Interrupt */
|
||||
status = ath6kldev_proc_err_intr(dev);
|
||||
status = ath6kl_hif_proc_err_intr(dev);
|
||||
if (status)
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (MS(HOST_INT_STATUS_COUNTER, host_int_status))
|
||||
/* Counter Interrupt */
|
||||
status = ath6kldev_proc_counter_intr(dev);
|
||||
status = ath6kl_hif_proc_counter_intr(dev);
|
||||
|
||||
out:
|
||||
/*
|
||||
@@ -479,9 +535,10 @@ out:
|
||||
}
|
||||
|
||||
/* interrupt handler, kicks off all interrupt processing */
|
||||
int ath6kldev_intr_bh_handler(struct ath6kl *ar)
|
||||
int ath6kl_hif_intr_bh_handler(struct ath6kl *ar)
|
||||
{
|
||||
struct ath6kl_device *dev = ar->htc_target->dev;
|
||||
unsigned long timeout;
|
||||
int status = 0;
|
||||
bool done = false;
|
||||
|
||||
@@ -495,7 +552,8 @@ int ath6kldev_intr_bh_handler(struct ath6kl *ar)
|
||||
* IRQ processing is synchronous, interrupt status registers can be
|
||||
* re-read.
|
||||
*/
|
||||
while (!done) {
|
||||
timeout = jiffies + msecs_to_jiffies(ATH6KL_HIF_COMMUNICATION_TIMEOUT);
|
||||
while (time_before(jiffies, timeout) && !done) {
|
||||
status = proc_pending_irqs(dev, &done);
|
||||
if (status)
|
||||
break;
|
||||
@@ -504,7 +562,7 @@ int ath6kldev_intr_bh_handler(struct ath6kl *ar)
|
||||
return status;
|
||||
}
|
||||
|
||||
static int ath6kldev_enable_intrs(struct ath6kl_device *dev)
|
||||
static int ath6kl_hif_enable_intrs(struct ath6kl_device *dev)
|
||||
{
|
||||
struct ath6kl_irq_enable_reg regs;
|
||||
int status;
|
||||
@@ -552,7 +610,7 @@ static int ath6kldev_enable_intrs(struct ath6kl_device *dev)
|
||||
return status;
|
||||
}
|
||||
|
||||
int ath6kldev_disable_intrs(struct ath6kl_device *dev)
|
||||
int ath6kl_hif_disable_intrs(struct ath6kl_device *dev)
|
||||
{
|
||||
struct ath6kl_irq_enable_reg regs;
|
||||
|
||||
@@ -571,7 +629,7 @@ int ath6kldev_disable_intrs(struct ath6kl_device *dev)
|
||||
}
|
||||
|
||||
/* enable device interrupts */
|
||||
int ath6kldev_unmask_intrs(struct ath6kl_device *dev)
|
||||
int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev)
|
||||
{
|
||||
int status = 0;
|
||||
|
||||
@@ -583,29 +641,29 @@ int ath6kldev_unmask_intrs(struct ath6kl_device *dev)
|
||||
* target "soft" resets. The ATH6KL interrupt enables reset back to an
|
||||
* "enabled" state when this happens.
|
||||
*/
|
||||
ath6kldev_disable_intrs(dev);
|
||||
ath6kl_hif_disable_intrs(dev);
|
||||
|
||||
/* unmask the host controller interrupts */
|
||||
ath6kl_hif_irq_enable(dev->ar);
|
||||
status = ath6kldev_enable_intrs(dev);
|
||||
status = ath6kl_hif_enable_intrs(dev);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* disable all device interrupts */
|
||||
int ath6kldev_mask_intrs(struct ath6kl_device *dev)
|
||||
int ath6kl_hif_mask_intrs(struct ath6kl_device *dev)
|
||||
{
|
||||
/*
|
||||
* Mask the interrupt at the HIF layer to avoid any stray interrupt
|
||||
* taken while we zero out our shadow registers in
|
||||
* ath6kldev_disable_intrs().
|
||||
* ath6kl_hif_disable_intrs().
|
||||
*/
|
||||
ath6kl_hif_irq_disable(dev->ar);
|
||||
|
||||
return ath6kldev_disable_intrs(dev);
|
||||
return ath6kl_hif_disable_intrs(dev);
|
||||
}
|
||||
|
||||
int ath6kldev_setup(struct ath6kl_device *dev)
|
||||
int ath6kl_hif_setup(struct ath6kl_device *dev)
|
||||
{
|
||||
int status = 0;
|
||||
|
||||
@@ -621,19 +679,17 @@ int ath6kldev_setup(struct ath6kl_device *dev)
|
||||
/* must be a power of 2 */
|
||||
if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) {
|
||||
WARN_ON(1);
|
||||
status = -EINVAL;
|
||||
goto fail_setup;
|
||||
}
|
||||
|
||||
/* assemble mask, used for padding to a block */
|
||||
dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1;
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_TRC, "block size: %d, mbox addr:0x%X\n",
|
||||
ath6kl_dbg(ATH6KL_DBG_HIF, "hif block size %d mbox addr 0x%x\n",
|
||||
dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr);
|
||||
|
||||
ath6kl_dbg(ATH6KL_DBG_TRC,
|
||||
"hif interrupt processing is sync only\n");
|
||||
|
||||
status = ath6kldev_disable_intrs(dev);
|
||||
status = ath6kl_hif_disable_intrs(dev);
|
||||
|
||||
fail_setup:
|
||||
return status;
|
||||
@@ -59,6 +59,18 @@
|
||||
/* mode to enable special 4-bit interrupt assertion without clock */
|
||||
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0)
|
||||
|
||||
/* HTC runs over mailbox 0 */
|
||||
#define HTC_MAILBOX 0
|
||||
|
||||
#define ATH6KL_TARGET_DEBUG_INTR_MASK 0x01
|
||||
|
||||
/* FIXME: are these duplicates with MAX_SCATTER_ values in hif.h? */
|
||||
#define ATH6KL_SCATTER_ENTRIES_PER_REQ 16
|
||||
#define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER (16 * 1024)
|
||||
#define ATH6KL_SCATTER_REQS 4
|
||||
|
||||
#define ATH6KL_HIF_COMMUNICATION_TIMEOUT 1000
|
||||
|
||||
struct bus_request {
|
||||
struct list_head list;
|
||||
|
||||
@@ -186,6 +198,34 @@ struct hif_scatter_req {
|
||||
struct hif_scatter_item scat_list[1];
|
||||
};
|
||||
|
||||
struct ath6kl_irq_proc_registers {
|
||||
u8 host_int_status;
|
||||
u8 cpu_int_status;
|
||||
u8 error_int_status;
|
||||
u8 counter_int_status;
|
||||
u8 mbox_frame;
|
||||
u8 rx_lkahd_valid;
|
||||
u8 host_int_status2;
|
||||
u8 gmbox_rx_avail;
|
||||
__le32 rx_lkahd[2];
|
||||
__le32 rx_gmbox_lkahd_alias[2];
|
||||
} __packed;
|
||||
|
||||
struct ath6kl_irq_enable_reg {
|
||||
u8 int_status_en;
|
||||
u8 cpu_int_status_en;
|
||||
u8 err_int_status_en;
|
||||
u8 cntr_int_status_en;
|
||||
} __packed;
|
||||
|
||||
struct ath6kl_device {
|
||||
spinlock_t lock;
|
||||
struct ath6kl_irq_proc_registers irq_proc_reg;
|
||||
struct ath6kl_irq_enable_reg irq_en_reg;
|
||||
struct htc_target *htc_cnxt;
|
||||
struct ath6kl *ar;
|
||||
};
|
||||
|
||||
struct ath6kl_hif_ops {
|
||||
int (*read_write_sync)(struct ath6kl *ar, u32 addr, u8 *buf,
|
||||
u32 len, u32 request);
|
||||
@@ -202,7 +242,26 @@ struct ath6kl_hif_ops {
|
||||
int (*scat_req_rw) (struct ath6kl *ar,
|
||||
struct hif_scatter_req *scat_req);
|
||||
void (*cleanup_scatter)(struct ath6kl *ar);
|
||||
int (*suspend)(struct ath6kl *ar);
|
||||
int (*suspend)(struct ath6kl *ar, struct cfg80211_wowlan *wow);
|
||||
int (*resume)(struct ath6kl *ar);
|
||||
int (*power_on)(struct ath6kl *ar);
|
||||
int (*power_off)(struct ath6kl *ar);
|
||||
void (*stop)(struct ath6kl *ar);
|
||||
};
|
||||
|
||||
int ath6kl_hif_setup(struct ath6kl_device *dev);
|
||||
int ath6kl_hif_unmask_intrs(struct ath6kl_device *dev);
|
||||
int ath6kl_hif_mask_intrs(struct ath6kl_device *dev);
|
||||
int ath6kl_hif_poll_mboxmsg_rx(struct ath6kl_device *dev,
|
||||
u32 *lk_ahd, int timeout);
|
||||
int ath6kl_hif_rx_control(struct ath6kl_device *dev, bool enable_rx);
|
||||
int ath6kl_hif_disable_intrs(struct ath6kl_device *dev);
|
||||
|
||||
int ath6kl_hif_rw_comp_handler(void *context, int status);
|
||||
int ath6kl_hif_intr_bh_handler(struct ath6kl *ar);
|
||||
|
||||
/* Scatter Function and Definitions */
|
||||
int ath6kl_hif_submit_scat_req(struct ath6kl_device *dev,
|
||||
struct hif_scatter_req *scat_req, bool read);
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -393,7 +393,7 @@ struct htc_endpoint_credit_dist {
|
||||
int cred_per_msg;
|
||||
|
||||
/* reserved for HTC use */
|
||||
void *htc_rsvd;
|
||||
struct htc_endpoint *htc_ep;
|
||||
|
||||
/*
|
||||
* current depth of TX queue , i.e. messages waiting for credits
|
||||
@@ -414,9 +414,11 @@ enum htc_credit_dist_reason {
|
||||
HTC_CREDIT_DIST_SEEK_CREDITS,
|
||||
};
|
||||
|
||||
struct htc_credit_state_info {
|
||||
struct ath6kl_htc_credit_info {
|
||||
int total_avail_credits;
|
||||
int cur_free_credits;
|
||||
|
||||
/* list of lowest priority endpoints */
|
||||
struct list_head lowestpri_ep_dist;
|
||||
};
|
||||
|
||||
@@ -508,10 +510,13 @@ struct ath6kl_device;
|
||||
/* our HTC target state */
|
||||
struct htc_target {
|
||||
struct htc_endpoint endpoint[ENDPOINT_MAX];
|
||||
|
||||
/* contains struct htc_endpoint_credit_dist */
|
||||
struct list_head cred_dist_list;
|
||||
|
||||
struct list_head free_ctrl_txbuf;
|
||||
struct list_head free_ctrl_rxbuf;
|
||||
struct htc_credit_state_info *cred_dist_cntxt;
|
||||
struct ath6kl_htc_credit_info *credit_info;
|
||||
int tgt_creds;
|
||||
unsigned int tgt_cred_sz;
|
||||
spinlock_t htc_lock;
|
||||
@@ -542,7 +547,7 @@ struct htc_target {
|
||||
|
||||
void *ath6kl_htc_create(struct ath6kl *ar);
|
||||
void ath6kl_htc_set_credit_dist(struct htc_target *target,
|
||||
struct htc_credit_state_info *cred_info,
|
||||
struct ath6kl_htc_credit_info *cred_info,
|
||||
u16 svc_pri_order[], int len);
|
||||
int ath6kl_htc_wait_target(struct htc_target *target);
|
||||
int ath6kl_htc_start(struct htc_target *target);
|
||||
@@ -563,7 +568,10 @@ int ath6kl_htc_get_rxbuf_num(struct htc_target *target,
|
||||
int ath6kl_htc_add_rxbuf_multiple(struct htc_target *target,
|
||||
struct list_head *pktq);
|
||||
int ath6kl_htc_rxmsg_pending_handler(struct htc_target *target,
|
||||
u32 msg_look_ahead[], int *n_pkts);
|
||||
u32 msg_look_ahead, int *n_pkts);
|
||||
|
||||
int ath6kl_credit_setup(void *htc_handle,
|
||||
struct ath6kl_htc_credit_info *cred_info);
|
||||
|
||||
static inline void set_htc_pkt_info(struct htc_packet *packet, void *context,
|
||||
u8 *buf, unsigned int len,
|
||||
|
||||
@@ -1,92 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2007-2011 Atheros Communications Inc.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef HTC_HIF_H
|
||||
#define HTC_HIF_H
|
||||
|
||||
#include "htc.h"
|
||||
#include "hif.h"
|
||||
|
||||
#define ATH6KL_MAILBOXES 4
|
||||
|
||||
/* HTC runs over mailbox 0 */
|
||||
#define HTC_MAILBOX 0
|
||||
|
||||
#define ATH6KL_TARGET_DEBUG_INTR_MASK 0x01
|
||||
|
||||
#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
|
||||
INT_STATUS_ENABLE_CPU_MASK | \
|
||||
INT_STATUS_ENABLE_COUNTER_MASK)
|
||||
|
||||
#define ATH6KL_REG_IO_BUFFER_SIZE 32
|
||||
#define ATH6KL_MAX_REG_IO_BUFFERS 8
|
||||
#define ATH6KL_SCATTER_ENTRIES_PER_REQ 16
|
||||
#define ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER (16 * 1024)
|
||||
#define ATH6KL_SCATTER_REQS 4
|
||||
|
||||
#ifndef A_CACHE_LINE_PAD
|
||||
#define A_CACHE_LINE_PAD 128
|
||||
#endif
|
||||
#define ATH6KL_MIN_SCATTER_ENTRIES_PER_REQ 2
|
||||
#define ATH6KL_MIN_TRANSFER_SIZE_PER_SCATTER (4 * 1024)
|
||||
|
||||
struct ath6kl_irq_proc_registers {
|
||||
u8 host_int_status;
|
||||
u8 cpu_int_status;
|
||||
u8 error_int_status;
|
||||
u8 counter_int_status;
|
||||
u8 mbox_frame;
|
||||
u8 rx_lkahd_valid;
|
||||
u8 host_int_status2;
|
||||
u8 gmbox_rx_avail;
|
||||
__le32 rx_lkahd[2];
|
||||
__le32 rx_gmbox_lkahd_alias[2];
|
||||
} __packed;
|
||||
|
||||
struct ath6kl_irq_enable_reg {
|
||||
u8 int_status_en;
|
||||
u8 cpu_int_status_en;
|
||||
u8 err_int_status_en;
|
||||
u8 cntr_int_status_en;
|
||||
} __packed;
|
||||
|
||||
struct ath6kl_device {
|
||||
spinlock_t lock;
|
||||
u8 pad1[A_CACHE_LINE_PAD];
|
||||
struct ath6kl_irq_proc_registers irq_proc_reg;
|
||||
u8 pad2[A_CACHE_LINE_PAD];
|
||||
struct ath6kl_irq_enable_reg irq_en_reg;
|
||||
u8 pad3[A_CACHE_LINE_PAD];
|
||||
struct htc_target *htc_cnxt;
|
||||
struct ath6kl *ar;
|
||||
};
|
||||
|
||||
int ath6kldev_setup(struct ath6kl_device *dev);
|
||||
int ath6kldev_unmask_intrs(struct ath6kl_device *dev);
|
||||
int ath6kldev_mask_intrs(struct ath6kl_device *dev);
|
||||
int ath6kldev_poll_mboxmsg_rx(struct ath6kl_device *dev,
|
||||
u32 *lk_ahd, int timeout);
|
||||
int ath6kldev_rx_control(struct ath6kl_device *dev, bool enable_rx);
|
||||
int ath6kldev_disable_intrs(struct ath6kl_device *dev);
|
||||
|
||||
int ath6kldev_rw_comp_handler(void *context, int status);
|
||||
int ath6kldev_intr_bh_handler(struct ath6kl *ar);
|
||||
|
||||
/* Scatter Function and Definitions */
|
||||
int ath6kldev_submit_scat_req(struct ath6kl_device *dev,
|
||||
struct hif_scatter_req *scat_req, bool read);
|
||||
|
||||
#endif /*ATH6KL_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -320,7 +320,10 @@ struct host_interest {
|
||||
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
|
||||
|------------------------------------------------------------------------------|
|
||||
*/
|
||||
#define HI_OPTION_FW_MODE_BITS 0x2
|
||||
#define HI_OPTION_FW_MODE_SHIFT 0xC
|
||||
|
||||
#define HI_OPTION_FW_SUBMODE_BITS 0x2
|
||||
#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
|
||||
|
||||
/* Convert a Target virtual address into a Target physical address */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user