mirror of
https://github.com/armbian/linux.git
synced 2026-01-06 10:13:00 -08:00
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
Pull m68knommu arch updates from Greg Ungerer: "Most of it is a cleanup of the ColdFire hardware header files. We have had a few occurrances of bugs caused by inconsistent definitions of peripheral addresses. These patches make them all consistent, and also clean out a bunch of old crap. Overall we remove about 1000 lines." * 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (27 commits) m68knommu: fix inconsistent formating in ColdFire 5407 definitions m68knommu: fix inconsistent formating in ColdFire 5307 definitions m68knommu: fix inconsistent formating in ColdFire 527x definitions m68knommu: fix inconsistent formating in ColdFire 5272 definitions m68knommu: fix inconsistent formating in ColdFire 523x definitions m68knommu: clean up ColdFire 54xx General Timer definitions m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x m68knommu: move ColdFire slice timer address defiens to 54xx header m68knommu: use read/write IO access functions in ColdFire m532x setup code m68knommu: modify ColdFire 532x GPIO register definitions to be consistent m68knommu: remove a lot of unsed definitions for 532x ColdFire m68knommu: use definitions for the ColdFire 528x FEC multi-function pins m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x m68knommu: remove unused ColdFire 5282 register definitions m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addresses m68knommu: make remaining ColdFire 5272 register definitions absolute addresses m68knommu: make ColdFire Park and Assignment register definitions absolute addresses m68knommu: make ColdFire Chip Select register definitions absolute addresses ...
This commit is contained in:
Linus Torvalds
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
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{
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#ifdef CACHE_INVALIDATE
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__asm__ __volatile__ (
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"movel %0, %%d0\n\t"
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"movec %%d0, %%CACR\n\t"
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"movec %0, %%CACR\n\t"
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"nop\n\t"
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: : "i" (CACHE_INVALIDATE) : "d0" );
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: : "r" (CACHE_INVALIDATE) );
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#endif
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}
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@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
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{
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#ifdef CACHE_INVALIDATEI
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__asm__ __volatile__ (
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"movel %0, %%d0\n\t"
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"movec %%d0, %%CACR\n\t"
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"movec %0, %%CACR\n\t"
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"nop\n\t"
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: : "i" (CACHE_INVALIDATEI) : "d0" );
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: : "r" (CACHE_INVALIDATEI) );
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#endif
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}
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@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
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#endif
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#ifdef CACHE_INVALIDATED
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__asm__ __volatile__ (
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"movel %0, %%d0\n\t"
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"movec %%d0, %%CACR\n\t"
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"movec %0, %%CACR\n\t"
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"nop\n\t"
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: : "i" (CACHE_INVALIDATED) : "d0" );
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: : "r" (CACHE_INVALIDATED) );
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#else
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/* Flush the wrtite buffer */
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/* Flush the write buffer */
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__asm__ __volatile__ ( "nop" );
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#endif
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}
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/*
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* Push cache entries at supplied address. We want to write back any dirty
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* data and the invalidate the cache lines associated with this address.
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* data and then invalidate the cache lines associated with this address.
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*/
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static inline void cache_push(unsigned long paddr, int len)
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{
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@@ -21,33 +21,33 @@
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/*
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* Define the 5206 SIM register set addresses.
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*/
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#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */
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#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */
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#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */
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#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */
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#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */
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#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */
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#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */
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#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */
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#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */
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#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */
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#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
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#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
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#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
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#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
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#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
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#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
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#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
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#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
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#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
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#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
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#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
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#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
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#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
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#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
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#ifdef CONFIG_M5206e
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#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */
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#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */
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#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
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#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
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#endif
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#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */
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#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */
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#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
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#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
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#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/
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#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
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#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */
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#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
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#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
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#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
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#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
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@@ -58,36 +58,36 @@
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#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
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#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */
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#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */
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#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */
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#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */
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#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */
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#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */
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#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */
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#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */
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#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */
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#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */
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#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */
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#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */
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#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */
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#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */
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#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */
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#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */
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#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */
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#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */
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#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */
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#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */
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#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */
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#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */
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#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */
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#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */
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#define MCFSIM_DMCR 0xc6 /* Default control */
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#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
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#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
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#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
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#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
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#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
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#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
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#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
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#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
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#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
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#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
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#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
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#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
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#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
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#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
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#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
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#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
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#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
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#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
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#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
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#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
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#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
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#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
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#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
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#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
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#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
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#ifdef CONFIG_M5206e
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#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */
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#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
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#else
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#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
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#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
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#endif
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
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@@ -176,21 +176,29 @@
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
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#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
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#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
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#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
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#define MCFGPIO_PIN_MAX 107
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCFGPIO_PIN_MAX 107
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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/*
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* Pin Assignment
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*/
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#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
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#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
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#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
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#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
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#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
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#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
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#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
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#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
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#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
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#define MCFGPIO_PAR_ETPU (MCF_IPSBAR + 0x10004E)
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/*
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* DMA unit base addresses.
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@@ -25,41 +25,41 @@
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/*
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* Define the 5249 SIM register set addresses.
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*/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
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#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
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#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
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#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
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#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
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#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
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#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
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#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
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#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
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#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
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#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
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#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
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#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
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#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
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#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
|
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#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
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#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
|
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#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
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#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
|
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#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
|
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#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
|
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#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
|
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#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
|
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#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
|
||||
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
|
||||
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
|
||||
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
|
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#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
|
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#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
|
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#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
|
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#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
|
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#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
|
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#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
|
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#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
|
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#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
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||||
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||||
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
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||||
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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||||
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
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||||
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
|
||||
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
|
||||
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
|
||||
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
|
||||
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
|
||||
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
|
||||
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
|
||||
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
|
||||
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
|
||||
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
|
||||
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
|
||||
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
|
||||
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
|
||||
@@ -134,23 +134,23 @@
|
||||
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
|
||||
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
|
||||
|
||||
#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
|
||||
#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
|
||||
#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */
|
||||
#define MCFSIM2_GPIOINTSTAT (MCF_MBAR2 + 0xc0) /* GPIO intr status */
|
||||
#define MCFSIM2_GPIOINTCLEAR (MCF_MBAR2 + 0xc0) /* GPIO intr clear */
|
||||
#define MCFSIM2_GPIOINTENABLE (MCF_MBAR2 + 0xc4) /* GPIO intr enable */
|
||||
|
||||
#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */
|
||||
#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */
|
||||
#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */
|
||||
#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */
|
||||
#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */
|
||||
#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */
|
||||
#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */
|
||||
#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */
|
||||
#define MCFSIM2_INTLEVEL1 (MCF_MBAR2 + 0x140) /* Intr level reg 1 */
|
||||
#define MCFSIM2_INTLEVEL2 (MCF_MBAR2 + 0x144) /* Intr level reg 2 */
|
||||
#define MCFSIM2_INTLEVEL3 (MCF_MBAR2 + 0x148) /* Intr level reg 3 */
|
||||
#define MCFSIM2_INTLEVEL4 (MCF_MBAR2 + 0x14c) /* Intr level reg 4 */
|
||||
#define MCFSIM2_INTLEVEL5 (MCF_MBAR2 + 0x150) /* Intr level reg 5 */
|
||||
#define MCFSIM2_INTLEVEL6 (MCF_MBAR2 + 0x154) /* Intr level reg 6 */
|
||||
#define MCFSIM2_INTLEVEL7 (MCF_MBAR2 + 0x158) /* Intr level reg 7 */
|
||||
#define MCFSIM2_INTLEVEL8 (MCF_MBAR2 + 0x15c) /* Intr level reg 8 */
|
||||
|
||||
#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */
|
||||
#define MCFSIM2_DMAROUTE (MCF_MBAR2 + 0x188) /* DMA routing */
|
||||
|
||||
#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
|
||||
#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
|
||||
#define MCFSIM2_IDECONFIG1 (MCF_MBAR2 + 0x18c) /* IDEconfig1 */
|
||||
#define MCFSIM2_IDECONFIG2 (MCF_MBAR2 + 0x190) /* IDEconfig2 */
|
||||
|
||||
/*
|
||||
* Define the base interrupt for the second interrupt controller.
|
||||
|
||||
@@ -26,41 +26,41 @@
|
||||
/*
|
||||
* Define the 525x SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
|
||||
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
|
||||
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
|
||||
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
|
||||
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
|
||||
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
|
||||
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
|
||||
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
|
||||
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
|
||||
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
|
||||
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
|
||||
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
|
||||
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
|
||||
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
|
||||
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
|
||||
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
|
||||
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
|
||||
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
|
||||
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
|
||||
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
|
||||
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
|
||||
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
|
||||
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
|
||||
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
|
||||
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
|
||||
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
|
||||
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
|
||||
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
|
||||
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
|
||||
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
|
||||
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
|
||||
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
|
||||
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
|
||||
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
|
||||
|
||||
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
|
||||
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
|
||||
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
|
||||
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
|
||||
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
|
||||
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
|
||||
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
|
||||
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
|
||||
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
|
||||
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
|
||||
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
|
||||
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
|
||||
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
|
||||
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
|
||||
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
|
||||
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
|
||||
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
|
||||
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
|
||||
|
||||
@@ -21,52 +21,52 @@
|
||||
/*
|
||||
* Define the 5272 SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */
|
||||
#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */
|
||||
#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */
|
||||
#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */
|
||||
#define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */
|
||||
#define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */
|
||||
#define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */
|
||||
#define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */
|
||||
#define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */
|
||||
|
||||
#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */
|
||||
#define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */
|
||||
#define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */
|
||||
#define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */
|
||||
#define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */
|
||||
|
||||
#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */
|
||||
#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */
|
||||
#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */
|
||||
#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */
|
||||
#define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */
|
||||
#define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */
|
||||
#define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */
|
||||
#define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */
|
||||
|
||||
#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */
|
||||
#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */
|
||||
#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */
|
||||
#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */
|
||||
#define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */
|
||||
#define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */
|
||||
#define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */
|
||||
#define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */
|
||||
|
||||
#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */
|
||||
#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */
|
||||
#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */
|
||||
#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */
|
||||
#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */
|
||||
#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */
|
||||
#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */
|
||||
#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */
|
||||
#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */
|
||||
#define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */
|
||||
#define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */
|
||||
#define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */
|
||||
#define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */
|
||||
#define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */
|
||||
#define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */
|
||||
#define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */
|
||||
#define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */
|
||||
#define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */
|
||||
#define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */
|
||||
#define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */
|
||||
#define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */
|
||||
#define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */
|
||||
#define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */
|
||||
#define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */
|
||||
#define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */
|
||||
|
||||
#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */
|
||||
#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */
|
||||
#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */
|
||||
#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */
|
||||
#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */
|
||||
#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */
|
||||
#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
|
||||
#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
|
||||
#define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */
|
||||
#define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */
|
||||
#define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */
|
||||
#define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */
|
||||
#define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */
|
||||
#define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */
|
||||
#define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */
|
||||
#define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */
|
||||
|
||||
#define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */
|
||||
#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
|
||||
@@ -132,8 +132,9 @@
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
#define MCFGPIO_PIN_MAX 48
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
#define MCFGPIO_PIN_MAX 48
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* m5272sim_h */
|
||||
|
||||
@@ -184,19 +184,33 @@
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
|
||||
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
|
||||
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
|
||||
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
|
||||
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
|
||||
#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
|
||||
#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
|
||||
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
|
||||
#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
|
||||
#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
|
||||
|
||||
#define MCFGPIO_PIN_MAX 100
|
||||
#define MCFGPIO_IRQ_MAX 8
|
||||
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
|
||||
#define MCFGPIO_PIN_MAX 100
|
||||
#define MCFGPIO_IRQ_MAX 8
|
||||
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
|
||||
|
||||
/*
|
||||
* Port Pin Assignment registers.
|
||||
*/
|
||||
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040)
|
||||
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042)
|
||||
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044)
|
||||
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045)
|
||||
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046)
|
||||
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047)
|
||||
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048)
|
||||
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A)
|
||||
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C)
|
||||
#endif
|
||||
|
||||
#define UART0_ENABLE_MASK 0x000f
|
||||
#define UART1_ENABLE_MASK 0x0ff0
|
||||
#define UART2_ENABLE_MASK 0x3000
|
||||
#endif /* CONFIG_M5271 */
|
||||
|
||||
#ifdef CONFIG_M5275
|
||||
#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
|
||||
@@ -279,18 +293,36 @@
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
|
||||
#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
|
||||
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
|
||||
#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
|
||||
#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
|
||||
#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
|
||||
#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
|
||||
#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
|
||||
#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
|
||||
#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
|
||||
|
||||
#define MCFGPIO_PIN_MAX 148
|
||||
#define MCFGPIO_IRQ_MAX 8
|
||||
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
|
||||
#define MCFGPIO_PIN_MAX 148
|
||||
#define MCFGPIO_IRQ_MAX 8
|
||||
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
|
||||
|
||||
/*
|
||||
* Port Pin Assignment registers.
|
||||
*/
|
||||
#define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070)
|
||||
#define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071)
|
||||
#define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072)
|
||||
#define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076)
|
||||
#define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078)
|
||||
#define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079)
|
||||
#define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A)
|
||||
#define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C)
|
||||
#define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E)
|
||||
#endif
|
||||
#define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080)
|
||||
#define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082)
|
||||
#define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084)
|
||||
|
||||
#define UART0_ENABLE_MASK 0x000f
|
||||
#define UART1_ENABLE_MASK 0x00f0
|
||||
#define UART2_ENABLE_MASK 0x3f00
|
||||
#endif /* CONFIG_M5275 */
|
||||
|
||||
/*
|
||||
* PIT timer base addresses.
|
||||
@@ -310,22 +342,6 @@
|
||||
#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
|
||||
#define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006)
|
||||
|
||||
/*
|
||||
* GPIO pins setups to enable the UARTs.
|
||||
*/
|
||||
#ifdef CONFIG_M5271
|
||||
#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */
|
||||
#define UART0_ENABLE_MASK 0x000f
|
||||
#define UART1_ENABLE_MASK 0x0ff0
|
||||
#define UART2_ENABLE_MASK 0x3000
|
||||
#endif
|
||||
#ifdef CONFIG_M5275
|
||||
#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */
|
||||
#define UART0_ENABLE_MASK 0x000f
|
||||
#define UART1_ENABLE_MASK 0x00f0
|
||||
#define UART2_ENABLE_MASK 0x3f00
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Reset Control Unit (relative to IPSBAR).
|
||||
*/
|
||||
|
||||
@@ -233,23 +233,6 @@
|
||||
#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
|
||||
#define MCFGPIO_PIN_MAX 180
|
||||
|
||||
|
||||
/*
|
||||
* Derek Cheung - 6 Feb 2005
|
||||
* add I2C and QSPI register definition using Freescale's MCF5282
|
||||
*/
|
||||
/* set Port AS pin for I2C or UART */
|
||||
#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056)
|
||||
|
||||
/* Port UA Pin Assignment Register (8 Bit) */
|
||||
#define MCF5282_GPIO_PUAPAR 0x10005C
|
||||
|
||||
/* Interrupt Mask Register Register Low */
|
||||
#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C)
|
||||
/* Interrupt Control Register 7 */
|
||||
#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51)
|
||||
|
||||
|
||||
/*
|
||||
* Reset Control Unit (relative to IPSBAR).
|
||||
*/
|
||||
@@ -259,37 +242,5 @@
|
||||
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
|
||||
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Inter-IC (I2C) Module
|
||||
*
|
||||
*********************************************************************/
|
||||
/* Read/Write access macros for general use */
|
||||
#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address
|
||||
#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider
|
||||
#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control
|
||||
#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status
|
||||
#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O
|
||||
|
||||
/* Bit level definitions and macros */
|
||||
#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01)
|
||||
|
||||
#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F))
|
||||
|
||||
#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable
|
||||
#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable
|
||||
#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode
|
||||
#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode
|
||||
#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable
|
||||
#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start
|
||||
|
||||
#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit
|
||||
#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave
|
||||
#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy
|
||||
#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost
|
||||
#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write
|
||||
#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt
|
||||
#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
#endif /* m528xsim_h */
|
||||
|
||||
@@ -23,71 +23,71 @@
|
||||
/*
|
||||
* Define the 5307 SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
|
||||
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
|
||||
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
|
||||
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
|
||||
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
|
||||
#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
|
||||
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
|
||||
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
|
||||
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
|
||||
#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
|
||||
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
|
||||
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
|
||||
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
|
||||
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
|
||||
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
|
||||
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
|
||||
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
|
||||
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
|
||||
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
|
||||
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
|
||||
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
|
||||
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
|
||||
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
|
||||
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
|
||||
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
|
||||
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
|
||||
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
|
||||
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
|
||||
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
|
||||
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
|
||||
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
|
||||
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
|
||||
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
|
||||
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
|
||||
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
|
||||
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
|
||||
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
|
||||
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
|
||||
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
|
||||
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
|
||||
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
|
||||
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
|
||||
|
||||
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
|
||||
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
|
||||
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
|
||||
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
|
||||
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
|
||||
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
|
||||
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
|
||||
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
|
||||
|
||||
#ifdef CONFIG_OLDMASK
|
||||
#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */
|
||||
#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */
|
||||
#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
|
||||
#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
|
||||
#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
|
||||
#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
|
||||
#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
|
||||
#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
|
||||
#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
|
||||
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
|
||||
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
|
||||
#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
|
||||
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
|
||||
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
|
||||
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
|
||||
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
|
||||
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
|
||||
#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
|
||||
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
|
||||
#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
|
||||
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
|
||||
#else
|
||||
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
|
||||
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
|
||||
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
|
||||
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
|
||||
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
|
||||
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
|
||||
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
|
||||
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
|
||||
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
|
||||
#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
|
||||
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
|
||||
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
|
||||
#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
|
||||
#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
|
||||
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
|
||||
#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
|
||||
#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
|
||||
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
|
||||
#endif /* CONFIG_OLDMASK */
|
||||
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
@@ -127,9 +127,9 @@
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
#define MCFGPIO_PIN_MAX 16
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
#define MCFGPIO_PIN_MAX 16
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
|
||||
|
||||
/* Definition offset address for CS2-7 -- old mask 5307 */
|
||||
@@ -167,9 +167,9 @@
|
||||
/*
|
||||
* Defines for the IRQPAR Register
|
||||
*/
|
||||
#define IRQ5_LEVEL4 0x80
|
||||
#define IRQ3_LEVEL6 0x40
|
||||
#define IRQ1_LEVEL2 0x20
|
||||
#define IRQ5_LEVEL4 0x80
|
||||
#define IRQ3_LEVEL6 0x40
|
||||
#define IRQ1_LEVEL2 0x20
|
||||
|
||||
/*
|
||||
* Define system peripheral IRQ usage.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -23,55 +23,55 @@
|
||||
/*
|
||||
* Define the 5407 SIM register set addresses.
|
||||
*/
|
||||
#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
|
||||
#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
|
||||
#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
|
||||
#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
|
||||
#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */
|
||||
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
|
||||
#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
|
||||
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
|
||||
#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
|
||||
#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
|
||||
#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */
|
||||
#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
|
||||
#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
|
||||
#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
|
||||
#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
|
||||
#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
|
||||
#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
|
||||
#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
|
||||
#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
|
||||
#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
|
||||
#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
|
||||
#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
|
||||
#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
|
||||
#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status */
|
||||
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
|
||||
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
|
||||
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
|
||||
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
|
||||
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
|
||||
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
|
||||
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
|
||||
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
|
||||
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
|
||||
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */
|
||||
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
|
||||
#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
|
||||
#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
|
||||
#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
|
||||
#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
|
||||
#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
|
||||
#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
|
||||
#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
|
||||
#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
|
||||
#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
|
||||
#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
|
||||
#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
|
||||
|
||||
#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
|
||||
#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
|
||||
#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
|
||||
#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
|
||||
#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
|
||||
#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
|
||||
#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
|
||||
#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
|
||||
|
||||
#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */
|
||||
#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */
|
||||
#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */
|
||||
#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
|
||||
#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
|
||||
#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
|
||||
#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
|
||||
#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
|
||||
#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
|
||||
#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
|
||||
#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
|
||||
#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
|
||||
#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
|
||||
#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
|
||||
#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
|
||||
#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
|
||||
#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
|
||||
#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
|
||||
#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
|
||||
#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
|
||||
#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
|
||||
|
||||
#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
|
||||
#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
|
||||
@@ -102,9 +102,9 @@
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
#define MCFGPIO_PIN_MAX 16
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
#define MCFGPIO_PIN_MAX 16
|
||||
#define MCFGPIO_IRQ_MAX -1
|
||||
#define MCFGPIO_IRQ_VECBASE -1
|
||||
|
||||
/*
|
||||
* Some symbol defines for the above...
|
||||
@@ -130,9 +130,9 @@
|
||||
/*
|
||||
* Defines for the IRQPAR Register
|
||||
*/
|
||||
#define IRQ5_LEVEL4 0x80
|
||||
#define IRQ3_LEVEL6 0x40
|
||||
#define IRQ1_LEVEL2 0x20
|
||||
#define IRQ5_LEVEL4 0x80
|
||||
#define IRQ3_LEVEL6 0x40
|
||||
#define IRQ1_LEVEL2 0x20
|
||||
|
||||
/*
|
||||
* Define system peripheral IRQ usage.
|
||||
|
||||
@@ -16,26 +16,26 @@
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPT_GMS0 0x000800
|
||||
#define MCF_GPT_GCIR0 0x000804
|
||||
#define MCF_GPT_GPWM0 0x000808
|
||||
#define MCF_GPT_GSR0 0x00080C
|
||||
#define MCF_GPT_GMS1 0x000810
|
||||
#define MCF_GPT_GCIR1 0x000814
|
||||
#define MCF_GPT_GPWM1 0x000818
|
||||
#define MCF_GPT_GSR1 0x00081C
|
||||
#define MCF_GPT_GMS2 0x000820
|
||||
#define MCF_GPT_GCIR2 0x000824
|
||||
#define MCF_GPT_GPWM2 0x000828
|
||||
#define MCF_GPT_GSR2 0x00082C
|
||||
#define MCF_GPT_GMS3 0x000830
|
||||
#define MCF_GPT_GCIR3 0x000834
|
||||
#define MCF_GPT_GPWM3 0x000838
|
||||
#define MCF_GPT_GSR3 0x00083C
|
||||
#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
|
||||
#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
|
||||
#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
|
||||
#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
|
||||
#define MCF_GPT_GMS0 (MCF_MBAR + 0x000800)
|
||||
#define MCF_GPT_GCIR0 (MCF_MBAR + 0x000804)
|
||||
#define MCF_GPT_GPWM0 (MCF_MBAR + 0x000808)
|
||||
#define MCF_GPT_GSR0 (MCF_MBAR + 0x00080C)
|
||||
#define MCF_GPT_GMS1 (MCF_MBAR + 0x000810)
|
||||
#define MCF_GPT_GCIR1 (MCF_MBAR + 0x000814)
|
||||
#define MCF_GPT_GPWM1 (MCF_MBAR + 0x000818)
|
||||
#define MCF_GPT_GSR1 (MCF_MBAR + 0x00081C)
|
||||
#define MCF_GPT_GMS2 (MCF_MBAR + 0x000820)
|
||||
#define MCF_GPT_GCIR2 (MCF_MBAR + 0x000824)
|
||||
#define MCF_GPT_GPWM2 (MCF_MBAR + 0x000828)
|
||||
#define MCF_GPT_GSR2 (MCF_MBAR + 0x00082C)
|
||||
#define MCF_GPT_GMS3 (MCF_MBAR + 0x000830)
|
||||
#define MCF_GPT_GCIR3 (MCF_MBAR + 0x000834)
|
||||
#define MCF_GPT_GPWM3 (MCF_MBAR + 0x000838)
|
||||
#define MCF_GPT_GSR3 (MCF_MBAR + 0x00083C)
|
||||
#define MCF_GPT_GMS(x) (MCF_MBAR + 0x000800 + ((x) * 0x010))
|
||||
#define MCF_GPT_GCIR(x) (MCF_MBAR + 0x000804 + ((x) * 0x010))
|
||||
#define MCF_GPT_GPWM(x) (MCF_MBAR + 0x000808 + ((x) * 0x010))
|
||||
#define MCF_GPT_GSR(x) (MCF_MBAR + 0x00080C + ((x) * 0x010))
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GMS */
|
||||
#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
|
||||
|
||||
@@ -46,6 +46,12 @@
|
||||
#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
|
||||
#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
|
||||
|
||||
/*
|
||||
* Slice Timer support.
|
||||
*/
|
||||
#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
|
||||
#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
|
||||
|
||||
/*
|
||||
* Generic GPIO support
|
||||
*/
|
||||
@@ -64,15 +70,25 @@
|
||||
#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
|
||||
|
||||
/*
|
||||
* Some PSC related definitions
|
||||
* Pin Assignment register definitions
|
||||
*/
|
||||
#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
|
||||
#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
|
||||
#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
|
||||
#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
|
||||
#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
|
||||
#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
|
||||
#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
|
||||
#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
|
||||
#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
|
||||
#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
|
||||
#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
|
||||
#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
|
||||
#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
|
||||
|
||||
#define MCF_PAR_SDA (0x0008)
|
||||
#define MCF_PAR_SCL (0x0004)
|
||||
#define MCF_PAR_PSC_TXD (0x04)
|
||||
#define MCF_PAR_PSC_RXD (0x08)
|
||||
#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
|
||||
#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
|
||||
#define MCF_PAR_PSC_CTS_GPIO (0x00)
|
||||
#define MCF_PAR_PSC_CTS_BCLK (0x80)
|
||||
#define MCF_PAR_PSC_CTS_CTS (0xC0)
|
||||
@@ -81,7 +97,4 @@
|
||||
#define MCF_PAR_PSC_RTS_RTS (0x30)
|
||||
#define MCF_PAR_PSC_CANRX (0x40)
|
||||
|
||||
#define MCF_PAR_PCIBG (CONFIG_MBAR + 0xa48) /* PCI bus grant */
|
||||
#define MCF_PAR_PCIBR (CONFIG_MBAR + 0xa4a) /* PCI */
|
||||
|
||||
#endif /* m54xxsim_h */
|
||||
|
||||
@@ -12,13 +12,6 @@
|
||||
#define mcfslt_h
|
||||
/****************************************************************************/
|
||||
|
||||
/*
|
||||
* Get address specific defines for the 547x.
|
||||
*/
|
||||
#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
|
||||
#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
|
||||
|
||||
|
||||
/*
|
||||
* Define the SLT timer register set addresses.
|
||||
*/
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
#ifdef CONFIG_COLDFIRE
|
||||
#include <asm/coldfire.h>
|
||||
#include <asm/mcfsim.h>
|
||||
#include <asm/io.h>
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
@@ -86,16 +87,12 @@ static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
|
||||
*/
|
||||
static __inline__ unsigned int mcf_getppdata(void)
|
||||
{
|
||||
volatile unsigned short *pp;
|
||||
pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
|
||||
return((unsigned int) *pp);
|
||||
return readw(MCFSIM_PBDAT);
|
||||
}
|
||||
|
||||
static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
|
||||
{
|
||||
volatile unsigned short *pp;
|
||||
pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT);
|
||||
*pp = (*pp & ~mask) | bits;
|
||||
write((readw(MCFSIM_PBDAT) & ~mask) | bits, MCFSIM_PBDAT);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,11 +1,5 @@
|
||||
#
|
||||
# Makefile for arch/m68knommu/platform/68VZ328.
|
||||
# Makefile for arch/m68k/platform/68VZ328.
|
||||
#
|
||||
|
||||
obj-y := config.o
|
||||
extra-$(DRAGEN2):= screen.h
|
||||
|
||||
$(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
|
||||
perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
|
||||
|
||||
clean-files := $(obj)/screen.h
|
||||
|
||||
@@ -347,12 +347,12 @@ static void __init mcf_uart_set_irq(void)
|
||||
{
|
||||
#ifdef MCFUART_UIVR
|
||||
/* UART0 interrupt setup */
|
||||
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
|
||||
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
|
||||
writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
|
||||
mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
|
||||
|
||||
/* UART1 interrupt setup */
|
||||
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
|
||||
writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
|
||||
writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
|
||||
mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
|
||||
#endif
|
||||
|
||||
@@ -60,7 +60,7 @@
|
||||
|
||||
#elif defined(CONFIG_M5272)
|
||||
.macro GET_MEM_SIZE
|
||||
movel MCF_MBAR+MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
|
||||
movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
|
||||
andil #0xfffff000,%d0 /* mask out chip select options */
|
||||
negl %d0 /* negate bits */
|
||||
.endm
|
||||
|
||||
@@ -20,22 +20,22 @@
|
||||
static void intc2_irq_gpio_mask(struct irq_data *d)
|
||||
{
|
||||
u32 imr;
|
||||
imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
|
||||
imr = readl(MCFSIM2_GPIOINTENABLE);
|
||||
imr &= ~(0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
|
||||
writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
|
||||
writel(imr, MCFSIM2_GPIOINTENABLE);
|
||||
}
|
||||
|
||||
static void intc2_irq_gpio_unmask(struct irq_data *d)
|
||||
{
|
||||
u32 imr;
|
||||
imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
|
||||
imr = readl(MCFSIM2_GPIOINTENABLE);
|
||||
imr |= (0x1 << (d->irq - MCFINTC2_GPIOIRQ0));
|
||||
writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
|
||||
writel(imr, MCFSIM2_GPIOINTENABLE);
|
||||
}
|
||||
|
||||
static void intc2_irq_gpio_ack(struct irq_data *d)
|
||||
{
|
||||
writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
|
||||
writel(0x1 << (d->irq - MCFINTC2_GPIOIRQ0), MCFSIM2_GPIOINTCLEAR);
|
||||
}
|
||||
|
||||
static struct irq_chip intc2_irq_gpio_chip = {
|
||||
|
||||
@@ -86,7 +86,7 @@ static void intc_irq_mask(struct irq_data *d)
|
||||
u32 v;
|
||||
irq -= MCFINT_VECBASE;
|
||||
v = 0x8 << intc_irqmap[irq].index;
|
||||
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
|
||||
writel(v, intc_irqmap[irq].icr);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -98,7 +98,7 @@ static void intc_irq_unmask(struct irq_data *d)
|
||||
u32 v;
|
||||
irq -= MCFINT_VECBASE;
|
||||
v = 0xd << intc_irqmap[irq].index;
|
||||
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
|
||||
writel(v, intc_irqmap[irq].icr);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -111,10 +111,10 @@ static void intc_irq_ack(struct irq_data *d)
|
||||
irq -= MCFINT_VECBASE;
|
||||
if (intc_irqmap[irq].ack) {
|
||||
u32 v;
|
||||
v = readl(MCF_MBAR + intc_irqmap[irq].icr);
|
||||
v = readl(intc_irqmap[irq].icr);
|
||||
v &= (0x7 << intc_irqmap[irq].index);
|
||||
v |= (0x8 << intc_irqmap[irq].index);
|
||||
writel(v, MCF_MBAR + intc_irqmap[irq].icr);
|
||||
writel(v, intc_irqmap[irq].icr);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -127,12 +127,12 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
irq -= MCFINT_VECBASE;
|
||||
if (intc_irqmap[irq].ack) {
|
||||
u32 v;
|
||||
v = readl(MCF_MBAR + MCFSIM_PITR);
|
||||
v = readl(MCFSIM_PITR);
|
||||
if (type == IRQ_TYPE_EDGE_FALLING)
|
||||
v &= ~(0x1 << (32 - irq));
|
||||
else
|
||||
v |= (0x1 << (32 - irq));
|
||||
writel(v, MCF_MBAR + MCFSIM_PITR);
|
||||
writel(v, MCFSIM_PITR);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
@@ -163,10 +163,10 @@ void __init init_IRQ(void)
|
||||
int irq, edge;
|
||||
|
||||
/* Mask all interrupt sources */
|
||||
writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
|
||||
writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
|
||||
writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
|
||||
writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
|
||||
writel(0x88888888, MCFSIM_ICR1);
|
||||
writel(0x88888888, MCFSIM_ICR2);
|
||||
writel(0x88888888, MCFSIM_ICR3);
|
||||
writel(0x88888888, MCFSIM_ICR4);
|
||||
|
||||
for (irq = 0; (irq < NR_IRQS); irq++) {
|
||||
irq_set_chip(irq, &intc_irq_chip);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user