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synced 2026-01-06 10:13:00 -08:00
b43: rewrite A PHY initialization
Rewrite and sync A PHY initialization with specs, thus allowing for further work to be done on 802.11a support. Note that A PHY initialization involves G PHYs as well. Signed-off-by: Stefano Brivio <stefano.brivio@polimi.it> Acked-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
committed by
David S. Miller
parent
db9683fb19
commit
61bca6eb85
@@ -5,6 +5,7 @@ b43-y += phy.o
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b43-y += sysfs.o
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b43-y += xmit.o
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b43-y += lo.o
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b43-y += wa.o
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# b43 RFKILL button support
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b43-$(CONFIG_B43_RFKILL) += rfkill.o
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# b43 LED support
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@@ -544,6 +544,10 @@ struct b43_phy {
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u16 lofcal;
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u16 initval; //FIXME rename?
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/* OFDM address read/write caching for hardware auto-increment. */
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u16 ofdm_addr;
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u8 ofdm_valid; /* 0: invalid, 1: read, 2: write */
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};
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/* Data structures for DMA transmission, per 80211 core. */
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@@ -2254,6 +2254,9 @@ static int b43_chip_init(struct b43_wldev *dev)
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b43_write16(dev, B43_MMIO_POWERUP_DELAY,
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dev->dev->bus->chipco.fast_pwrup_delay);
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/* OFDM address caching. */
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phy->ofdm_valid = 0;
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err = 0;
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b43dbg(dev->wl, "Chip initialized\n");
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out:
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File diff suppressed because it is too large
Load Diff
@@ -27,8 +27,11 @@ struct b43_phy;
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#define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
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#define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 */
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#define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
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#define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
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#define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
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#define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
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#define B43_PHY_CRS0_EN 0x4000
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#define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
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#define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
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#define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
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#define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
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@@ -37,6 +40,7 @@ struct b43_phy;
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#define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
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#define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */
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#define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
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#define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
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#define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
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#define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
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#define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
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@@ -44,6 +48,9 @@ struct b43_phy;
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#define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
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#define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
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#define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
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#define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
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#define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
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#define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
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#define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
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#define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
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#define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
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@@ -54,6 +61,8 @@ struct b43_phy;
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#define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
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#define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
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#define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
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#define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
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#define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
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#define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
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#define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
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#define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
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@@ -125,13 +134,14 @@ struct b43_phy;
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#define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7)
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#define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12)
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#define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13)
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//TODO
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#define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename
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#define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename
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#define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12)
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#define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0)
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//TODO
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#define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename
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#define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0)
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#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO rename
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#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 1)
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#define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove!
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#define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0)
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#define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0)
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#define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4)
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#define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0)
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@@ -229,7 +229,7 @@ const u16 b43_tab_noisea2[] = {
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};
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const u16 b43_tab_noisea3[] = {
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0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
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0x5E5E, 0x5E5E, 0x5E5E, 0x3F48,
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0x4C4C, 0x4C4C, 0x4C4C, 0x2D36,
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};
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@@ -243,6 +243,26 @@ const u16 b43_tab_noiseg2[] = {
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0x0000, 0x0000, 0x0000, 0x0000,
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};
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const u16 b43_tab_noisescalea2[] = {
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0x6767, 0x6767, 0x6767, 0x6767, /* 0 */
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0x6767, 0x6767, 0x6767, 0x6767,
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0x6767, 0x6767, 0x6767, 0x6767,
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0x6767, 0x6700, 0x6767, 0x6767,
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0x6767, 0x6767, 0x6767, 0x6767, /* 16 */
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0x6767, 0x6767, 0x6767, 0x6767,
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0x6767, 0x6767, 0x0067,
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};
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const u16 b43_tab_noisescalea3[] = {
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0x2323, 0x2323, 0x2323, 0x2323, /* 0 */
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0x2323, 0x2323, 0x2323, 0x2323,
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0x2323, 0x2323, 0x2323, 0x2323,
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0x2323, 0x2300, 0x2323, 0x2323,
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0x2323, 0x2323, 0x2323, 0x2323, /* 16 */
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0x2323, 0x2323, 0x2323, 0x2323,
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0x2323, 0x2323, 0x0023,
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};
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const u16 b43_tab_noisescaleg1[] = {
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0x6C77, 0x5162, 0x3B40, 0x3335, /* 0 */
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0x2F2D, 0x2A2A, 0x2527, 0x1F21,
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@@ -254,7 +274,7 @@ const u16 b43_tab_noisescaleg1[] = {
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};
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const u16 b43_tab_noisescaleg2[] = {
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0xD8DD, 0xCBD4, 0xBCC0, 0XB6B7, /* 0 */
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0xD8DD, 0xCBD4, 0xBCC0, 0xB6B7, /* 0 */
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0xB2B0, 0xADAD, 0xA7A9, 0x9FA1,
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0x969B, 0x9195, 0x8F8F, 0x8A8A,
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0x8A8A, 0x8A00, 0x8A8A, 0x8F8A,
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@@ -307,6 +327,28 @@ const u16 b43_tab_sigmasqr2[] = {
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0x00DE,
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};
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const u16 b43_tab_rssiagc1[] = {
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0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8, /* 0 */
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0xFFF8, 0xFFF9, 0xFFFC, 0xFFFE,
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0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8,
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0xFFF8, 0xFFF8, 0xFFF8, 0xFFF8,
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};
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const u16 b43_tab_rssiagc2[] = {
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0x0820, 0x0820, 0x0920, 0x0C38, /* 0 */
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0x0820, 0x0820, 0x0820, 0x0820,
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0x0820, 0x0820, 0x0920, 0x0A38,
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0x0820, 0x0820, 0x0820, 0x0820,
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0x0820, 0x0820, 0x0920, 0x0A38, /* 16 */
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0x0820, 0x0820, 0x0820, 0x0820,
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0x0820, 0x0820, 0x0920, 0x0A38,
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0x0820, 0x0820, 0x0820, 0x0820,
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0x0820, 0x0820, 0x0920, 0x0A38, /* 32 */
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0x0820, 0x0820, 0x0820, 0x0820,
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0x0820, 0x0820, 0x0920, 0x0A38,
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0x0820, 0x0820, 0x0820, 0x0820,
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};
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static inline void assert_sizes(void)
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{
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BUILD_BUG_ON(B43_TAB_ROTOR_SIZE != ARRAY_SIZE(b43_tab_rotor));
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@@ -317,36 +359,65 @@ static inline void assert_sizes(void)
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BUILD_BUG_ON(B43_TAB_NOISEA3_SIZE != ARRAY_SIZE(b43_tab_noisea3));
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BUILD_BUG_ON(B43_TAB_NOISEG1_SIZE != ARRAY_SIZE(b43_tab_noiseg1));
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BUILD_BUG_ON(B43_TAB_NOISEG2_SIZE != ARRAY_SIZE(b43_tab_noiseg2));
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BUILD_BUG_ON(B43_TAB_NOISESCALEG_SIZE !=
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BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
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ARRAY_SIZE(b43_tab_noisescalea2));
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BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
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ARRAY_SIZE(b43_tab_noisescalea3));
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BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
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ARRAY_SIZE(b43_tab_noisescaleg1));
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BUILD_BUG_ON(B43_TAB_NOISESCALEG_SIZE !=
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BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
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ARRAY_SIZE(b43_tab_noisescaleg2));
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BUILD_BUG_ON(B43_TAB_NOISESCALEG_SIZE !=
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BUILD_BUG_ON(B43_TAB_NOISESCALE_SIZE !=
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ARRAY_SIZE(b43_tab_noisescaleg3));
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BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr1));
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BUILD_BUG_ON(B43_TAB_SIGMASQR_SIZE != ARRAY_SIZE(b43_tab_sigmasqr2));
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BUILD_BUG_ON(B43_TAB_RSSIAGC1_SIZE != ARRAY_SIZE(b43_tab_rssiagc1));
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BUILD_BUG_ON(B43_TAB_RSSIAGC2_SIZE != ARRAY_SIZE(b43_tab_rssiagc2));
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}
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u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset)
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{
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assert_sizes();
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struct b43_phy *phy = &dev->phy;
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u16 addr;
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addr = table + offset;
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if (addr - 1 != phy->ofdm_addr || phy->ofdm_valid != 1) {
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b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
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phy->ofdm_valid = 1;
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}
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phy->ofdm_addr = addr;
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b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
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return b43_phy_read(dev, B43_PHY_OTABLEI);
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assert_sizes();
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}
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void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
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u16 offset, u16 value)
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{
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b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
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struct b43_phy *phy = &dev->phy;
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u16 addr;
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addr = table + offset;
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if (addr - 1 != phy->ofdm_addr || phy->ofdm_valid != 2) {
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b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
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phy->ofdm_valid = 2;
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}
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phy->ofdm_addr = addr;
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b43_phy_write(dev, B43_PHY_OTABLEI, value);
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}
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u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
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{
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struct b43_phy *phy = &dev->phy;
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u32 ret;
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u16 addr;
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b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
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addr = table + offset;
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if (addr - 1 != phy->ofdm_addr || phy->ofdm_valid != 1) {
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b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
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phy->ofdm_valid = 1;
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}
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phy->ofdm_addr = addr;
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ret = b43_phy_read(dev, B43_PHY_OTABLEQ);
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ret <<= 16;
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ret |= b43_phy_read(dev, B43_PHY_OTABLEI);
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@@ -357,9 +428,17 @@ u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset)
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void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
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u16 offset, u32 value)
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{
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b43_phy_write(dev, B43_PHY_OTABLECTL, table + offset);
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struct b43_phy *phy = &dev->phy;
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u16 addr;
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addr = table + offset;
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if (addr - 1 != phy->ofdm_addr || phy->ofdm_valid != 2) {
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b43_phy_write(dev, B43_PHY_OTABLECTL, addr);
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phy->ofdm_valid = 2;
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}
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phy->ofdm_addr = addr;
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b43_phy_write(dev, B43_PHY_OTABLEI, value);
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b43_phy_write(dev, B43_PHY_OTABLEQ, (value >> 16));
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}
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u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset)
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@@ -1,9 +1,9 @@
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#ifndef B43_TABLES_H_
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#define B43_TABLES_H_
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#define B43_TAB_ROTOR_SIZE 53
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#define B43_TAB_ROTOR_SIZE 53
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extern const u32 b43_tab_rotor[];
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#define B43_TAB_RETARD_SIZE 53
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#define B43_TAB_RETARD_SIZE 53
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extern const u32 b43_tab_retard[];
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#define B43_TAB_FINEFREQA_SIZE 256
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extern const u16 b43_tab_finefreqa[];
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@@ -17,12 +17,18 @@ extern const u16 b43_tab_noisea3[];
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extern const u16 b43_tab_noiseg1[];
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#define B43_TAB_NOISEG2_SIZE 8
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extern const u16 b43_tab_noiseg2[];
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#define B43_TAB_NOISESCALEG_SIZE 27
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#define B43_TAB_NOISESCALE_SIZE 27
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extern const u16 b43_tab_noisescalea2[];
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extern const u16 b43_tab_noisescalea3[];
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extern const u16 b43_tab_noisescaleg1[];
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extern const u16 b43_tab_noisescaleg2[];
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extern const u16 b43_tab_noisescaleg3[];
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#define B43_TAB_SIGMASQR_SIZE 53
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extern const u16 b43_tab_sigmasqr1[];
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extern const u16 b43_tab_sigmasqr2[];
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#define B43_TAB_RSSIAGC1_SIZE 16
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extern const u16 b43_tab_rssiagc1[];
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#define B43_TAB_RSSIAGC2_SIZE 48
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extern const u16 b43_tab_rssiagc2[];
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#endif /* B43_TABLES_H_ */
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668
drivers/net/wireless/b43/wa.c
Normal file
668
drivers/net/wireless/b43/wa.c
Normal file
File diff suppressed because it is too large
Load Diff
7
drivers/net/wireless/b43/wa.h
Normal file
7
drivers/net/wireless/b43/wa.h
Normal file
@@ -0,0 +1,7 @@
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#ifndef B43_WA_H_
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#define B43_WA_H_
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void b43_wa_initgains(struct b43_wldev *dev);
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void b43_wa_all(struct b43_wldev *dev);
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#endif /* B43_WA_H_ */
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