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Merge branch 'master' of /home/davem/src/GIT/linux-2.6/

Browse Source
This commit is contained in:
David S. Miller
2009-02-04 16:51:58 -08:00
parent 4d7902f22b eda58a85ec
commit 005c79b3d4
148 changed files with 2448 additions and 1808 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/filesystems/ubifs.txt
View File

@@ -79,13 +79,6 @@ Mount options
(*) == default.
norm_unmount (*) commit on unmount; the journal is committed
when the file-system is unmounted so that the
next mount does not have to replay the journal
and it becomes very fast;
fast_unmount do not commit on unmount; this option makes
unmount faster, but the next mount slower
because of the need to replay the journal.
bulk_read read more in one go to take advantage of flash
media that read faster sequentially
no_bulk_read (*) do not bulk-read

2
MAINTAINERS
View File

@@ -911,7 +911,7 @@ S: Maintained
BLACKFIN ARCHITECTURE
P: Bryan Wu
M: cooloney@kernel.org
L: uclinux-dist-devel@blackfin.uclinux.org (subscribers-only)
L: uclinux-dist-devel@blackfin.uclinux.org
W: http://blackfin.uclinux.org
S: Supported

1
arch/arm/kernel/entry-armv.S
View File

@@ -650,6 +650,7 @@ ENTRY(fp_enter)
no_fp: mov pc, lr
__und_usr_unknown:
enable_irq
mov r0, sp
adr lr, ret_from_exception
b do_undefinstr

2
arch/arm/kernel/entry-common.S
View File

@@ -136,7 +136,7 @@ ENTRY(mcount)
ldmia sp!, {r0-r3, pc}
trace:
ldr r1, [fp, #-4]
ldr r1, [fp, #-4] @ lr of instrumented routine
mov r0, lr
sub r0, r0, #MCOUNT_INSN_SIZE
mov lr, pc

2
arch/arm/kernel/irq.c
View File

@@ -101,7 +101,7 @@ unlock:
/* Handle bad interrupts */
static struct irq_desc bad_irq_desc = {
.handle_irq = handle_bad_irq,
.lock = SPIN_LOCK_UNLOCKED
.lock = __SPIN_LOCK_UNLOCKED(bad_irq_desc.lock),
};
/*

1
arch/arm/mach-msm/board-halibut.c
View File

@@ -27,6 +27,7 @@
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <mach/irqs.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>

2
arch/arm/mach-omap1/devices.c
View File

@@ -181,7 +181,7 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
}
size = OMAP1_MMC_SIZE;
omap_mmc_add(i, base, size, irq, mmc_data[i]);
omap_mmc_add("mmci-omap", i, base, size, irq, mmc_data[i]);
};
}

98
arch/arm/mach-omap1/mcbsp.c
View File

@@ -28,81 +28,8 @@
#define DPS_RSTCT2_PER_EN (1 << 0)
#define DSP_RSTCT2_WD_PER_EN (1 << 1)
struct mcbsp_internal_clk {
struct clk clk;
struct clk **childs;
int n_childs;
};
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
{
const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
int i;
mclk->n_childs = ARRAY_SIZE(clk_names);
mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
GFP_KERNEL);
for (i = 0; i < mclk->n_childs; i++) {
/* We fake a platform device to get correct device id */
struct platform_device pdev;
pdev.dev.bus = &platform_bus_type;
pdev.id = mclk->clk.id;
mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
if (IS_ERR(mclk->childs[i]))
printk(KERN_ERR "Could not get clock %s (%d).\n",
clk_names[i], mclk->clk.id);
}
}
static int omap_mcbsp_clk_enable(struct clk *clk)
{
struct mcbsp_internal_clk *mclk = container_of(clk,
struct mcbsp_internal_clk, clk);
int i;
for (i = 0; i < mclk->n_childs; i++)
clk_enable(mclk->childs[i]);
return 0;
}
static void omap_mcbsp_clk_disable(struct clk *clk)
{
struct mcbsp_internal_clk *mclk = container_of(clk,
struct mcbsp_internal_clk, clk);
int i;
for (i = 0; i < mclk->n_childs; i++)
clk_disable(mclk->childs[i]);
}
static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
{
.clk = {
.name = "mcbsp_clk",
.id = 1,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
{
.clk = {
.name = "mcbsp_clk",
.id = 3,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
};
#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
#else
#define omap_mcbsp_clks_size 0
static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
{ }
const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
#endif
static void omap1_mcbsp_request(unsigned int id)
@@ -167,8 +94,9 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
.rx_irq = INT_McBSP1RX,
.tx_irq = INT_McBSP1TX,
.ops = &omap1_mcbsp_ops,
.clk_name = "mcbsp_clk",
},
.clk_names = clk_names,
.num_clks = 3,
},
{
.phys_base = OMAP1510_MCBSP2_BASE,
.dma_rx_sync = OMAP_DMA_MCBSP2_RX,
@@ -184,7 +112,8 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
.rx_irq = INT_McBSP3RX,
.tx_irq = INT_McBSP3TX,
.ops = &omap1_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 3,
},
};
#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
@@ -202,7 +131,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
.rx_irq = INT_McBSP1RX,
.tx_irq = INT_McBSP1TX,
.ops = &omap1_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 3,
},
{
.phys_base = OMAP1610_MCBSP2_BASE,
@@ -219,7 +149,8 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
.rx_irq = INT_McBSP3RX,
.tx_irq = INT_McBSP3TX,
.ops = &omap1_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 3,
},
};
#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
@@ -230,15 +161,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
int __init omap1_mcbsp_init(void)
{
int i;
for (i = 0; i < omap_mcbsp_clks_size; i++) {
if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
clk_register(&omap_mcbsp_clks[i].clk);
}
}
if (cpu_is_omap730())
omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
if (cpu_is_omap15xx())

11
arch/arm/mach-omap2/devices.c
View File

@@ -421,6 +421,7 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
int nr_controllers)
{
int i;
char *name;
for (i = 0; i < nr_controllers; i++) {
unsigned long base, size;
@@ -450,12 +451,14 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
continue;
}
if (cpu_is_omap2420())
if (cpu_is_omap2420()) {
size = OMAP2420_MMC_SIZE;
else
name = "mmci-omap";
} else {
size = HSMMC_SIZE;
omap_mmc_add(i, base, size, irq, mmc_data[i]);
name = "mmci-omap-hs";
}
omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
};
}

6
arch/arm/mach-omap2/id.c
View File

@@ -172,9 +172,13 @@ void __init omap34xx_check_revision(void)
omap_revision = OMAP3430_REV_ES3_0;
rev_name = "ES3.0";
break;
case 4:
omap_revision = OMAP3430_REV_ES3_1;
rev_name = "ES3.1";
break;
default:
/* Use the latest known revision as default */
omap_revision = OMAP3430_REV_ES3_0;
omap_revision = OMAP3430_REV_ES3_1;
rev_name = "Unknown revision\n";
}
}

1
arch/arm/mach-omap2/irq.c
View File

@@ -134,6 +134,7 @@ static struct irq_chip omap_irq_chip = {
.ack = omap_mask_ack_irq,
.mask = omap_mask_irq,
.unmask = omap_unmask_irq,
.disable = omap_mask_irq,
};
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)

145
arch/arm/mach-omap2/mcbsp.c
View File

@@ -24,106 +24,7 @@
#include <mach/cpu.h>
#include <mach/mcbsp.h>
struct mcbsp_internal_clk {
struct clk clk;
struct clk **childs;
int n_childs;
};
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
{
const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
int i;
mclk->n_childs = ARRAY_SIZE(clk_names);
mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
GFP_KERNEL);
for (i = 0; i < mclk->n_childs; i++) {
/* We fake a platform device to get correct device id */
struct platform_device pdev;
pdev.dev.bus = &platform_bus_type;
pdev.id = mclk->clk.id;
mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
if (IS_ERR(mclk->childs[i]))
printk(KERN_ERR "Could not get clock %s (%d).\n",
clk_names[i], mclk->clk.id);
}
}
static int omap_mcbsp_clk_enable(struct clk *clk)
{
struct mcbsp_internal_clk *mclk = container_of(clk,
struct mcbsp_internal_clk, clk);
int i;
for (i = 0; i < mclk->n_childs; i++)
clk_enable(mclk->childs[i]);
return 0;
}
static void omap_mcbsp_clk_disable(struct clk *clk)
{
struct mcbsp_internal_clk *mclk = container_of(clk,
struct mcbsp_internal_clk, clk);
int i;
for (i = 0; i < mclk->n_childs; i++)
clk_disable(mclk->childs[i]);
}
static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
{
.clk = {
.name = "mcbsp_clk",
.id = 1,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
{
.clk = {
.name = "mcbsp_clk",
.id = 2,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
{
.clk = {
.name = "mcbsp_clk",
.id = 3,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
{
.clk = {
.name = "mcbsp_clk",
.id = 4,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
{
.clk = {
.name = "mcbsp_clk",
.id = 5,
.enable = omap_mcbsp_clk_enable,
.disable = omap_mcbsp_clk_disable,
},
},
};
#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
#else
#define omap_mcbsp_clks_size 0
static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
static inline void omap_mcbsp_clk_init(struct clk *clk)
{ }
#endif
const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
static void omap2_mcbsp2_mux_setup(void)
{
@@ -156,7 +57,8 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP24XX_MCBSP2_BASE,
@@ -165,7 +67,8 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
};
#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
@@ -183,7 +86,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP24XX_MCBSP2_BASE,
@@ -192,7 +96,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP2430_MCBSP3_BASE,
@@ -201,7 +106,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP2430_MCBSP4_BASE,
@@ -210,7 +116,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP2430_MCBSP5_BASE,
@@ -219,7 +126,8 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
};
#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
@@ -237,7 +145,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP1_IRQ_RX,
.tx_irq = INT_24XX_MCBSP1_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP34XX_MCBSP2_BASE,
@@ -246,7 +155,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP2_IRQ_RX,
.tx_irq = INT_24XX_MCBSP2_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP34XX_MCBSP3_BASE,
@@ -255,7 +165,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP3_IRQ_RX,
.tx_irq = INT_24XX_MCBSP3_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP34XX_MCBSP4_BASE,
@@ -264,7 +175,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP4_IRQ_RX,
.tx_irq = INT_24XX_MCBSP4_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
{
.phys_base = OMAP34XX_MCBSP5_BASE,
@@ -273,7 +185,8 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
.rx_irq = INT_24XX_MCBSP5_IRQ_RX,
.tx_irq = INT_24XX_MCBSP5_IRQ_TX,
.ops = &omap2_mcbsp_ops,
.clk_name = "mcbsp_clk",
.clk_names = clk_names,
.num_clks = 2,
},
};
#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
@@ -284,14 +197,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
static int __init omap2_mcbsp_init(void)
{
int i;
for (i = 0; i < omap_mcbsp_clks_size; i++) {
/* Once we call clk_get inside init, we do not register it */
omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
clk_register(&omap_mcbsp_clks[i].clk);
}
if (cpu_is_omap2420())
omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
if (cpu_is_omap2430())

3
arch/arm/mach-omap2/sleep24xx.S
View File

@@ -93,9 +93,8 @@ ENTRY(omap24xx_cpu_suspend)
orr r4, r4, #0x40 @ enable self refresh on idle req
mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
str r4, [r2] @ make it so
mov r2, #0
nop
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
nop
loop:
subs r5, r5, #0x1 @ awake, wait just a bit

3
arch/arm/mach-omap2/timer-gp.c
View File

@@ -118,7 +118,8 @@ static void __init omap2_gp_clockevent_init(void)
clockevent_gpt.max_delta_ns =
clockevent_delta2ns(0xffffffff, &clockevent_gpt);
clockevent_gpt.min_delta_ns =
clockevent_delta2ns(1, &clockevent_gpt);
clockevent_delta2ns(3, &clockevent_gpt);
/* Timer internal resynch latency. */
clockevent_gpt.cpumask = cpumask_of(0);
clockevents_register_device(&clockevent_gpt);

2
arch/arm/mach-sa1100/generic.c
View File

@@ -289,7 +289,7 @@ static struct platform_device sa11x0pcmcia_device = {
};
static struct platform_device sa11x0mtd_device = {
.name = "flash",
.name = "sa1100-mtd",
.id = -1,
};

5
arch/arm/mm/fault-armv.c
View File

@@ -66,7 +66,10 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
* fault (ie, is old), we can safely ignore any issues.
*/
if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
flush_cache_page(vma, address, pte_pfn(entry));
unsigned long pfn = pte_pfn(entry);
flush_cache_page(vma, address, pfn);
outer_flush_range((pfn << PAGE_SHIFT),
(pfn << PAGE_SHIFT) + PAGE_SIZE);
pte_val(entry) &= ~L_PTE_MT_MASK;
pte_val(entry) |= shared_pte_mask;
set_pte_at(vma->vm_mm, address, pte, entry);

7
arch/arm/plat-omap/devices.c
View File

@@ -200,14 +200,15 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
/*
* Register MMC devices. Called from mach-omap1 and mach-omap2 device init.
*/
int __init omap_mmc_add(int id, unsigned long base, unsigned long size,
unsigned int irq, struct omap_mmc_platform_data *data)
int __init omap_mmc_add(const char *name, int id, unsigned long base,
unsigned long size, unsigned int irq,
struct omap_mmc_platform_data *data)
{
struct platform_device *pdev;
struct resource res[OMAP_MMC_NR_RES];
int ret;
pdev = platform_device_alloc("mmci-omap", id);
pdev = platform_device_alloc(name, id);
if (!pdev)
return -ENOMEM;

5
arch/arm/plat-omap/dma.c
View File

@@ -709,6 +709,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
chan->flags = 0;
#ifndef CONFIG_ARCH_OMAP1
if (cpu_class_is_omap2()) {
@@ -1888,11 +1889,11 @@ static int omap2_dma_handle_ch(int ch)
status = dma_read(CSR(ch));
}
dma_write(status, CSR(ch));
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
dma_write(status, CSR(ch));
return 0;
}

1
arch/arm/plat-omap/include/mach/cpu.h
View File

@@ -339,6 +339,7 @@ IS_OMAP_TYPE(3430, 0x3430)
#define OMAP3430_REV_ES2_0 0x34301034
#define OMAP3430_REV_ES2_1 0x34302034
#define OMAP3430_REV_ES3_0 0x34303034
#define OMAP3430_REV_ES3_1 0x34304034
/*
* omap_chip bits

6
arch/arm/plat-omap/include/mach/mcbsp.h
View File

@@ -344,7 +344,8 @@ struct omap_mcbsp_platform_data {
u8 dma_rx_sync, dma_tx_sync;
u16 rx_irq, tx_irq;
struct omap_mcbsp_ops *ops;
char const *clk_name;
char const **clk_names;
int num_clks;
};
struct omap_mcbsp {
@@ -376,7 +377,8 @@ struct omap_mcbsp {
/* Protect the field .free, while checking if the mcbsp is in use */
spinlock_t lock;
struct omap_mcbsp_platform_data *pdata;
struct clk *clk;
struct clk **clks;
int num_clks;
};
extern struct omap_mcbsp **mcbsp_ptr;
extern int omap_mcbsp_count;

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