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Merge commit 'bc95e6862a3f13d4ae07e5a5265f142641bdef02'

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* commit 'bc95e6862a3f13d4ae07e5a5265f142641bdef02':
  media: i2c: mis4001 driver update version 0.01.02
  arm64: dts: rockchip: rk3562: Add csu-clocks for vop
  drm/rockchip: vop2: Add csu clock support for rk3562
  arm64: dts: rockchip: rk3562: Add rockchip,csu for gmac
  ethernet: stmmac: dwmac-rk: Add csu clock support
  arm64: dts: rockchip: rk3562: Add csu device node
  Revert "arm64: dts: rockchip: rk3562-rk817-tablet-v10: Change clkin div to 5 for aclk vo"
  Revert "arm64: dts: rockchip: rk3562-evb1-lp4x-v10: Change clkin div to 5 for aclk vo"
  arm64: configs: rockchip_linux_defconfig: Enable CONFIG_ROCKCHIP_CSU
  arm64: configs: rockchip_defconfig: Enable CONFIG_ROCKCHIP_CSU
  soc: rockchip: Add clock subunit driver
  arm64: dts: rockchip: px30: add pwm irq configs
  PCI: rockchip: dw: Reserve msi_data in obj_info
  misc: rockchip: pcie-rkep: Support mmap bar resource and rw config space
  misc: rockchip: pcie-rkep: Adding more mmap resources
  media: rockchip: isp: fix wnd_num cause array access out of bounds
  mfd: rk806: Add RK806 support i2c
  PCI: rockchip: dw: Validate phy mode in suspend
  phy: rockchip: naneng-combphy: Add phy_validate support
  arm64: dts: rockchip: add lvds demo dts for rk3567/rk3568

Change-Id: I610c43a60826e361c65a6e1d4fa23da6a56653fa
This commit is contained in:
Tao Huang
2023-12-01 20:43:53 +08:00
parent f3e269432c bc95e6862a
commit fa453b17a5
39 changed files with 2060 additions and 529 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -152,14 +152,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-single-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-lvds-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-amp.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-spi-nor.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-single-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb4-lp3-v10.dtb

10
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@@ -1048,6 +1048,7 @@
pwm0: pwm@ff200000 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200000 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1059,6 +1060,7 @@
pwm1: pwm@ff200010 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200010 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1070,6 +1072,7 @@
pwm2: pwm@ff200020 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200020 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1081,6 +1084,8 @@
pwm3: pwm@ff200030 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff200030 0x0 0x10>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1092,6 +1097,7 @@
pwm4: pwm@ff208000 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208000 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1103,6 +1109,7 @@
pwm5: pwm@ff208010 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208010 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1114,6 +1121,7 @@
pwm6: pwm@ff208020 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208020 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";
@@ -1125,6 +1133,8 @@
pwm7: pwm@ff208030 {
compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xff208030 0x0 0x10>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-names = "active";

12
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
View File

@@ -179,18 +179,6 @@
};
};
&bus_soc {
rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
&gmac0 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";

12
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
View File

@@ -209,18 +209,6 @@
cpu-supply = <&vdd_cpu>;
};
&bus_soc {
rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
&dfi {
status = "okay";
};

38
arch/arm64/boot/dts/rockchip/rk3562.dtsi
View File

@@ -9,6 +9,7 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/rk3562-power.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip-csu.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/soc/rockchip-system-status.h>
#include <dt-bindings/suspend/rockchip-rk3562.h>
@@ -361,20 +362,6 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
bus_soc: bus-soc {
compatible = "rockchip,rk3562-bus";
rockchip,busfreq-policy = "smc";
rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a4 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
cpuinfo {
compatible = "rockchip,cpuinfo";
nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
@@ -423,6 +410,23 @@
status = "disabled";
};
csu: csu {
compatible = "rockchip,rk3562-csu";
rockchip,clock = <CSU_GMAC_ACLK 1>,
<CSU_GMAC_PCLK 3>,
<CSU_VOP_ACLK 4>,
<CSU_MCU_CLK 2>;
rockchip,bus = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a4 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
display_subsystem: display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
@@ -1896,6 +1900,8 @@
reset-names = "axi",
"ahb",
"dclk_vp0";
rockchip,csu = <&csu CSU_VOP_ACLK>;
rockchip,csu-names = "aclk";
iommus = <&vop_mmu>;
power-domains = <&power RK3562_PD_VO>;
rockchip,grf = <&ioc_grf>;
@@ -2837,6 +2843,8 @@
"pclk_mac", "aclk_mac";
resets = <&cru SRST_A_GMAC>;
reset-names = "stmmaceth";
rockchip,csu = <&csu CSU_GMAC_ACLK>, <&csu CSU_GMAC_PCLK>;
rockchip,csu-names = "aclk", "pclk";
snps,mixed-burst;
snps,tso;
@@ -2955,6 +2963,8 @@
"pclk_mac", "aclk_mac";
resets = <&cru SRST_A_MAC100>;
reset-names = "stmmaceth";
rockchip,csu = <&csu CSU_GMAC_ACLK>, <&csu CSU_GMAC_PCLK>;
rockchip,csu-names = "aclk", "pclk";
status = "disabled";
mdio1: mdio {

108
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts
View File

@@ -70,68 +70,14 @@
};
};
&backlight1 {
status = "okay";
};
&backlight {
status = "okay";
};
&lvds {
status = "okay";
dual-channel;
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds1 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds1_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&lvds_in_vp1 {
&backlight1 {
status = "okay";
};
&lvds1_in_vp1 {
status = "disabled";
};
&lvds1_in_vp2 {
status = "okay";
};
/* enable hdmi */
&hdmi_in_vp1 {
status = "okay";
};
/* enable video phy */
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};
/* disable other encoder output */
&dsi0 {
status = "disabled";
};
@@ -152,10 +98,52 @@
status = "disabled";
};
&rgb_in_vp2 {
&hdmi_in_vp1 {
status = "okay";
};
&lvds0 {
status = "okay";
dual-channel;
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds0_in_vp1 {
status = "okay";
};
&lvds1 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds1_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&lvds1_in_vp1 {
status = "okay";
};
&lvds1_in_vp2 {
status = "disabled";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
@@ -166,3 +154,11 @@
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

88
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-lvds.dts → arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dts
View File

@@ -13,8 +13,8 @@
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3567 EVB2 LP4X V10 Board";
compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567";
model = "Rockchip RK3567 EVB2 LP4X V10 Board with one vp two single channel lvds";
compatible = "rockchip,rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds", "rockchip,rk3567";
/* panel: claa070wp03xg */
panel {
@@ -34,7 +34,7 @@
timing0: timing0 {
clock-frequency = <134000000>;
hactive = <1600>;
hactive = <1600>; /* each panel show 1600 / 2 = 800 pxiel */
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
@@ -75,15 +75,39 @@
};
};
&backlight1 {
status = "okay";
};
&backlight {
status = "okay";
};
&lvds {
&backlight1 {
status = "okay";
};
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "okay";
};
&lvds0 {
status = "okay";
dual-channel;
@@ -110,50 +134,15 @@
};
};
&lvds_in_vp1 {
&lvds0_in_vp1 {
status = "okay";
};
&lvds1_in_vp1 {
status = "disabled";
status = "okay";
};
&lvds1_in_vp2 {
status = "okay";
};
/* enable hdmi */
&hdmi_in_vp1 {
status = "okay";
};
/* enable video phy */
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};
/* disable other encoder output */
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
@@ -161,7 +150,6 @@
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
@@ -171,3 +159,11 @@
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

136
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-single-channel-lvds.dts Normal file
View File

@@ -0,0 +1,136 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3567-evb2-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3567 EVB2 LP4X V10 Board with single channel lvds";
compatible = "rockchip,rk3567-evb2-lp4x-v10-single-channel-lvds", "rockchip,rk3567";
/* panel: claa070wp03xg */
panel {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd0_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out_panel>;
};
};
};
};
};
&backlight {
status = "okay";
};
&backlight1 {
status = "okay";
};
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds0_in_vp1 {
status = "okay";
};
&lvds1 {
status = "disabled";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

201
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dts Normal file
View File

@@ -0,0 +1,201 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3567-evb2-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3567 EVB2 LP4X V10 Board with two vp two separate single channel lvds";
compatible = "rockchip,rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds", "rockchip,rk3567";
/**
* VP1 -> LVDS0 -> Panel0
* VP2 -> LVDS1 -> Panel1
*/
/* panel: claa070wp03xg */
panel-lvds0 {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd0_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out_panel>;
};
};
};
};
/* panel: claa070wp03xg */
panel-lvds1 {
compatible = "simple-panel";
backlight = <&backlight1>;
power-supply = <&vcc3v3_lcd1_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing1>;
timing1: timing1 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds1_out_panel>;
};
};
};
};
};
&backlight {
status = "okay";
};
&backlight1 {
status = "okay";
};
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds0_in_vp1 {
status = "okay";
};
&lvds1 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds1_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&lvds1_in_vp1 {
status = "disabled";
};
&lvds1_in_vp2 {
status = "okay";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

14
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-lvds.dts
View File

@@ -1,14 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rk3568-evb1-ddr4-v10-dual-lvds.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3568 EVB1 V10 Board with Dual LVDS";
compatible = "rockchip,rk3568-evb1-ddr4-v10-dual-lvds", "rockchip,rk3568";
};

6
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-lvds-linux.dts → arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds-linux.dts
View File

@@ -6,12 +6,12 @@
/dts-v1/;
#include <dt-bindings/display/rockchip_vop.h>
#include "rk3568-evb1-ddr4-v10-dual-lvds.dtsi"
#include "rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi"
#include "rk3568-linux.dtsi"
/ {
model = "Rockchip RK3568 EVB1 V10 Board with Dual LVDS";
compatible = "rockchip,rk3568-evb1-ddr4-v10-dual-lvds", "rockchip,rk3568";
model = "Rockchip RK3568 EVB1 V10 Board with one vp two single channel lvds";
compatible = "rockchip,rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds", "rockchip,rk3568";
};
&vp0 {

14
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dts Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3568 EVB1 V10 Board with one vp two single channel lvds";
compatible = "rockchip,rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds", "rockchip,rk3568";
};

36
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-dual-lvds.dtsi → arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi
View File

@@ -27,7 +27,7 @@
timing0: timing0 {
clock-frequency = <134000000>;
hactive = <1600>;
hactive = <1600>; /* each panel show 1600 / 2 = 800 pxiel */
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
@@ -68,11 +68,11 @@
};
};
&backlight1 {
&backlight {
status = "okay";
};
&backlight {
&backlight1 {
status = "okay";
};
@@ -100,7 +100,7 @@
status = "okay";
};
&lvds {
&lvds0 {
status = "okay";
dual-channel;
@@ -114,6 +114,10 @@
};
};
&lvds0_in_vp1 {
status = "okay";
};
&lvds1 {
status = "okay";
@@ -127,30 +131,18 @@
};
};
&lvds_in_vp1 {
status = "okay";
};
&lvds1_in_vp1 {
status = "disabled";
status = "okay";
};
&lvds1_in_vp2 {
status = "okay";
status = "disabled";
};
&rgb_in_vp2 {
status = "disabled";
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
@@ -160,3 +152,11 @@
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

133
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-single-channel-lvds.dts Normal file
View File

@@ -0,0 +1,133 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568-evb1-ddr4-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3568 EVB1 V10 Board with single channel lvds";
compatible = "rockchip,rk3568-evb1-ddr4-v10-single-channel-lvds", "rockchip,rk3568";
/* panel: claa070wp03xg */
panel-lvds0 {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd0_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out_panel>;
};
};
};
};
};
&backlight {
status = "okay";
};
&backlight1 {
status = "okay";
};
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds0_in_vp1 {
status = "okay";
};
&lvds1 {
status = "disabled";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

198
arch/arm64/boot/dts/rockchip/rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds.dts Normal file
View File

@@ -0,0 +1,198 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568-evb1-ddr4-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3568 EVB1 V10 Board with two vp two separate single channel lvds";
compatible = "rockchip,rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds", "rockchip,rk3568";
/**
* VP1 -> LVDS0 -> Panel0
* VP2 -> LVDS1 -> Panel1
*/
/* panel: claa070wp03xg */
panel-lvds0 {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd0_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out_panel>;
};
};
};
};
/* panel: claa070wp03xg */
panel-lvds1 {
compatible = "simple-panel";
backlight = <&backlight1>;
power-supply = <&vcc3v3_lcd1_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing1>;
timing1: timing1 {
clock-frequency = <67000000>;
hactive = <800>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <8>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds1_out_panel>;
};
};
};
};
};
&backlight {
status = "okay";
};
&backlight1 {
status = "okay";
};
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&hdmi_in_vp1 {
status = "okay";
};
&lvds0 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds0_in_vp1 {
status = "okay";
};
&lvds1 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds1_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&lvds1_in_vp1 {
status = "disabled";
};
&lvds1_in_vp2 {
status = "okay";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};

1
arch/arm64/configs/rockchip_defconfig
View File

@@ -899,6 +899,7 @@ CONFIG_CPU_RK3562=y
CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_CSU=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_IPA=y

1
arch/arm64/configs/rockchip_linux_defconfig
View File

@@ -514,6 +514,7 @@ CONFIG_CPU_RK3568=y
CONFIG_CPU_RK3588=y
CONFIG_ROCKCHIP_AMP=y
CONFIG_ROCKCHIP_CPUINFO=y
CONFIG_ROCKCHIP_CSU=y
CONFIG_ROCKCHIP_GRF=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_IPA=y

30
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
View File

@@ -46,6 +46,7 @@
#include <linux/rockchip/cpu.h>
#include <linux/workqueue.h>
#include <linux/types.h>
#include <soc/rockchip/rockchip_csu.h>
#include <soc/rockchip/rockchip_dmc.h>
#include <soc/rockchip/rockchip-system-status.h>
#include <uapi/linux/videodev2.h>
@@ -885,6 +886,7 @@ struct vop2 {
struct clk *pclk;
struct reset_control *ahb_rst;
struct reset_control *axi_rst;
struct csu_clk *csu_aclk;
/* list_head of extend clk */
struct list_head extend_clk_list_head;
@@ -6111,6 +6113,27 @@ static int vop2_crtc_get_inital_acm_info(struct drm_crtc *crtc)
return 0;
}
static void vop2_crtc_csu_set_rate(struct drm_crtc *crtc)
{
struct vop2_video_port *vp = to_vop2_video_port(crtc);
struct vop2 *vop2 = vp->vop2;
unsigned long aclk_rate = 0, dclk_rate = 0;
u32 csu_div = 0;
if (!vop2->csu_aclk)
return;
aclk_rate = clk_get_rate(vop2->aclk);
dclk_rate = clk_get_rate(vp->dclk);
if (!dclk_rate)
return;
/* aclk >= 1/2 * dclk */
csu_div = aclk_rate * 2 / dclk_rate;
rockchip_csu_set_div(vop2->csu_aclk, csu_div);
}
static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
{
struct vop2_video_port *vp = to_vop2_video_port(crtc);
@@ -6190,6 +6213,8 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data)
cubic_lut_mst = cubic_lut->offset + private->cubic_lut_dma_addr;
VOP_MODULE_SET(vop2, vp, cubic_lut_mst, cubic_lut_mst);
}
vop2_crtc_csu_set_rate(crtc);
} else {
vop2_crtc_atomic_disable(crtc, NULL);
}
@@ -8123,6 +8148,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_sta
if (is_vop3(vop2))
vop3_setup_pipe_dly(vp, NULL);
vop2_crtc_csu_set_rate(crtc);
vop2_cfg_done(crtc);
/*
@@ -11974,6 +12000,10 @@ static int vop2_bind(struct device *dev, struct device *master, void *data)
return PTR_ERR(vop2->axi_rst);
}
vop2->csu_aclk = rockchip_csu_get(dev, "aclk");
if (IS_ERR(vop2->csu_aclk))
vop2->csu_aclk = NULL;
vop2->irq = platform_get_irq(pdev, 0);
if (vop2->irq < 0) {
DRM_DEV_ERROR(dev, "cannot find irq for vop2\n");

578
drivers/media/i2c/mis4001.c
View File

File diff suppressed because it is too large Load Diff

18
drivers/media/platform/rockchip/isp/isp_params_v21.c
View File

@@ -1178,6 +1178,12 @@ isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
ISP2X_REG_WR_MASK);
wnd_num_idx = arg->wnd_num;
if (wnd_num_idx >= ARRAY_SIZE(ae_wnd_num)) {
wnd_num_idx = ARRAY_SIZE(ae_wnd_num) - 1;
dev_err(params_vdev->dev->dev,
"%s invalid wnd_num:%d, set to %d\n",
__func__, arg->wnd_num, wnd_num_idx);
}
value |= ISP2X_RAWAEBIG_WNDNUM_SET(wnd_num_idx);
if (arg->subwin_en[0])
@@ -2291,6 +2297,12 @@ isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
return;
wnd_num_idx = arg->wnd_num;
if (wnd_num_idx >= ARRAY_SIZE(hist_wnd_num)) {
wnd_num_idx = ARRAY_SIZE(hist_wnd_num) - 1;
dev_err(params_vdev->dev->dev,
"%s invalid wnd_num:%d, set to %d\n",
__func__, arg->wnd_num, wnd_num_idx);
}
memset(weight15x15, 0, sizeof(weight15x15));
for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
@@ -2338,6 +2350,12 @@ isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
}
wnd_num_idx = arg->wnd_num;
if (wnd_num_idx >= ARRAY_SIZE(hist_wnd_num)) {
wnd_num_idx = ARRAY_SIZE(hist_wnd_num) - 1;
dev_err(params_vdev->dev->dev,
"%s invalid wnd_num:%d, set to %d\n",
__func__, arg->wnd_num, wnd_num_idx);
}
/* avoid to override the old enable value */
hist_ctrl = rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL);
hist_ctrl &= ISP2X_RAWHSTBIG_CTRL_EN_MASK;

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