Merge commit 'a2d0c7f12f46c81b82f2453a39ea65013d553275'

* commit 'a2d0c7f12f46c81b82f2453a39ea65013d553275': (49 commits) ASoC: rockchip: i2s: Use add_component_controls ASoC: rockchip: i2s-tdm: Add support for PCM R/W Wait Time ASoC: rockchip: i2s-tdm: Add support for PATHx controls ASoC: rockchip: i2s-tdm: Use add_component_controls ASoC: rockchip: multi-dais: Fix component's name_prefix ASoC: rockchip: sai: Fix Transmit SDOx Select ASoC: rockchip: sai: Reduce FIFO XRUN warning prompt media: rockchip: hdmirx: avoid PKTDEC_AVIIF_CHG_IRQ mistrigger. video: rockchip: mpp: rkvenc2: fix slice mode poll failed arm64: dts: rockchip: px30: Add reboot_mode label for Android ARM: dts: rockchip: add rv1106g-evb1-v11-nofastae-spi-nand PCI: rockchip: dw: Use handle_level_irq for legacy irq arm64: dts: rockchip: rk3562-amp: Move the rpmsg node backwards. arm64: dts: rockchip: rk3568-amp: Move the rpmsg node backwards. arm64: dts: rockchip: rk3588-amp: support ap rpmsg rpmsg: rockchip: use rockchip,rpmsg for all rockchip platform arm64: dts: rockchip: rk3588-vehicle-evb: add v22 dts files and use serdes-mfd-display default mailbox: rockchip: Add Rockchip MBOX Demo arm64: dts: rockchip: add rk3588 evb1 lp4 v10 linux amp dts arm64: dts: rockchip: rk3588-amp: support ap core for amp ... Change-Id: I13bb9ab1c3def29f25b18c67ee73d915b17ec817 Conflicts: drivers/gpio/Kconfig drivers/media/i2c/maxim4c/Kconfig
2026-01-06 11:08:10 -08:00 · 2023-09-28 09:23:21 +08:00
parent a420b993b2 a2d0c7f12f
commit dfd3eeaf2b
60 changed files with 11207 additions and 601 deletions
--- a/Documentation/devicetree/bindings/gpio/novo,nca9539-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/novo,nca9539-gpio.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/novo,nca9539-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novosense I2C GPIO controller
+
+maintainers:
+  - Cody Xie <cody.xie@rock-chips.com>
+
+description: |
+  This controller is A GPIO expander with I2C interface and one interrupt pin.
+
+properties:
+  compatible:
+    const: novo,nca9539-gpio
+
+  reg:
+    items:
+      - description: the I2C address containing the GPIO controller registers.
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  ngpios:
+    minimum: 0
+    maximum: 32
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 2
+
+  interrupts:
+    maxItems: 1
+
+  vdd-supply:
+    - description: the regulator for the VDD supplier.
+
+required:
+  - compatible
+  - reg
+  - "#gpio-cells"
+  - gpio-controller
+  - vdd-supply
+
+additionalProperties: false
+
+dependencies:
+  interrupt-controller: [ interrupts ]
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    / {
+	  nca9539_vdd: nca9539-vdd {
+		compatible = "regulator-fixed";
+		regulator-name = "nca9539_vdd";
+		enable-active-high;
+		regulator-boot-on;
+		regulator-always-on;
+	  };
+	};
+
+    nca9539_gpio: gpio@74 {
+		compatible = "novo,nca9539-gpio";
+        reg = <0x74>;
+        gpio-controller;
+        #gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vdd-supply = <&nca9539_vdd>;
+    };
+
+
+...
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1145,6 +1145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1106g-evb1-v11-facial-gate.dtb \
 	rv1106g-evb1-v10-spi-nand.dtb \
 	rv1106g-evb1-v10-spi-nor.dtb \
+	rv1106g-evb1-v11-nofastae-spi-nand.dtb \
 	rv1106g-evb2-v10.dtb \
 	rv1106g-evb2-v10-dual-camera.dtb \
 	rv1106g-evb2-v11-emmc.dtb \
--- a/arch/arm/boot/dts/rv1106g-evb1-v11-nofastae-spi-nand.dts
+++ b/arch/arm/boot/dts/rv1106g-evb1-v11-nofastae-spi-nand.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "rv1106g-evb1-v11.dts"
+#include "rv1106-tb-nofastae.dtsi"
+
+/ {
+	model = "Rockchip RV1106G EVB1 V11 Board";
+	compatible = "rockchip,rv1106g-evb1-v11", "rockchip,rv1106";
+	chosen {
+		bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
+	};
+};
+
+&fiq_debugger {
+	rockchip,baudrate = <1500000>;
+};
+
+&ramdisk_r {
+	reg = <0x800000 (15 * 0x00100000)>;
+};
+
+&ramdisk_c {
+	reg = <0x1700000 (10 * 0x00100000)>;
+};
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -145,6 +145,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-channel-lvds.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-lvds.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb
@@ -211,6 +213,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-amp.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-ipc.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-lt6911uxe.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10.dtb
@@ -248,6 +251,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-linux.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v20.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v21.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v22.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-s66-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10-linux.dtb
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -652,7 +652,7 @@
 			status = "disabled";
 		};

-		reboot-mode {
+		reboot_mode: reboot-mode {
 			compatible = "syscon-reboot-mode";
 			offset = <0x200>;
 			mode-bootloader = <BOOT_BL_DOWNLOAD>;
--- a/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
@@ -22,18 +22,6 @@
 		status = "okay";
 	};

-	rpmsg: rpmsg@7c00000 {
-		compatible = "rockchip,rk3562-rpmsg";
-		mbox-names = "rpmsg-rx", "rpmsg-tx";
-		mboxes = <&mailbox 0 &mailbox 3>;
-		rockchip,vdev-nums = <1>;
-		rockchip,link-id = <0x04>;
-		reg = <0x0 0x7c00000 0x0 0x20000>;
-		memory-region = <&rpmsg_dma_reserved>;
-
-		status = "okay";
-	};
-
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -63,6 +51,18 @@
 		};

 	};
+
+	rpmsg: rpmsg@7c00000 {
+		compatible = "rockchip,rpmsg";
+		mbox-names = "rpmsg-rx", "rpmsg-tx";
+		mboxes = <&mailbox 0 &mailbox 3>;
+		rockchip,vdev-nums = <1>;
+		rockchip,link-id = <0x04>;
+		reg = <0x0 0x7c00000 0x0 0x20000>;
+		memory-region = <&rpmsg_dma_reserved>;
+
+		status = "okay";
+	};
 };

 &mailbox {
--- a/arch/arm64/boot/dts/rockchip/rk3562.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3562.dtsi
@@ -2266,6 +2266,7 @@
 			     &i2s0m0_sdo2
 			     &i2s0m0_sdo3>;
 		#sound-dai-cells = <0>;
+		sound-name-prefix = "SAI0";
 		status = "disabled";
 	};

@@ -2293,6 +2294,7 @@
 			     &i2s1m0_sdo2
 			     &i2s1m0_sdo3>;
 		#sound-dai-cells = <0>;
+		sound-name-prefix = "SAI1";
 		status = "disabled";
 	};

@@ -2314,6 +2316,7 @@
 			     &i2s2m0_sdi
 			     &i2s2m0_sdo>;
 		#sound-dai-cells = <0>;
+		sound-name-prefix = "SAI2";
 		status = "disabled";
 	};

--- a/arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/display/media-bus-format.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#include "rk3567-evb2-lp4x-v10.dtsi"
+#include "rk3568-android.dtsi"
+
+/ {
+	model = "Rockchip RK3567 EVB2 LP4X V10 Board";
+	compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567";
+
+	panel {
+		compatible = "simple-panel";
+		backlight = <&backlight>;
+		power-supply = <&vcc3v3_lcd0_n>;
+		enable-delay-ms = <20>;
+		prepare-delay-ms = <20>;
+		unprepare-delay-ms = <20>;
+		disable-delay-ms = <20>;
+		bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
+		width-mm = <217>;
+		height-mm = <136>;
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing0 {
+				clock-frequency = <148500000>;
+				hactive = <1920>;
+				vactive = <1080>;
+				hback-porch = <96>;
+				hfront-porch = <120>;
+				vback-porch = <16>;
+				vfront-porch = <64>;
+				hsync-len = <64>;
+				vsync-len = <16>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <0>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+				dual-lvds-odd-pixels;
+				panel_in_lvds0: endpoint {
+					remote-endpoint = <&lvds0_out_panel>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				dual-lvds-even-pixels;
+				panel_in_lvds1: endpoint {
+					remote-endpoint = <&lvds1_out_panel>;
+				};
+			};
+		};
+	};
+};
+
+&backlight1 {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lvds {
+	status = "okay";
+	dual-channel;
+
+	ports {
+		port@1 {
+			reg = <1>;
+			lvds0_out_panel: endpoint {
+				remote-endpoint = <&panel_in_lvds0>;
+			};
+		};
+	};
+};
+
+&lvds1 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+			lvds1_out_panel: endpoint {
+				remote-endpoint = <&panel_in_lvds1>;
+			};
+		};
+	};
+};
+
+&lvds_in_vp1 {
+	status = "okay";
+};
+
+&lvds1_in_vp1 {
+	status = "disabled";
+};
+
+&lvds1_in_vp2 {
+	status = "okay";
+};
+
+/* enable hdmi */
+&hdmi_in_vp1 {
+	status = "okay";
+};
+
+/* enable video phy */
+&video_phy0 {
+	status = "okay";
+};
+
+&video_phy1 {
+	status = "okay";
+};
+
+/* disable other encoder output */
+&dsi0 {
+	status = "disabled";
+};
+
+&dsi0_in_vp0 {
+	status = "disabled";
+};
+
+&dsi0_in_vp1 {
+	status = "disabled";
+};
+
+&dsi1_in_vp1 {
+	status = "disabled";
+};
+
+&edp_in_vp1 {
+	status = "disabled";
+};
+
+&rgb_in_vp2 {
+	status = "disabled";
+};
+
+
+&vcc3v3_lcd0_n {
+	gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
+
+&vcc3v3_lcd1_n {
+	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-lvds.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-lvds.dts
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/display/media-bus-format.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+#include "rk3567-evb2-lp4x-v10.dtsi"
+#include "rk3568-android.dtsi"
+
+/ {
+	model = "Rockchip RK3567 EVB2 LP4X V10 Board";
+	compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567";
+
+	panel {
+		compatible = "simple-panel";
+		backlight = <&backlight>;
+		power-supply = <&vcc3v3_lcd0_n>;
+		enable-delay-ms = <20>;
+		prepare-delay-ms = <20>;
+		unprepare-delay-ms = <20>;
+		disable-delay-ms = <20>;
+		bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
+		width-mm = <217>;
+		height-mm = <136>;
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			timing0: timing0 {
+				clock-frequency = <134000000>;
+				hactive = <1600>;
+				vactive = <1280>;
+				hback-porch = <60>;
+				hfront-porch = <60>;
+				vback-porch = <4>;
+				vfront-porch = <2>;
+				hsync-len = <8>;
+				vsync-len = <2>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <0>;
+				pixelclk-active = <0>;
+			};
+		};
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/**
+			 *  Panel <----> LVDS0
+			 *  Panel <----> LVDS1
+			 */
+			port@0 {
+				reg = <0>;
+				dual-lvds-left-pixels;
+				panel_in_lvds0: endpoint {
+					remote-endpoint = <&lvds0_out_panel>;
+				};
+			};
+			port@1 {
+				reg = <1>;
+				dual-lvds-right-pixels;
+				panel_in_lvds1: endpoint {
+					remote-endpoint = <&lvds1_out_panel>;
+				};
+			};
+		};
+	};
+};
+
+&backlight1 {
+	status = "okay";
+};
+
+&backlight {
+	status = "okay";
+};
+
+&lvds {
+	status = "okay";
+	dual-channel;
+
+	ports {
+		port@1 {
+			reg = <1>;
+			lvds0_out_panel: endpoint {
+				remote-endpoint = <&panel_in_lvds0>;
+			};
+		};
+	};
+};
+
+&lvds1 {
+	status = "okay";
+
+	ports {
+		port@1 {
+			reg = <1>;
+			lvds1_out_panel: endpoint {
+				remote-endpoint = <&panel_in_lvds1>;
+			};
+		};
+	};
+};
+
+&lvds_in_vp1 {
+	status = "okay";
+};
+
+&lvds1_in_vp1 {
+	status = "disabled";
+};
+
+&lvds1_in_vp2 {
+	status = "okay";
+};
+
+/* enable hdmi */
+&hdmi_in_vp1 {
+	status = "okay";
+};
+
+/* enable video phy */
+&video_phy0 {
+	status = "okay";
+};
+
+&video_phy1 {
+	status = "okay";
+};
+
+/* disable other encoder output */
+&dsi0 {
+	status = "disabled";
+};
+
+&dsi0_in_vp0 {
+	status = "disabled";
+};
+
+&dsi0_in_vp1 {
+	status = "disabled";
+};
+
+&dsi1_in_vp1 {
+	status = "disabled";
+};
+
+&edp_in_vp1 {
+	status = "disabled";
+};
+
+&rgb_in_vp2 {
+	status = "disabled";
+};
+
+
+&vcc3v3_lcd0_n {
+	gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
+
+&vcc3v3_lcd1_n {
+	gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+	enable-active-high;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-amp.dtsi
@@ -24,18 +24,6 @@
 		};
 	};

-	rpmsg: rpmsg@7c00000 {
-		compatible = "rockchip,rk3568-rpmsg";
-		mbox-names = "rpmsg-rx", "rpmsg-tx";
-		mboxes = <&mailbox 0 &mailbox 3>;
-		rockchip,vdev-nums = <1>;
-		rockchip,link-id = <0x03>;
-		reg = <0x0 0x7c00000 0x0 0x20000>;
-		memory-region = <&rpmsg_dma_reserved>;
-
-		status = "okay";
-	};
-
 	reserved-memory {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -64,6 +52,18 @@
 			no-map;
 		};
 	};
+
+	rpmsg: rpmsg@7c00000 {
+		compatible = "rockchip,rpmsg";
+		mbox-names = "rpmsg-rx", "rpmsg-tx";
+		mboxes = <&mailbox 0 &mailbox 3>;
+		rockchip,vdev-nums = <1>;
+		rockchip,link-id = <0x03>;
+		reg = <0x0 0x7c00000 0x0 0x20000>;
+		memory-region = <&rpmsg_dma_reserved>;
+
+		status = "okay";
+	};
 };

 &mailbox {
--- a/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-amp.dtsi
@@ -3,12 +3,15 @@
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 */

+#include <dt-bindings/soc/rockchip-amp.h>
+
 / {
 	rockchip_amp: rockchip-amp {
-		compatible = "rockchip,mcu-amp";
+		compatible = "rockchip,amp";
 		clocks = <&cru HCLK_PMU_CM0_ROOT>, <&cru FCLK_PMU_CM0_CORE>,
 			<&cru CLK_PMU_CM0_RTC>, <&cru PCLK_PMUCM0_INTMUX>,
 			<&cru SCLK_UART5>, <&cru PCLK_UART5>,
+			<&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER4>, <&cru CLK_BUSTIMER5>,
 			<&cru PCLK_BUSTIMER1>, <&cru CLK_BUSTIMER10>, <&cru CLK_BUSTIMER11>;

 		pinctrl-names = "default";
@@ -22,10 +25,44 @@
 		#size-cells = <2>;
 		ranges;

+		/* remote amp core address */
+		amp_shmem_reserved: amp-shmem@7800000 {
+			reg = <0x0 0x7800000 0x0 0x400000>;
+			no-map;
+		};
+
+		rpmsg_reserved: rpmsg@7c00000 {
+			reg = <0x0 0x07c00000 0x0 0x400000>;
+			no-map;
+		};
+
+		rpmsg_dma_reserved: rpmsg-dma@8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x08000000 0x0 0x100000>;
+			no-map;
+		};
+
 		/* mcu address */
 		mcu_reserved: mcu@8200000 {
 			reg = <0x0 0x8200000 0x0 0x100000>;
 			no-map;
 		};
 	};
+
+	rpmsg: rpmsg@7c00000 {
+		compatible = "rockchip,rpmsg";
+		mbox-names = "rpmsg-rx", "rpmsg-tx";
+		mboxes = <&mailbox0 0 &mailbox0 3>;
+		rockchip,vdev-nums = <1>;
+		rockchip,link-id = <0x03>;
+		reg = <0x0 0x7c00000 0x0 0x20000>;
+		memory-region = <&rpmsg_dma_reserved>;
+
+		status = "okay";
+	};
+};
+
+&mailbox0 {
+	rockchip,txpoll-period-ms = <1>;
+	status = "okay";
 };
--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux-amp.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-linux-amp.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+
+#include "rk3588-evb1-lp4.dtsi"
+#include "rk3588-evb1-imx415.dtsi"
+#include "rk3588-linux.dtsi"
+#include "rk3588-amp.dtsi"
+
+/ {
+	model = "Rockchip RK3588 EVB1 LP4 V10 Board";
+	compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588";
+
+	cpus {
+		cpu-map {
+			cluster0 {
+				/delete-node/ core3;
+			};
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x02000000 0x0 0x06400000>,
+		      <0x0 0x09400000 0x0 0xe6c00000>,
+		      <0x1 0x00000000 0x1 0x00000000>,
+		      <0x2 0xf0000000 0x0 0x10000000>;
+	};
+};
+
+&arm_pmu {
+	interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
+			     <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
+};
+
+/delete-node/ &cpu_l3;
+
+&route_hdmi0 {
+	status = "okay";
+	connect = <&vp0_out_hdmi0>;
+	/delete-property/ force-output;
+	/delete-node/ force_timing;
+};
+
+&route_hdmi1 {
+	status = "okay";
+	connect = <&vp1_out_hdmi1>;
+	/delete-property/ force-output;
+	/delete-node/ force_timing;
+};
+
+&vcc_1v8_s0 {
+	/delete-property/ regulator-state-mem;
+	regulator-state-mem {
+		regulator-on-in-suspend;
+		regulator-suspend-microvolt = <1800000>;
+	};
+};
+
+&vcc_3v3_s0 {
+	/delete-property/ regulator-state-mem;
+	regulator-state-mem {
+		regulator-on-in-suspend;
+		regulator-suspend-microvolt = <3300000>;
+	};
+};
+
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dcphy0.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dcphy0.dtsi
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dcphy1.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dcphy1.dtsi
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+#include <dt-bindings/display/media-bus-format.h>
+
+/ {
+	max96712_dcphy1_osc: max96712-dcphy1-oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+		clock-output-names = "max96712-dcphy1-osc";
+	};
+};
+
+&mipi_dcphy1 {
+	status = "okay";
+};
+
+&csi2_dcphy1 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_dcphy1_in_max96712: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&max96712_dcphy1_out>;
+				data-lanes = <1 2>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidcphy1_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi1_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2m4_xfer>;
+
+	max96712_dcphy1: max96712@29 {
+		compatible = "maxim4c,max96712";
+		status = "okay";
+		reg = <0x29>;
+		clock-names = "xvclk";
+		clocks = <&max96712_dcphy1_osc 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&max96712_dcphy1_pwdn>, <&max96712_dcphy1_errb>, <&max96712_dcphy1_lock>;
+		power-domains = <&power RK3588_PD_VI>;
+		rockchip,grf = <&sys_grf>;
+		pwdn-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
+		pocen-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+		lock-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
+
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "max96712";
+		rockchip,camera-module-lens-name = "max96712";
+
+		port {
+			max96712_dcphy1_out: endpoint {
+				remote-endpoint = <&mipi_dcphy1_in_max96712>;
+				data-lanes = <1 2>;
+			};
+		};
+
+		/* support mode config start */
+		support-mode-config {
+			status = "okay";
+
+			bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
+			sensor-width = <1600>;
+			sensor-height = <1300>;
+			max-fps-numerator = <10000>;
+			max-fps-denominator = <300000>;
+			bpp = <16>;
+			link-freq-idx = <20>;
+			vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7
+		};
+		/* support mode config end */
+
+		/* serdes local device start */
+		serdes-local-device {
+			status = "okay";
+
+			/* GMSL LINK config start */
+			gmsl-links {
+				status = "okay";
+
+				link-vdd-ldo1-en = <1>;
+				link-vdd-ldo2-en = <1>;
+
+				// Link A: link-id = 0
+				gmsl-link-config-0 {
+					status = "okay";
+					link-id = <0>; // Link ID: 0/1/2/3
+
+					link-type = <1>;
+					link-rx-rate = <0>;
+					link-tx-rate = <0>;
+
+					port {
+						max96712_dcphy1_link0_in: endpoint {
+							remote-endpoint = <&max96712_dcphy1_remote0_out>;
+						};
+					};
+
+					link-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							14 D1 03 00 00 // VGAHiGain
+							14 45 00 00 00 // Disable SSC
+						];
+					};
+				};
+
+				// Link B: link-id = 1
+				gmsl-link-config-1 {
+					status = "okay";
+					link-id = <1>; // Link ID: 0/1/2/3
+
+					link-type = <1>;
+					link-rx-rate = <0>;
+					link-tx-rate = <0>;
+
+					port {
+						max96712_dcphy1_link1_in: endpoint {
+							remote-endpoint = <&max96712_dcphy1_remote1_out>;
+						};
+					};
+
+					link-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							15 D1 03 00 00 // VGAHiGain
+							15 45 00 00 00 // Disable SSC
+						];
+					};
+				};
+			};
+			/* GMSL LINK config end */
+
+			/* VIDEO PIPE config start */
+			video-pipes {
+				status = "okay";
+
+				// Video Pipe 0
+				video-pipe-config-0 {
+					status = "okay";
+					pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
+
+					pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3
+					link-idx = <0>; // Link A/B/C/D: 0/1/2/3
+
+					pipe-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							// Send YUV422, FS, and FE from Video Pipe 0 to Controller 0
+							09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
+							09 2D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0;
+							// For the following MSB 2 bits = VC, LSB 6 bits = DT
+							09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
+							09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
+							09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
+							09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
+							09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
+							09 12 01 00 00 // DST2 VC = 0, DT = Frame End
+							// pipe Cross
+							01 D9 59 00 00 // pipe 0: Inverts Cross VS
+						];
+					};
+				};
+
+				// Video Pipe 1
+				video-pipe-config-1 {
+					status = "okay";
+					pipe-id = <1>; // Video Pipe 1: pipe-id = 1
+
+					pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3
+					link-idx = <1>; // Link A/B/C/D: 0/1/2/3
+
+					pipe-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							// Send YUV422, FS, and FE from Video Pipe 1 to Controller 0
+							09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
+							09 6D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0;
+							// For the following MSB 2 bits = VC, LSB 6 bits = DT
+							09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
+							09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
+							09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
+							09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
+							09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
+							09 52 41 00 00 // DST2 VC = 1, DT = Frame End
+							// pipe Cross
+							01 F9 59 00 00 // pipe 1: Inverts Cross VS
+						];
+					};
+				};
+
+				// Software override for parallel mode
+				parallel-mode-config {
+					status = "okay";
+
+					parallel-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							// Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8)
+							04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode
+							04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
+							04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00
+							04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00
+							04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit
+							04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit
+							04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
+							04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
+							04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
+							04 15 c0 c0 00 // pipe 0/1 enable software overide
+							04 18 c0 c0 00 // pipe 2/3 enable software overide
+						];
+					};
+				};
+			};
+			/* VIDEO PIPE config end */
+
+			/* MIPI TXPHY config start */
+			mipi-txphys {
+				status = "okay";
+
+				phy-mode = <1>;
+				phy-force-clock-out = <1>;
+				phy-force-clk0-en = <0>;
+				phy-force-clk3-en = <0>;
+
+				// MIPI TXPHY A: phy-id = 0
+				mipi-txphy-config-0 {
+					status = "okay";
+					phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
+
+					phy-type = <0>;
+					auto-deskew = <0x00>;
+					data-lane-num = <2>;
+					data-lane-map = <0x4>;
+					vc-ext-en = <0>;
+				};
+			};
+			/* MIPI TXPHY config end */
+
+			/* local device extra init sequence */
+			extra-init-sequence {
+				status = "disabled";
+
+				seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+				reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+				reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+				// reg_addr reg_val val_mask delay
+				init-sequence = [
+					// common init sequence such as fsync / gpio and so on
+				];
+			};
+		};
+		/* serdes local device end */
+
+		/* serdes remote device start */
+		serdes-remote-device-0 {
+			compatible = "maxim4c,link0,max9295";
+			status = "okay";
+
+			remote-id = <0>; // Same as Link ID: 0/1/2/3
+
+			// Serializer i2c 7bit address remap
+			ser-i2c-addr-def = <0x40>;
+			ser-i2c-addr-map = <0x41>; // 0: disable remap
+
+			port {
+				max96712_dcphy1_remote0_out: endpoint {
+					remote-endpoint = <&max96712_dcphy1_link0_in>;
+				};
+			};
+
+			remote-init-sequence {
+				seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+				reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+				reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+				// reg_addr reg_val val_mask delay
+				init-sequence = [
+					00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps
+					00 11 03 00 00 // Coax Drive
+					02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1
+					03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL
+					00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL
+					00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected
+					02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0
+					02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup
+					00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable
+					00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled
+					00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE
+					01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high
+					01 01 50 00 00 // Video X, BPP = 0x10
+					00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel
+					00 02 13 00 00 // Video transmit enable for Port X
+				];
+			};
+		};
+
+		serdes-remote-device-1 {
+			compatible = "maxim4c,link1,max9295";
+			status = "okay";
+
+			remote-id = <1>; // Same as Link ID: 0/1/2/3
+
+			// Serializer i2c 7bit address remap
+			ser-i2c-addr-def = <0x40>;
+			ser-i2c-addr-map = <0x42>; // 0: disable remap
+
+			port {
+				max96712_dcphy1_remote1_out: endpoint {
+					remote-endpoint = <&max96712_dcphy1_link1_in>;
+				};
+			};
+
+			remote-init-sequence {
+				seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+				reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+				reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+				// reg_addr reg_val val_mask delay
+				init-sequence = [
+					00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps
+					00 11 03 00 00 // Coax Drive
+					02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1
+					03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL
+					00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL
+					00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected
+					02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0
+					02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup
+					00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable
+					00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled
+					00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE
+					01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high
+					01 01 50 00 00 // Video X, BPP = 0x10
+					00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel
+					00 02 13 00 00 // Video transmit enable for Port X
+				];
+			};
+		};
+		/* serdes remote device end */
+	};
+};
+
+&mipi1_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi1_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidcphy1_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi1_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi1_in>;
+			};
+		};
+	};
+};
+
+&rkcif_mipi_lvds1 {
+	status = "okay";
+	/* parameters for do cif reset detecting:
+	 * index0: monitor mode,
+		   0 for idle,
+		   1 for continue,
+		   2 for trigger,
+		   3 for hotplug (for nextchip)
+	 * index1: the frame id to start timer,
+		   min is 2
+	 * index2: frame num of monitoring cycle
+	 * index3: err time for keep monitoring
+		   after finding out err (ms)
+	 * index4: csi2 err reference val for resetting
+	 */
+	rockchip,cif-monitor = <3 2 1 1000 5>;
+
+	port {
+		cif_mipi1_in: endpoint {
+			remote-endpoint = <&mipi1_csi2_output>;
+		};
+	};
+};
+
+&rkcif {
+	status = "okay";
+	rockchip,android-usb-camerahal-enable;
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&pinctrl {
+	max96712-dcphy1 {
+		max96712_dcphy1_pwdn: max96712-dcphy1-pwdn {
+			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		max96712_dcphy1_errb: max96712-dcphy1-errb {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		max96712_dcphy1_lock: max96712-dcphy1-lock {
+			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy0.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy0.dtsi
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722-dphy0.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722-dphy0.dtsi
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722-dphy3.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-maxim-max96722-dphy3.dtsi
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+#include <dt-bindings/display/media-bus-format.h>
+
+/ {
+	max96722_dphy3_osc0: max96722-dphy3-oscillator@0 {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+		clock-output-names = "max96722-dphy3-osc0";
+	};
+};
+
+&csi2_dphy1_hw {
+	status = "okay";
+};
+
+&csi2_dphy3 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_dphy3_in_max96722: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&max96722_dphy3_out>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidphy3_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi4_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c6 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c6m3_xfer>;
+
+	max96722_dphy3: max96722@29 {
+		compatible = "maxim4c,max96722";
+		status = "okay";
+		reg = <0x29>;
+		clock-names = "xvclk";
+		clocks = <&max96722_dphy3_osc0 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&max96722_dphy3_pwdn>, <&max96722_dphy3_errb>, <&max96722_dphy3_lock>;
+		power-domains = <&power RK3588_PD_VI>;
+		rockchip,grf = <&sys_grf>;
+		pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+		lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
+
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "max96722";
+		rockchip,camera-module-lens-name = "max96722";
+
+		port {
+			max96722_dphy3_out: endpoint {
+				remote-endpoint = <&mipi_dphy3_in_max96722>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		/* support mode config start */
+		support-mode-config {
+			status = "okay";
+
+			bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
+			sensor-width = <1600>;
+			sensor-height = <1300>;
+			max-fps-numerator = <10000>;
+			max-fps-denominator = <300000>;
+			bpp = <16>;
+			link-freq-idx = <20>;
+			vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7
+		};
+		/* support mode config end */
+
+		/* serdes local device start */
+		serdes-local-device {
+			status = "okay";
+
+			/* GMSL LINK config start */
+			gmsl-links {
+				status = "okay";
+
+				link-vdd-ldo1-en = <1>;
+				link-vdd-ldo2-en = <1>;
+
+				// Link A: link-id = 0
+				gmsl-link-config-0 {
+					status = "okay";
+					link-id = <0>; // Link ID: 0/1/2/3
+
+					link-type = <1>;
+					link-rx-rate = <0>;
+					link-tx-rate = <0>;
+
+					port {
+						max96722_dphy3_link0_in: endpoint {
+							remote-endpoint = <&max96722_dphy3_remote0_out>;
+						};
+					};
+
+					link-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							14 D1 03 00 00 // VGAHiGain
+							14 45 00 00 00 // Disable SSC
+						];
+					};
+				};
+
+				// Link B: link-id = 1
+				gmsl-link-config-1 {
+					status = "okay";
+					link-id = <1>; // Link ID: 0/1/2/3
+
+					link-type = <1>;
+					link-rx-rate = <0>;
+					link-tx-rate = <0>;
+
+					port {
+						max96722_dphy3_link1_in: endpoint {
+							remote-endpoint = <&max96722_dphy3_remote1_out>;
+						};
+					};
+
+					link-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							15 D1 03 00 00 // VGAHiGain
+							15 45 00 00 00 // Disable SSC
+						];
+					};
+				};
+			};
+			/* GMSL LINK config end */
+
+			/* VIDEO PIPE config start */
+			video-pipes {
+				status = "okay";
+
+				// Video Pipe 0
+				video-pipe-config-0 {
+					status = "okay";
+					pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
+
+					pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3
+					link-idx = <0>; // Link A/B/C/D: 0/1/2/3
+
+					pipe-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							// Send YUV422, FS, and FE from Video Pipe 0 to Controller 1
+							09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
+							09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
+							// For the following MSB 2 bits = VC, LSB 6 bits = DT
+							09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
+							09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
+							09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
+							09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
+							09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
+							09 12 01 00 00 // DST2 VC = 0, DT = Frame End
+							// pipe Cross
+							01 D9 59 00 00 // pipe 0: Inverts Cross VS
+						];
+					};
+				};
+
+				// Video Pipe 1
+				video-pipe-config-1 {
+					status = "okay";
+					pipe-id = <1>; // Video Pipe 1: pipe-id = 1
+
+					pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3
+					link-idx = <1>; // Link A/B/C/D: 0/1/2/3
+
+					pipe-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							// Send YUV422, FS, and FE from Video Pipe 1 to Controller 1
+							09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
+							09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1;
+							// For the following MSB 2 bits = VC, LSB 6 bits = DT
+							09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
+							09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
+							09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
+							09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
+							09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
+							09 52 41 00 00 // DST2 VC = 1, DT = Frame End
+							// pipe Cross
+							01 F9 59 00 00 // pipe 1: Inverts Cross VS
+						];
+					};
+				};
+
+				// Software override for parallel mode
+				parallel-mode-config {
+					status = "okay";
+
+					parallel-init-sequence {
+						seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+						reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+						reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+						// reg_addr reg_val val_mask delay
+						init-sequence = [
+							// Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8)
+							04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode
+							04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
+							04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00
+							04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00
+							04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit
+							04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit
+							04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
+							04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
+							04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
+							04 15 c0 c0 00 // pipe 0/1 enable software overide
+							04 18 c0 c0 00 // pipe 2/3 enable software overide
+						];
+					};
+				};
+			};
+			/* VIDEO PIPE config end */
+
+			/* MIPI TXPHY config start */
+			mipi-txphys {
+				status = "okay";
+
+				phy-mode = <0>;
+				phy-force-clock-out = <1>;
+				phy-force-clk0-en = <1>;
+				phy-force-clk3-en = <0>;
+
+				// MIPI TXPHY A: phy-id = 0
+				mipi-txphy-config-0 {
+					status = "okay";
+					phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
+
+					phy-type = <0>;
+					auto-deskew = <0x80>;
+					data-lane-num = <4>;
+					data-lane-map = <0x4>;
+					vc-ext-en = <0>;
+				};
+
+				// MIPI TXPHY B: phy-id = 1
+				mipi-txphy-config-1 {
+					status = "okay";
+					phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3
+
+					phy-type = <0>;
+					auto-deskew = <0x80>;
+					data-lane-num = <4>;
+					data-lane-map = <0xe>;
+					vc-ext-en = <0>;
+				};
+			};
+			/* MIPI TXPHY config end */
+
+			/* local device extra init sequence */
+			extra-init-sequence {
+				status = "disabled";
+
+				seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+				reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+				reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+				// reg_addr reg_val val_mask delay
+				init-sequence = [
+					// common init sequence such as fsync / gpio and so on
+				];
+			};
+		};
+		/* serdes local device end */
+
+		/* serdes remote device start */
+		serdes-remote-device-0 {
+			compatible = "maxim4c,link0,max9295";
+			status = "okay";
+
+			remote-id = <0>; // Same as Link ID: 0/1/2/3
+
+			// Serializer i2c 7bit address remap
+			ser-i2c-addr-def = <0x40>;
+			ser-i2c-addr-map = <0x41>; // 0: disable remap
+
+			port {
+				max96722_dphy3_remote0_out: endpoint {
+					remote-endpoint = <&max96722_dphy3_link0_in>;
+				};
+			};
+
+			remote-init-sequence {
+				seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+				reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+				reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+				// reg_addr reg_val val_mask delay
+				init-sequence = [
+					00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps
+					00 11 03 00 00 // Coax Drive
+					02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1
+					03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL
+					00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL
+					00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected
+					02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0
+					02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup
+					00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable
+					00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled
+					00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE
+					01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high
+					01 01 50 00 00 // Video X, BPP = 0x10
+					00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel
+					00 02 13 00 00 // Video transmit enable for Port X
+				];
+			};
+		};
+
+		serdes-remote-device-1 {
+			compatible = "maxim4c,link1,max9295";
+			status = "okay";
+
+			remote-id = <1>; // Same as Link ID: 0/1/2/3
+
+			// Serializer i2c 7bit address remap
+			ser-i2c-addr-def = <0x40>;
+			ser-i2c-addr-map = <0x42>; // 0: disable remap
+
+			port {
+				max96722_dphy3_remote1_out: endpoint {
+					remote-endpoint = <&max96722_dphy3_link1_in>;
+				};
+			};
+
+			remote-init-sequence {
+				seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
+				reg-addr-len = <2>; // 1: 8bits, 2: 16bits
+				reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
+
+				// reg_addr reg_val val_mask delay
+				init-sequence = [
+					00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps
+					00 11 03 00 00 // Coax Drive
+					02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1
+					03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL
+					00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL
+					00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected
+					02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0
+					02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup
+					00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable
+					00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled
+					00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE
+					01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high
+					01 01 50 00 00 // Video X, BPP = 0x10
+					00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel
+					00 02 13 00 00 // Video transmit enable for Port X
+				];
+			};
+		};
+		/* serdes remote device end */
+	};
+};
+
+&mipi4_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi4_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidphy3_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi4_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi4_in>;
+			};
+		};
+	};
+};
+
+&rkcif_mipi_lvds4 {
+	status = "okay";
+	/* parameters for do cif reset detecting:
+	 * index0: monitor mode,
+		   0 for idle,
+		   1 for continue,
+		   2 for trigger,
+		   3 for hotplug (for nextchip)
+	 * index1: the frame id to start timer,
+		   min is 2
+	 * index2: frame num of monitoring cycle
+	 * index3: err time for keep monitoring
+		   after finding out err (ms)
+	 * index4: csi2 err reference val for resetting
+	 */
+	rockchip,cif-monitor = <3 2 1 1000 5>;
+
+	port {
+		cif_mipi4_in: endpoint {
+			remote-endpoint = <&mipi4_csi2_output>;
+		};
+	};
+};
+
+&rkcif {
+	status = "okay";
+	rockchip,android-usb-camerahal-enable;
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&pinctrl {
+	max96722-dphy3 {
+		max96722_dphy3_pwdn: max96722-dphy3-pwdn {
+			rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		max96722_dphy3_errb: max96722-dphy3-errb {
+			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+
+		max96722_dphy3_lock: max96722-dphy3-lock {
+			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v21.dts
@@ -7,8 +7,8 @@
 /dts-v1/;

 #include "rk3588-vehicle-evb-v21.dtsi"
-#include "rk3588-vehicle-evb-maxim-max96712.dtsi"
-#include "rk3588-vehicle-serdes-display-v21.dtsi"
+#include "rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi"
+#include "rk3588-vehicle-serdes-mfd-display-rohm.dtsi"
 #include "rk3588-android.dtsi"

 / {
@@ -55,6 +55,32 @@
 	};
 };

+&i2c2 {
+	himax@48 {
+		himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
+
+&i2c4 {
+	himax@48 {
+		himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
+
+&i2c5 {
+	ilitek@41 {
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
+		reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&i2c6 {
+	himax@48 {
+		himax,irq-gpio = <&gpio1 RK_PB7 IRQ_TYPE_EDGE_FALLING>;	//use rst as int
+	};
+};
+
 &i2s2_2ch {
 	pinctrl-0 = <&i2s2m1_lrck
 		     &i2s2m1_sclk
@@ -63,6 +89,78 @@
 	status = "okay";
 };

+
+&pinctrl {
+
+	bl {
+		bl0_enable_pin: bl0-enable-pin {
+			rockchip,pins =
+				<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
+				<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
+				<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+
+		};
+
+		bl1_enable_pin: bl1-enable-pin {
+			rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl2_enable_pin: bl2-enable-pin {
+			rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl3_enable_pin: bl3-enable-pin {
+			rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl4_enable_pin: bl4-enable-pin {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		bl5_enable_pin: bl5-enable-pin {
+			rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	serdes {
+		//dsi0
+		ser0_rst_pin: ser0-rst-pin {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		//dsi1
+		ser1_rst_pin: ser1-rst-pin {
+			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	touch {
+		//dsi0-i2c2
+		touch_gpio_dsi0: touch-gpio-dsi0 {
+			rockchip,pins =
+				<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;  //rst
+		};
+		//dsi1-i2c6
+		touch_gpio_dsi1: touch-gpio-dsi1 {
+			rockchip,pins =
+				<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,  //rst
+				<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;  //int
+		};
+		//dp0-i2c4
+		touch_gpio_dp0: touch-gpio-dp0 {
+			rockchip,pins =
+				<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>,	//rst
+				<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;	//int
+		};
+		//edp0-i2c5
+		touch_gpio_edp0: touch-gpio-edp0 {
+			rockchip,pins =
+				<0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>,  //rst
+				<0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;  //int
+		};
+	};
+};
+
 &rockchip_suspend {
 	rockchip,sleep-mode-config = <
 		(0
--- a/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/ {
+	nca9539_vdd: nca9539-vdd3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "nca9539_vdd";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		startup-delay-us = <20>; // NCA9539 POR
+		vin-supply = <&vcc_3v3_s0>;
+	};
+
+};
+
+&i2c5 {
+	clock-frequency = <400000>;
+	status = "okay";
+
+	nca9539_gpio: gpio@74 {
+		status = "okay";
+		compatible = "novo,nca9539-gpio";
+		reg = <0x74>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <16>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		vdd-supply = <&nca9539_vdd>;
+	};
+};
--- a/Show More
+++ b/Show More