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Merge commit '52f971ee6e023d89d24f9e3cd145d86d707e459c'
* commit '52f971ee6e023d89d24f9e3cd145d86d707e459c': (84565 commits) arm64: dts: rockchip: rk3562: Enable viLKsvPwrActive for soc bus mtd: spi-nor: esmt: Support New devices mtd: spi-nor: fmsh: Support New devices mtd: spi-nor: gigadevice: Support New devices mtd: spinand: gsto: Add code mtd: spinand: hyf: Support new devices mmc: convert thunder boot dependency ARM: dts: rockchip: rv1106: add node for system sleep ARM: rockchip: support rv1106 suspend ARM: rockchip: add some pm-related functions video: rockchip: mpp: fix rk3528 avsd not probe issue arm64: dts: rockchip: rk3588-vehicle-maxim-serdes: Add BOE AV156FHT L83 support arm64: rockchip_defconfig: Enable CONFIG_DRM_PANEL_MAXIM_MAX96752F drm/panel: Add panel driver for Maxim MAX96752F based LCDs media: i2c: techpoint: add support 4 channel 2 lane mode drm/rockchip: dsi2: fix NULL in component_ops .unbind helper media: rockchip: vicap: fixes cma can not alloc when capture raw media: rockchip: vicap: fixed vc err for multi channel media: rockchip: hdmirx: fix timing info for interlaced resolution media: rockchip: hdmirx: fix code error for cec register failed ... Change-Id: Ia7ac365455d87a295e62bbf481d80694a9712f30 Conflicts: .gitignore Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt Documentation/devicetree/bindings/connector/usb-connector.yaml Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt Documentation/devicetree/bindings/hwmon/pwm-fan.txt Documentation/devicetree/bindings/iio/light/vl6180.txt Documentation/devicetree/bindings/iommu/rockchip,iommu.txt Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml Documentation/devicetree/bindings/net/rockchip-dwmac.yaml Documentation/devicetree/bindings/net/snps,dwmac.yaml Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml Documentation/devicetree/bindings/power/rockchip-io-domain.txt Documentation/devicetree/bindings/regulator/fan53555.txt Documentation/devicetree/bindings/soc/rockchip/power_domain.txt Documentation/devicetree/bindings/sound/rockchip,pdm.yaml Documentation/devicetree/bindings/sound/rockchip-spdif.yaml Documentation/devicetree/bindings/spi/spi-rockchip.yaml Documentation/devicetree/bindings/thermal/rockchip-thermal.txt Documentation/devicetree/bindings/usb/usb-xhci.txt Documentation/filesystems/erofs.rst arch/arm/Kconfig arch/arm/Makefile arch/arm/boot/compressed/head.S arch/arm/boot/dts/rk3036.dtsi arch/arm/boot/dts/rk3066a-rayeager.dts arch/arm/boot/dts/rk3066a.dtsi arch/arm/boot/dts/rk322x.dtsi arch/arm/boot/dts/rk3288.dtsi arch/arm/boot/dts/rk3xxx.dtsi arch/arm64/boot/dts/rockchip/Makefile arch/arm64/boot/dts/rockchip/px30.dtsi arch/arm64/boot/dts/rockchip/rk3308.dtsi arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi arch/arm64/boot/dts/rockchip/rk3399.dtsi arch/arm64/boot/dts/rockchip/rk3566.dtsi arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi arch/arm64/boot/dts/rockchip/rk3568.dtsi arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi arch/arm64/kernel/process.c arch/arm64/mm/Makefile arch/arm64/mm/fault.c arch/arm64/mm/init.c drivers/Kconfig drivers/Makefile drivers/android/Kconfig drivers/ata/ahci_platform.c drivers/char/hw_random/Kconfig drivers/char/hw_random/Makefile drivers/clk/clk.c drivers/clk/rockchip/Kconfig drivers/clk/rockchip/Makefile drivers/clk/rockchip/clk-cpu.c drivers/clk/rockchip/clk-rk3036.c drivers/clk/rockchip/clk-rk3188.c drivers/clk/rockchip/clk-rk3308.c drivers/clk/rockchip/clk-rk3399.c drivers/clk/rockchip/clk-rk3568.c drivers/clk/rockchip/clk-rv1126.c drivers/clk/rockchip/clk.c drivers/clk/rockchip/clk.h drivers/cpufreq/cpufreq-dt.c drivers/crypto/Kconfig drivers/devfreq/Makefile drivers/devfreq/devfreq.c drivers/dma-buf/dma-buf.c drivers/dma-buf/heaps/Makefile drivers/dma/pl330.c drivers/firmware/Kconfig drivers/gpio/Kconfig drivers/gpio/Makefile drivers/gpio/gpio-rockchip.c drivers/gpu/Makefile drivers/gpu/drm/Kconfig drivers/gpu/drm/Makefile drivers/gpu/drm/bridge/Kconfig drivers/gpu/drm/bridge/Makefile drivers/gpu/drm/bridge/analogix/analogix_dp_core.c drivers/gpu/drm/bridge/analogix/analogix_dp_core.h drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c drivers/gpu/drm/bridge/display-connector.c drivers/gpu/drm/bridge/sii902x.c drivers/gpu/drm/bridge/synopsys/Makefile drivers/gpu/drm/bridge/synopsys/dw-hdmi.c drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c drivers/gpu/drm/drm_atomic_helper.c drivers/gpu/drm/drm_crtc_internal.h drivers/gpu/drm/drm_edid.c drivers/gpu/drm/panel/panel-simple.c drivers/gpu/drm/rockchip/Kconfig drivers/gpu/drm/rockchip/Makefile drivers/gpu/drm/rockchip/analogix_dp-rockchip.c drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c drivers/gpu/drm/rockchip/inno_hdmi.c drivers/gpu/drm/rockchip/rockchip_drm_drv.c drivers/gpu/drm/rockchip/rockchip_drm_drv.h drivers/gpu/drm/rockchip/rockchip_drm_fbdev.c drivers/gpu/drm/rockchip/rockchip_drm_gem.c drivers/gpu/drm/rockchip/rockchip_drm_vop.c drivers/gpu/drm/rockchip/rockchip_drm_vop.h drivers/gpu/drm/rockchip/rockchip_drm_vop2.c drivers/gpu/drm/rockchip/rockchip_lvds.c drivers/gpu/drm/rockchip/rockchip_rgb.c drivers/gpu/drm/rockchip/rockchip_vop2_reg.c drivers/gpu/drm/rockchip/rockchip_vop_reg.c drivers/gpu/drm/rockchip/rockchip_vop_reg.h drivers/hwmon/pwm-fan.c drivers/hwspinlock/Kconfig drivers/hwspinlock/Makefile drivers/i2c/busses/i2c-rk3x.c drivers/i2c/i2c-core-base.c drivers/iio/adc/Kconfig drivers/iio/adc/rockchip_saradc.c drivers/iio/industrialio-event.c drivers/input/touchscreen/Makefile drivers/iommu/iommu.c drivers/iommu/rockchip-iommu.c drivers/irqchip/irq-gic-v3-its.c drivers/leds/Makefile drivers/mailbox/Kconfig drivers/media/common/videobuf2/Makefile drivers/media/i2c/Kconfig drivers/media/i2c/Makefile drivers/media/i2c/dw9714.c drivers/media/i2c/hi556.c drivers/media/i2c/imx214.c drivers/media/i2c/imx258.c drivers/media/i2c/imx334.c drivers/media/i2c/imx335.c drivers/media/i2c/ov5648.c drivers/media/i2c/ov5670.c drivers/media/i2c/ov5695.c drivers/media/i2c/ov7251.c drivers/media/platform/Kconfig drivers/media/platform/Makefile drivers/media/platform/rockchip/Kconfig drivers/media/spi/Kconfig drivers/media/spi/Makefile drivers/media/usb/uvc/uvc_driver.c drivers/media/usb/uvc/uvcvideo.h drivers/media/v4l2-core/v4l2-async.c drivers/media/v4l2-core/v4l2-ioctl.c drivers/mfd/rk808.c drivers/mmc/core/block.c drivers/mmc/core/host.c drivers/mmc/core/mmc.c drivers/mmc/core/mmc_ops.c drivers/mmc/host/Makefile drivers/mmc/host/dw_mmc-rockchip.c drivers/mmc/host/dw_mmc.c drivers/mmc/host/dw_mmc.h drivers/mmc/host/sdhci-of-dwcmshc.c drivers/mtd/nand/Makefile drivers/mtd/nand/raw/Kconfig drivers/mtd/nand/raw/Makefile drivers/mtd/nand/raw/rockchip-nand-controller.c drivers/mtd/nand/spi/Makefile drivers/mtd/nand/spi/core.c drivers/mtd/nand/spi/gigadevice.c drivers/mtd/nand/spi/macronix.c drivers/mtd/nand/spi/xtx.c drivers/mtd/spi-nor/Kconfig drivers/mtd/spi-nor/Makefile drivers/mtd/spi-nor/core.c drivers/mtd/spi-nor/core.h drivers/mtd/spi-nor/eon.c drivers/mtd/spi-nor/esmt.c drivers/mtd/spi-nor/gigadevice.c drivers/mtd/spi-nor/macronix.c drivers/mtd/spi-nor/winbond.c drivers/mtd/spi-nor/xmc.c drivers/net/ethernet/stmicro/stmmac/Makefile drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c drivers/net/ethernet/stmicro/stmmac/stmmac.h drivers/net/ethernet/stmicro/stmmac/stmmac_main.c drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c drivers/net/phy/Kconfig drivers/net/phy/motorcomm.c drivers/net/phy/phy_device.c drivers/nvmem/Kconfig drivers/nvmem/Makefile drivers/pci/controller/dwc/Makefile drivers/pci/controller/dwc/pcie-designware-host.c drivers/pci/controller/dwc/pcie-dw-rockchip.c drivers/pci/controller/pcie-rockchip-host.c drivers/pci/controller/pcie-rockchip.h drivers/pci/pci-sysfs.c drivers/pci/pcie/Makefile drivers/phy/rockchip/Kconfig drivers/phy/rockchip/Makefile drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c drivers/phy/rockchip/phy-rockchip-inno-usb2.c drivers/phy/rockchip/phy-rockchip-naneng-combphy.c drivers/phy/rockchip/phy-rockchip-snps-pcie3.c drivers/phy/rockchip/phy-rockchip-typec.c drivers/pinctrl/Kconfig drivers/pinctrl/Makefile drivers/pinctrl/pinctrl-rk805.c drivers/pinctrl/pinctrl-rockchip.c drivers/pinctrl/pinctrl-rockchip.h drivers/power/supply/Kconfig drivers/power/supply/Makefile drivers/power/supply/bq25890_charger.c drivers/power/supply/rk817_charger.c drivers/pwm/core.c drivers/pwm/pwm-rockchip.c drivers/regulator/fan53555.c drivers/regulator/rk808-regulator.c drivers/rtc/rtc-hym8563.c drivers/soc/rockchip/Kconfig drivers/soc/rockchip/Makefile drivers/soc/rockchip/grf.c drivers/soc/rockchip/io-domain.c drivers/soc/rockchip/pm_domains.c drivers/spi/Kconfig drivers/spi/spi-rockchip-sfc.c drivers/spi/spi-rockchip.c drivers/spi/spidev.c drivers/staging/android/ion/heaps/ion_system_heap.c drivers/thermal/rockchip_thermal.c drivers/tty/serial/8250/8250_dma.c drivers/tty/serial/8250/8250_dw.c drivers/tty/serial/8250/8250_dwlib.c drivers/tty/serial/8250/8250_port.c drivers/usb/dwc2/platform.c drivers/usb/dwc3/core.c drivers/usb/dwc3/core.h drivers/usb/dwc3/ep0.c drivers/usb/dwc3/gadget.c drivers/usb/gadget/configfs.c drivers/usb/gadget/function/f_fs.c drivers/usb/gadget/function/f_uvc.c drivers/usb/gadget/function/uvc.h drivers/usb/gadget/function/uvc_configfs.c drivers/usb/gadget/function/uvc_queue.c drivers/usb/gadget/function/uvc_v4l2.c drivers/usb/gadget/function/uvc_video.c drivers/usb/gadget/udc/core.c drivers/usb/host/ehci-hcd.c drivers/usb/host/ehci-platform.c drivers/usb/storage/unusual_uas.h drivers/usb/typec/altmodes/Kconfig drivers/usb/typec/altmodes/displayport.c drivers/usb/typec/class.c drivers/usb/typec/tcpm/tcpm.c fs/Kconfig fs/cifs/inode.c fs/dax.c fs/erofs/data.c fs/erofs/inode.c fs/erofs/internal.h fs/erofs/super.c fs/f2fs/super.c fs/fuse/dev.c include/drm/bridge/dw_hdmi.h include/drm/drm_connector.h include/drm/drm_edid.h include/dt-bindings/clock/rk3568-cru.h include/dt-bindings/power/rk3568-power.h include/dt-bindings/power/rk3588-power.h include/linux/clk-provider.h include/linux/cma.h include/linux/dma-buf.h include/linux/dma-heap.h include/linux/mfd/rk808.h include/linux/mtd/spi-nor.h include/linux/mtd/spinand.h include/linux/phy/pcie.h include/linux/pwm.h include/linux/sched/sysctl.h include/linux/slub_def.h include/linux/stmmac.h include/linux/usb/typec.h include/media/v4l2-async.h include/soc/rockchip/pm_domains.h include/uapi/drm/drm_fourcc.h include/uapi/linux/iio/types.h include/uapi/linux/media-bus-format.h init/Kconfig init/main.c kernel/printk/printk.c kernel/rcu/Kconfig.debug kernel/rcu/tree_stall.h kernel/sched/core.c kernel/sched/cpufreq_schedutil.c kernel/sched/fair.c kernel/sched/pelt.c kernel/sched/rt.c kernel/sched/sched.h kernel/softirq.c kernel/sysctl.c mm/Makefile mm/cma.c mm/page_alloc.c mm/slub.c scripts/.gitignore scripts/headers_install.sh sound/soc/codecs/Kconfig sound/soc/codecs/Makefile sound/soc/codecs/es8326.c sound/soc/codecs/es8326.h sound/soc/codecs/hdmi-codec.c sound/soc/codecs/rk817_codec.c sound/soc/rockchip/Kconfig sound/soc/rockchip/Makefile sound/soc/rockchip/rockchip_i2s.c sound/soc/rockchip/rockchip_i2s_tdm.c sound/soc/rockchip/rockchip_i2s_tdm.h sound/soc/rockchip/rockchip_pdm.c sound/soc/rockchip/rockchip_spdif.c sound/soc/soc-generic-dmaengine-pcm.c tools/iio/iio_event_monitor.c
This commit is contained in:
Tao Huang
3
.gitignore
vendored
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vendored
@@ -26,6 +26,7 @@
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*.gz
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*.i
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*.ko
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*.lds
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*.lex.c
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*.ll
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*.lst
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@@ -56,6 +57,8 @@ modules.order
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#
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# Top-level generic files
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||||
#
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/*.img
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/out/
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/linux
|
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/modules-only.symvers
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/vmlinux
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0
.scmversion
Normal file
0
.scmversion
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319
Documentation/ABI/testing/sysfs-device-mali
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319
Documentation/ABI/testing/sysfs-device-mali
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@@ -0,0 +1,319 @@
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/*
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||||
*
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* (C) COPYRIGHT 2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program is free software and is provided to you under the terms of the
|
||||
* GNU General Public License version 2 as published by the Free Software
|
||||
* Foundation) and any use by you of this program is subject to the terms
|
||||
* of such GNU licence.
|
||||
*
|
||||
* A copy of the licence is included with the program) and can also be obtained
|
||||
* from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
|
||||
* Boston) MA 02110-1301) USA.
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*
|
||||
*/
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|
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What: /sys/class/misc/mali%u/device/core_mask
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||||
Description:
|
||||
This attribute is used to restrict the number of shader cores
|
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available in this instance, is useful for debugging purposes.
|
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Reading this attribute provides us mask of all cores available.
|
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Writing to it will set the current core mask. Doesn't
|
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allow disabling all the cores present in this instance.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/debug_command
|
||||
Description:
|
||||
This attribute is used to issue debug commands that supported
|
||||
by the driver. On reading it provides the list of debug commands
|
||||
that are supported, and writing back one of those commands will
|
||||
enable that debug option.
|
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|
||||
What: /sys/class/misc/mali%u/device/dvfs_period
|
||||
Description:
|
||||
This is used to set the DVFS sampling period to be used by the
|
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driver, On reading it provides the current DVFS sampling period,
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on writing a value we set the DVFS sampling period.
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|
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What: /sys/class/misc/mali%u/device/dummy_job_wa_info
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU that requires a GPU workaround
|
||||
to execute the dummy fragment job on all shader cores to
|
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workaround a hang issue.
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|
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Its a readonly attribute and on reading gives details on the
|
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options used with the dummy workaround.
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|
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What: /sys/class/misc/mali%u/device/fw_timeout
|
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Description:
|
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This attribute is available only with mali platform
|
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device-driver that supports a CSF GPU. This attribute is
|
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used to set the duration value in milliseconds for the
|
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waiting timeout used for a GPU status change request being
|
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acknowledged by the FW.
|
||||
|
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What: /sys/class/misc/mali%u/device/gpuinfo
|
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Description:
|
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This attribute provides description of the present Mali GPU.
|
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Its a read only attribute provides details like GPU family, the
|
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number of cores, the hardware version and the raw product id.
|
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|
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What: /sys/class/misc/mali%u/device/idle_hysteresis_time
|
||||
Description:
|
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This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. This attribute is
|
||||
used to set the duration value in milliseconds for the
|
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configuring hysteresis field for determining GPU idle detection.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/js_ctx_scheduling_mode
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU. This attribute is used to set
|
||||
context scheduling priority for a job slot.
|
||||
|
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On Reading it provides the currently set job slot context
|
||||
priority.
|
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|
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Writing 0 to this attribute sets it to the mode were
|
||||
higher priority atoms will be scheduled first, regardless of
|
||||
the context they belong to. Newly-runnable higher priority atoms
|
||||
can preempt lower priority atoms currently running on the GPU,
|
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even if they belong to a different context.
|
||||
|
||||
Writing 1 to this attribute set it to the mode were the
|
||||
highest-priority atom will be chosen from each context in turn
|
||||
using a round-robin algorithm, so priority only has an effect
|
||||
within the context an atom belongs to. Newly-runnable higher
|
||||
priority atoms can preempt the lower priority atoms currently
|
||||
running on the GPU, but only if they belong to the same context.
|
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|
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What: /sys/class/misc/mali%u/device/js_scheduling_period
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU. Used to set the job scheduler
|
||||
tick period in nano-seconds. The Job Scheduler determines the
|
||||
jobs that are run on the GPU, and for how long, Job Scheduler
|
||||
makes decisions at a regular time interval determined by value
|
||||
in js_scheduling_period.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/js_softstop_always
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU. Soft-stops are disabled when
|
||||
only a single context is present, this attribute is used to
|
||||
enable soft-stop when only a single context is present can be
|
||||
used for debug and unit-testing purposes.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/js_timeouts
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU. It used to set the soft stop
|
||||
and hard stop times for the job scheduler.
|
||||
|
||||
Writing value 0 causes no change, or -1 to restore the
|
||||
default timeout.
|
||||
|
||||
The format used to set js_timeouts is
|
||||
"<soft_stop_ms> <soft_stop_ms_cl> <hard_stop_ms_ss>
|
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<hard_stop_ms_cl> <hard_stop_ms_dumping> <reset_ms_ss>
|
||||
<reset_ms_cl> <reset_ms_dumping>"
|
||||
|
||||
|
||||
What: /sys/class/misc/mali%u/device/lp_mem_pool_max_size
|
||||
Description:
|
||||
This attribute is used to set the maximum number of large pages
|
||||
memory pools that the driver can contain. Large pages are of
|
||||
size 2MB. On read it displays all the max size of all memory
|
||||
pools and can be used to modify each individual pools as well.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/lp_mem_pool_size
|
||||
Description:
|
||||
This attribute is used to set the number of large memory pages
|
||||
which should be populated, changing this value may cause
|
||||
existing pages to be removed from the pool, or new pages to be
|
||||
created and then added to the pool. On read it will provide
|
||||
pool size for all available pools and we can modify individual
|
||||
pool.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/mem_pool_max_size
|
||||
Description:
|
||||
This attribute is used to set the maximum number of small pages
|
||||
for memory pools that the driver can contain. Here small pages
|
||||
are of size 4KB. On read it will display the max size for all
|
||||
available pools and allows us to set max size of
|
||||
individual pools.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/mem_pool_size
|
||||
Description:
|
||||
This attribute is used to set the number of small memory pages
|
||||
which should be populated, changing this value may cause
|
||||
existing pages to be removed from the pool, or new pages to
|
||||
be created and then added to the pool. On read it will provide
|
||||
pool size for all available pools and we can modify individual
|
||||
pool.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/device/mempool/ctx_default_max_size
|
||||
Description:
|
||||
This attribute is used to set maximum memory pool size for
|
||||
all the memory pool so that the maximum amount of free memory
|
||||
that each pool can hold is identical.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/device/mempool/lp_max_size
|
||||
Description:
|
||||
This attribute is used to set the maximum number of large pages
|
||||
for all memory pools that the driver can contain.
|
||||
Large pages are of size 2MB.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/device/mempool/max_size
|
||||
Description:
|
||||
This attribute is used to set the maximum number of small pages
|
||||
for all the memory pools that the driver can contain.
|
||||
Here small pages are of size 4KB.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/pm_poweroff
|
||||
Description:
|
||||
This attribute contains the current values, represented as the
|
||||
following space-separated integers:
|
||||
• PM_GPU_POWEROFF_TICK_NS.
|
||||
• PM_POWEROFF_TICK_SHADER.
|
||||
• PM_POWEROFF_TICK_GPU.
|
||||
|
||||
Example:
|
||||
echo 100000 4 4 > /sys/class/misc/mali0/device/pm_poweroff
|
||||
|
||||
Sets the following new values: 100,000ns tick, four ticks
|
||||
for shader power down, and four ticks for GPU power down.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/power_policy
|
||||
Description:
|
||||
This attribute is used to find the current power policy been
|
||||
used, reading will list the power policies available and
|
||||
enclosed in square bracket is the current one been selected.
|
||||
|
||||
Example:
|
||||
cat /sys/class/misc/mali0/device/power_policy
|
||||
[demand] coarse_demand always_on
|
||||
|
||||
To switch to a different policy at runtime write the valid entry
|
||||
name back to the attribute.
|
||||
|
||||
Example:
|
||||
echo "coarse_demand" > /sys/class/misc/mali0/device/power_policy
|
||||
|
||||
What: /sys/class/misc/mali%u/device/progress_timeout
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. This attribute
|
||||
is used to set the progress timeout value and read the current
|
||||
progress timeout value.
|
||||
|
||||
Progress timeout value is the maximum number of GPU cycles
|
||||
without forward progress to allow to elapse before terminating a
|
||||
GPU command queue group.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/mcu_shader_pwroff_timeout
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. The duration value unit
|
||||
is in micro-seconds and is used for configuring MCU shader Core power-off
|
||||
timer. The configured MCU shader Core power-off timer will only have
|
||||
effect when the host driver has delegated the shader cores
|
||||
power management to MCU. The supplied value will be
|
||||
recorded internally without any change. But the actual field
|
||||
value will be subject to core power-off timer source frequency
|
||||
scaling and maximum value limiting. The default source will be
|
||||
SYSTEM_TIMESTAMP counter. But in case the platform is not able
|
||||
to supply it, the GPU CYCLE_COUNTER source will be used as an
|
||||
alternative.
|
||||
|
||||
If we set the value to zero then MCU-controlled shader/tiler
|
||||
power management will be disabled.
|
||||
|
||||
|
||||
What: /sys/class/misc/mali%u/device/csg_scheduling_period
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. The duration value unit
|
||||
is in milliseconds and is used for configuring csf scheduling
|
||||
tick duration.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/reset_timeout
|
||||
Description:
|
||||
This attribute is used to set the number of milliseconds to
|
||||
wait for the soft stop to complete for the GPU jobs before
|
||||
proceeding with the GPU reset.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/soft_job_timeout
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU. It used to set the timeout
|
||||
value for waiting for any soft event to complete.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/scheduling/serialize_jobs
|
||||
Description:
|
||||
This attribute is available only with platform device that
|
||||
supports a Job Manager based GPU.
|
||||
|
||||
Various options available under this are:
|
||||
• none - for disabling serialization.
|
||||
• intra-slot - Serialize atoms within a slot, only one
|
||||
atom per job slot.
|
||||
• inter-slot - Serialize atoms between slots, only one
|
||||
job slot running at any time.
|
||||
• full - it a combination of both inter and intra slot,
|
||||
so only one atom and one job slot running
|
||||
at any time.
|
||||
• full-reset - full serialization and Reset the GPU after
|
||||
each atom completion
|
||||
|
||||
These options are useful for debugging and investigating
|
||||
failures and gpu hangs to narrow down atoms that could cause
|
||||
troubles.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/firmware_config/Compute iterator count/*
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. Its a read-only attribute
|
||||
which indicates the maximum number of Compute iterators
|
||||
supported by the GPU.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/firmware_config/CSHWIF count/*
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. Its a read-only
|
||||
attribute which indicates the maximum number of CSHWIFs
|
||||
supported by the GPU.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/firmware_config/Fragment iterator count/*
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. Its a read-only
|
||||
attribute which indicates the maximum number of
|
||||
Fragment iterators supported by the GPU.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/firmware_config/Scoreboard set count/*
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. Its a read-only
|
||||
attribute which indicates the maximum number of
|
||||
Scoreboard set supported by the GPU.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/firmware_config/Tiler iterator count/*
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU. Its a read-only
|
||||
attribute which indicates the maximum number of Tiler iterators
|
||||
supported by the GPU.
|
||||
|
||||
What: /sys/class/misc/mali%u/device/firmware_config/Log verbosity/*
|
||||
Description:
|
||||
This attribute is available only with mali platform
|
||||
device-driver that supports a CSF GPU.
|
||||
|
||||
Used to enable firmware logs, logging levels valid values
|
||||
are indicated using 'min and 'max' attribute values
|
||||
values that are read-only.
|
||||
|
||||
Log level can be set using the 'cur' read, write attribute,
|
||||
we can use a valid log level value from min and max range values
|
||||
and set a valid desired log level for firmware logs.
|
||||
113
Documentation/ABI/testing/sysfs-device-mali-coresight-source
Normal file
113
Documentation/ABI/testing/sysfs-device-mali-coresight-source
Normal file
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
*
|
||||
* (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program is free software and is provided to you under the terms of the
|
||||
* GNU General Public License version 2 as published by the Free Software
|
||||
* Foundation) and any use by you of this program is subject to the terms
|
||||
* of such GNU licence.
|
||||
*
|
||||
* A copy of the licence is included with the program) and can also be obtained
|
||||
* from Free Software Foundation) Inc.) 51 Franklin Street) Fifth Floor)
|
||||
* Boston) MA 02110-1301) USA.
|
||||
*
|
||||
*/
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/enable_source
|
||||
Description:
|
||||
Attribute used to enable Coresight Source ETM.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/is_enabled
|
||||
Description:
|
||||
Attribute used to check if Coresight Source ITM is enabled.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/trcconfigr
|
||||
Description:
|
||||
Coresight Source ETM trace configuration to enable global
|
||||
timestamping, and data value tracing.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/trctraceidr
|
||||
Description:
|
||||
Coresight Source ETM trace ID.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/trcvdarcctlr
|
||||
Description:
|
||||
Coresight Source ETM viewData include/exclude address
|
||||
range comparators.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/trcviiectlr
|
||||
Description:
|
||||
Coresight Source ETM viewInst include and exclude control.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-etm/trcstallctlr
|
||||
Description:
|
||||
Coresight Source ETM stall control register.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-itm/enable_source
|
||||
Description:
|
||||
Attribute used to enable Coresight Source ITM.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-itm/is_enabled
|
||||
Description:
|
||||
Attribute used to check if Coresight Source ITM is enabled.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-itm/dwt_ctrl
|
||||
Description:
|
||||
Coresight Source DWT configuration:
|
||||
[0] = 1, enable cycle counter
|
||||
[4:1] = 4, set PC sample rate pf 256 cycles
|
||||
[8:5] = 1, set initial post count value
|
||||
[9] = 1, select position of post count tap on the cycle counter
|
||||
[10:11] = 1, enable sync packets
|
||||
[12] = 1, enable periodic PC sample packets
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-itm/itm_tcr
|
||||
Description:
|
||||
Coresight Source ITM configuration:
|
||||
[0] = 1, Enable ITM
|
||||
[1] = 1, Enable Time stamp generation
|
||||
[2] = 1, Enable sync packet transmission
|
||||
[3] = 1, Enable HW event forwarding
|
||||
[11:10] = 1, Generate TS request approx every 128 cycles
|
||||
[22:16] = 1, Trace bus ID
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/enable_source
|
||||
Description:
|
||||
Attribute used to enable Coresight Source ELA.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/is_enabled
|
||||
Description:
|
||||
Attribute used to check if Coresight Source ELA is enabled.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/select
|
||||
Description:
|
||||
Coresight Source ELA select trace mode:
|
||||
[0], NONE
|
||||
[1], JCN
|
||||
[2], CEU_EXEC
|
||||
[3], CEU_CMDS
|
||||
[4], MCU_AHBP
|
||||
[5], HOST_AXI
|
||||
[6], NR_TRACEMODE
|
||||
|
||||
Refer to specification for more details.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/sigmask0
|
||||
Description:
|
||||
Coresight Source ELA SIGMASK0 register set/get.
|
||||
Refer to specification for more details.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/sigmask4
|
||||
Description:
|
||||
Coresight Source ELA SIGMASK4 register set/get.
|
||||
Refer to specification for more details.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/sigcomp0
|
||||
Description:
|
||||
Coresight Source ELA SIGCOMP0 register set/get.
|
||||
Refer to specification for more details.
|
||||
|
||||
What: /sys/bus/coresight/devices/mali-source-ela/sigcomp4
|
||||
Description:
|
||||
Coresight Source ELA SIGCOMP4 register set/get.
|
||||
Refer to specification for more details.
|
||||
@@ -590,6 +590,64 @@ This governor exposes the following tunables:
|
||||
It effectively causes the frequency to go down ``sampling_down_factor``
|
||||
times slower than it ramps up.
|
||||
|
||||
``interactive``
|
||||
----------------
|
||||
|
||||
The CPUfreq governor `interactive` is designed for latency-sensitive,
|
||||
interactive workloads. This governor sets the CPU speed depending on
|
||||
usage, similar to `ondemand` and `conservative` governors, but with a
|
||||
different set of configurable behaviors.
|
||||
|
||||
The tunable values for this governor are:
|
||||
|
||||
``above_hispeed_delay``
|
||||
When speed is at or above hispeed_freq, wait for
|
||||
this long before raising speed in response to continued high load.
|
||||
The format is a single delay value, optionally followed by pairs of
|
||||
CPU speeds and the delay to use at or above those speeds. Colons can
|
||||
be used between the speeds and associated delays for readability. For
|
||||
example:
|
||||
|
||||
80000 1300000:200000 1500000:40000
|
||||
|
||||
uses delay 80000 uS until CPU speed 1.3 GHz, at which speed delay
|
||||
200000 uS is used until speed 1.5 GHz, at which speed (and above)
|
||||
delay 40000 uS is used. If speeds are specified these must appear in
|
||||
ascending order. Default is 20000 uS.
|
||||
|
||||
``boost``
|
||||
If non-zero, immediately boost speed of all CPUs to at least
|
||||
hispeed_freq until zero is written to this attribute. If zero, allow
|
||||
CPU speeds to drop below hispeed_freq according to load as usual.
|
||||
Default is zero.
|
||||
|
||||
``boostpulse``
|
||||
On each write, immediately boost speed of all CPUs to
|
||||
hispeed_freq for at least the period of time specified by
|
||||
boostpulse_duration, after which speeds are allowed to drop below
|
||||
hispeed_freq according to load as usual. Its a write-only file.
|
||||
|
||||
``boostpulse_duration``
|
||||
Length of time to hold CPU speed at hispeed_freq
|
||||
on a write to boostpulse, before allowing speed to drop according to
|
||||
load as usual. Default is 80000 uS.
|
||||
|
||||
``go_hispeed_load``
|
||||
The CPU load at which to ramp to hispeed_freq.
|
||||
Default is 99%.
|
||||
|
||||
``hispeed_freq``
|
||||
An intermediate "high speed" at which to initially ramp
|
||||
when CPU load hits the value specified in go_hispeed_load. If load
|
||||
stays high for the amount of time specified in above_hispeed_delay,
|
||||
then speed may be bumped higher. Default is the maximum speed allowed
|
||||
by the policy at governor initialization time.
|
||||
|
||||
``io_is_busy``
|
||||
If set, the governor accounts IO time as CPU busy time.
|
||||
|
||||
``min_sample_time``
|
||||
The minimum amount of time to spend at the current
|
||||
|
||||
Frequency Boost Support
|
||||
=======================
|
||||
|
||||
111
Documentation/csf_sync_state_dump.txt
Normal file
111
Documentation/csf_sync_state_dump.txt
Normal file
@@ -0,0 +1,111 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
#
|
||||
# (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU license.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, you can access it online at
|
||||
# http://www.gnu.org/licenses/gpl-2.0.html.
|
||||
#
|
||||
#
|
||||
|
||||
DebugFS interface:
|
||||
------------------
|
||||
|
||||
A new per-kbase-context debugfs file called csf_sync has been implemented
|
||||
which captures the current KCPU & GPU queue state of the not-yet-completed
|
||||
operations and displayed through the debugfs file.
|
||||
This file is at:
|
||||
=======================================================
|
||||
/sys/kernel/debug/mali0/ctx/<pid>_<context id>/csf_sync
|
||||
=======================================================
|
||||
|
||||
Output Format:
|
||||
----------------
|
||||
|
||||
The csf_sync file contains important data for the currently active queues.
|
||||
This data is formatted into two segments, which are separated by a
|
||||
pipe character: the common properties and the operation-specific properties.
|
||||
|
||||
Common Properties:
|
||||
------------------
|
||||
|
||||
* Queue type: GPU or KCPU.
|
||||
* kbase context id and the queue id.
|
||||
* If the queue type is a GPU queue then the group handle is also noted,
|
||||
in the middle of the other two IDs. The slot value is also dumped.
|
||||
* Execution status, which can either be 'P' for pending or 'S' for started.
|
||||
* Command type is then output which indicates the type of dependency
|
||||
(i.e. wait or signal).
|
||||
* Object address which is a pointer to the sync object that the
|
||||
command operates on.
|
||||
* The live value, which is the value of the synchronization object
|
||||
at the time of dumping. This could help to determine why wait
|
||||
operations might be blocked.
|
||||
|
||||
Operation-Specific Properties:
|
||||
------------------------------
|
||||
|
||||
The operation-specific values for KCPU queue fence operations
|
||||
are as follows: a unique timeline name, timeline context, and a fence
|
||||
sequence number. The CQS WAIT and CQS SET are denoted in the sync dump
|
||||
as their OPERATION counterparts, and therefore show the same operation
|
||||
specific values; the argument value to wait on or set to, and operation type,
|
||||
being (by definition) op:gt and op:set for CQS_WAIT and CQS_SET respectively.
|
||||
|
||||
There are only two operation-specific values for operations in GPU queues
|
||||
which are always shown; the argument value to wait on or set/add to,
|
||||
and the operation type (set/add) or wait condition (e.g. LE, GT, GE).
|
||||
|
||||
Examples
|
||||
--------
|
||||
GPU Queue Example
|
||||
------------------
|
||||
|
||||
The following output is of a GPU queue, from a process that has a KCTX ID of 52,
|
||||
is in Queue Group (CSG) 0, and has Queue ID 0. It has started and is waiting on
|
||||
the object at address 0x0000007f81ffc800. The live value is 0,
|
||||
as is the arg value. However, the operation "op" is GT, indicating it's waiting
|
||||
for the live value to surpass the arg value:
|
||||
|
||||
======================================================================================================================================
|
||||
queue:GPU-52-0-0 exec:S cmd:SYNC_WAIT slot:4 obj:0x0000007f81ffc800 live_value:0x0000000000000000 | op:gt arg_value:0x0000000000000000
|
||||
======================================================================================================================================
|
||||
|
||||
The following is an example of GPU queue dump, where the SYNC SET operation
|
||||
is blocked by the preceding SYNC WAIT operation. This shows two GPU queues,
|
||||
with the same KCTX ID of 8, Queue Group (CSG) 0, and Queue ID 0. The SYNC WAIT
|
||||
operation has started, while the SYNC SET is pending, blocked by the SYNC WAIT.
|
||||
Both operations are on the same slot, 2 and have live value of 0. The SYNC WAIT
|
||||
is waiting on the object at address 0x0000007f81ffc800, while the SYNC SET will
|
||||
set the object at address 0x00000000a3bad4fb when it is unblocked.
|
||||
The operation "op" is GT for the SYNC WAIT, indicating it's waiting for the
|
||||
live value to surpass the arg value, while the operation and arg value for the
|
||||
SYNC SET is "set" and "1" respectively:
|
||||
|
||||
======================================================================================================================================
|
||||
queue:GPU-8-0-0 exec:S cmd:SYNC_WAIT slot:2 obj:0x0000007f81ffc800 live_value:0x0000000000000000 | op:gt arg_value:0x0000000000000000
|
||||
queue:GPU-8-0-0 exec:P cmd:SYNC_SET slot:2 obj:0x00000000a3bad4fb live_value:0x0000000000000000 | op:set arg_value:0x0000000000000001
|
||||
======================================================================================================================================
|
||||
|
||||
KCPU Queue Example
|
||||
------------------
|
||||
|
||||
The following is an example of a KCPU queue, from a process that has
|
||||
a KCTX ID of 0 and has Queue ID 1. It has started and is waiting on the
|
||||
object at address 0x0000007fbf6f2ff8. The live value is currently 0 with
|
||||
the "op" being GT indicating it is waiting on the live value to
|
||||
surpass the arg value.
|
||||
|
||||
===============================================================================================================================
|
||||
queue:KCPU-0-1 exec:S cmd:CQS_WAIT_OPERATION obj:0x0000007fbf6f2ff8 live_value:0x0000000000000000 | op:gt arg_value: 0x00000000
|
||||
===============================================================================================================================
|
||||
241
Documentation/devicetree/bindings/arm/mali-bifrost.txt
Normal file
241
Documentation/devicetree/bindings/arm/mali-bifrost.txt
Normal file
@@ -0,0 +1,241 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
#
|
||||
# (C) COPYRIGHT 2013-2022 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU license.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, you can access it online at
|
||||
# http://www.gnu.org/licenses/gpl-2.0.html.
|
||||
#
|
||||
#
|
||||
|
||||
* ARM Mali Midgard / Bifrost devices
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be mali<chip>, replacing digits with x from the back,
|
||||
until malit<Major>xx, and it must end with one of: "arm,malit6xx" or
|
||||
"arm,mali-midgard" or "arm,mali-bifrost"
|
||||
- reg : Physical base address of the device and length of the register area.
|
||||
- interrupts : Contains the three IRQ lines required by T-6xx devices
|
||||
- interrupt-names : Contains the names of IRQ resources in the order they were
|
||||
provided in the interrupts property. Must contain: "JOB, "MMU", "GPU".
|
||||
|
||||
Optional:
|
||||
|
||||
- clocks : One or more pairs of phandle to clock and clock specifier
|
||||
for the Mali device. The order is important: the first clock
|
||||
shall correspond to the "clk_mali" source, while the second clock
|
||||
(that is optional) shall correspond to the "shadercores" source.
|
||||
- clock-names : Shall be set to: "clk_mali", "shadercores".
|
||||
- mali-supply : Phandle to the top level regulator for the Mali device.
|
||||
Refer to
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt for details.
|
||||
- mem-supply : Phandle to memory regulator for the Mali device. This is optional.
|
||||
- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/mali-opp.txt
|
||||
for details.
|
||||
- quirks_gpu : Used to write to the JM_CONFIG or CSF_CONFIG register.
|
||||
Should be used with care. Options passed here are used to override
|
||||
certain default behavior. Note: This will override 'idvs-group-size'
|
||||
field in devicetree and module param 'corestack_driver_control',
|
||||
therefore if 'quirks_gpu' is used then 'idvs-group-size' and
|
||||
'corestack_driver_control' value should be incorporated into 'quirks_gpu'.
|
||||
- quirks_sc : Used to write to the SHADER_CONFIG register.
|
||||
Should be used with care. Options passed here are used to override
|
||||
certain default behavior.
|
||||
- quirks_tiler : Used to write to the TILER_CONFIG register.
|
||||
Should be used with care. Options passed here are used to
|
||||
disable or override certain default behavior.
|
||||
- quirks_mmu : Used to write to the L2_CONFIG register.
|
||||
Should be used with care. Options passed here are used to
|
||||
disable or override certain default behavior.
|
||||
- power_model : Sets the power model parameters. Defined power models include:
|
||||
"mali-simple-power-model", "mali-g51-power-model", "mali-g52-power-model",
|
||||
"mali-g52_r1-power-model", "mali-g71-power-model", "mali-g72-power-model",
|
||||
"mali-g76-power-model", "mali-g77-power-model", "mali-tnax-power-model",
|
||||
"mali-tbex-power-model" and "mali-tbax-power-model".
|
||||
- mali-simple-power-model: this model derives the GPU power usage based
|
||||
on the GPU voltage scaled by the system temperature. Note: it was
|
||||
designed for the Juno platform, and may not be suitable for others.
|
||||
- compatible: Should be "arm,mali-simple-power-model"
|
||||
- dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is
|
||||
multiplied by v^2*f to calculate the dynamic power consumption.
|
||||
- static-coefficient: Coefficient, in uW/V^3, which is
|
||||
multiplied by v^3 to calculate the static power consumption.
|
||||
- ts: An array containing coefficients for the temperature
|
||||
scaling factor. This is used to scale the static power by a
|
||||
factor of tsf/1000000,
|
||||
where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0],
|
||||
and T = temperature in degrees.
|
||||
- thermal-zone: A string identifying the thermal zone used for
|
||||
the GPU
|
||||
- temp-poll-interval-ms: the interval at which the system
|
||||
temperature is polled
|
||||
- mali-g*-power-model(s): unless being stated otherwise, these models derive
|
||||
the GPU power usage based on performance counters, so they are more
|
||||
accurate.
|
||||
- compatible: Should be, as examples, "arm,mali-g51-power-model" /
|
||||
"arm,mali-g72-power-model".
|
||||
- scale: the dynamic power calculated by the power model is
|
||||
multiplied by a factor of 'scale'. This value should be
|
||||
chosen to match a particular implementation.
|
||||
- min_sample_cycles: Fall back to the simple power model if the
|
||||
number of GPU cycles for a given counter dump is less than
|
||||
'min_sample_cycles'. The default value of this should suffice.
|
||||
* Note: when IPA is used, two separate power models (simple and counter-based)
|
||||
are used at different points so care should be taken to configure
|
||||
both power models in the device tree (specifically dynamic-coefficient,
|
||||
static-coefficient and scale) to best match the platform.
|
||||
- power_policy : Sets the GPU power policy at probe time. Available options are
|
||||
"coarse_demand" and "always_on". If not set, then "coarse_demand" is used.
|
||||
- system-coherency : Sets the coherency protocol to be used for coherent
|
||||
accesses made from the GPU.
|
||||
If not set then no coherency is used.
|
||||
- 0 : ACE-Lite
|
||||
- 1 : ACE
|
||||
- 31 : No coherency
|
||||
- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the
|
||||
model is not found in the registered models list. If no model is specified here,
|
||||
a gpu-id based model is picked if available, otherwise the default model is used.
|
||||
- mali-simple-power-model: Default model used on mali
|
||||
- idvs-group-size : Override the IDVS group size value. Tasks are sent to
|
||||
cores in groups of N + 1, so i.e. 0xF means 16 tasks.
|
||||
Valid values are between 0 to 0x3F (including).
|
||||
- l2-size : Override L2 cache size on GPU that supports it
|
||||
- l2-hash : Override L2 hash function on GPU that supports it
|
||||
- l2-hash-values : Override L2 hash function using provided hash values, on GPUs that supports it.
|
||||
It is mutually exclusive with 'l2-hash'. Only one or the other must be
|
||||
used in a supported GPU.
|
||||
- arbiter_if : Phandle to the arbif platform device, used to provide KBASE with an interface
|
||||
to the Arbiter. This is required when using arbitration; setting to a non-NULL
|
||||
value will enable arbitration.
|
||||
If arbitration is in use, then there should be no external GPU control.
|
||||
When arbiter_if is in use then the following must not be:
|
||||
- power_model (no IPA allowed with arbitration)
|
||||
- #cooling-cells
|
||||
- operating-points-v2 (no dvfs in kbase with arbitration)
|
||||
- system-coherency with a value of 1 (no full coherency with arbitration)
|
||||
- int_id_override: list of <ID Setting[7:0]> tuples defining the IDs needed to be
|
||||
set and the setting coresponding to the SYSC_ALLOC register.
|
||||
|
||||
|
||||
Example for a Mali GPU with 1 clock and 1 regulator:
|
||||
|
||||
gpu@0xfc010000 {
|
||||
compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
|
||||
reg = <0xfc010000 0x4000>;
|
||||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
interrupt-names = "JOB", "MMU", "GPU";
|
||||
|
||||
clocks = <&pclk_mali>;
|
||||
clock-names = "clk_mali";
|
||||
mali-supply = <&vdd_mali>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
power_model@0 {
|
||||
compatible = "arm,mali-simple-power-model";
|
||||
static-coefficient = <2427750>;
|
||||
dynamic-coefficient = <4687>;
|
||||
ts = <20000 2000 (-20) 2>;
|
||||
thermal-zone = "gpu";
|
||||
};
|
||||
power_model@1 {
|
||||
compatible = "arm,mali-g71-power-model";
|
||||
scale = <5>;
|
||||
};
|
||||
|
||||
idvs-group-size = <0x7>;
|
||||
l2-size = /bits/ 8 <0x10>;
|
||||
l2-hash = /bits/ 8 <0x04>; /* or l2-hash-values = <0x12345678 0x8765 0xAB>; */
|
||||
};
|
||||
|
||||
gpu_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp@533000000 {
|
||||
opp-hz = /bits/ 64 <533000000>;
|
||||
opp-microvolt = <1250000>;
|
||||
};
|
||||
opp@450000000 {
|
||||
opp-hz = /bits/ 64 <450000000>;
|
||||
opp-microvolt = <1150000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <1125000>;
|
||||
};
|
||||
opp@350000000 {
|
||||
opp-hz = /bits/ 64 <350000000>;
|
||||
opp-microvolt = <1075000>;
|
||||
};
|
||||
opp@266000000 {
|
||||
opp-hz = /bits/ 64 <266000000>;
|
||||
opp-microvolt = <1025000>;
|
||||
};
|
||||
opp@160000000 {
|
||||
opp-hz = /bits/ 64 <160000000>;
|
||||
opp-microvolt = <925000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <912500>;
|
||||
};
|
||||
};
|
||||
|
||||
Example for a Mali GPU with 2 clocks and 2 regulators:
|
||||
|
||||
gpu: gpu@6e000000 {
|
||||
compatible = "arm,mali-midgard";
|
||||
reg = <0x0 0x6e000000 0x0 0x200000>;
|
||||
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
|
||||
interrupt-names = "JOB", "MMU", "GPU";
|
||||
clocks = <&clk_mali 0>, <&clk_mali 1>;
|
||||
clock-names = "clk_mali", "shadercores";
|
||||
mali-supply = <&supply0_3v3>;
|
||||
mem-supply = <&supply1_3v3>;
|
||||
system-coherency = <31>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
};
|
||||
|
||||
gpu_opp_table: opp_table0 {
|
||||
compatible = "operating-points-v2", "operating-points-v2-mali";
|
||||
|
||||
opp@0 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
|
||||
opp-microvolt = <820000>, <800000>;
|
||||
opp-core-mask = /bits/ 64 <0xf>;
|
||||
};
|
||||
opp@1 {
|
||||
opp-hz = /bits/ 64 <40000000>;
|
||||
opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
|
||||
opp-microvolt = <720000>, <700000>;
|
||||
opp-core-mask = /bits/ 64 <0x7>;
|
||||
};
|
||||
opp@2 {
|
||||
opp-hz = /bits/ 64 <30000000>;
|
||||
opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
|
||||
opp-microvolt = <620000>, <700000>;
|
||||
opp-core-mask = /bits/ 64 <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
Example for a Mali GPU supporting PBHA configuration via DTB (default):
|
||||
|
||||
gpu@0xfc010000 {
|
||||
...
|
||||
pbha {
|
||||
int_id_override = <2 0x32>, <9 0x05>, <16 0x32>;
|
||||
propagate_bits = <0x03>;
|
||||
};
|
||||
...
|
||||
};
|
||||
160
Documentation/devicetree/bindings/arm/mali-coresight-source.txt
Normal file
160
Documentation/devicetree/bindings/arm/mali-coresight-source.txt
Normal file
@@ -0,0 +1,160 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
#
|
||||
# (C) COPYRIGHT 2022 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU license.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, you can access it online at
|
||||
# http://www.gnu.org/licenses/gpl-2.0.html.
|
||||
#
|
||||
#
|
||||
=====================================
|
||||
ARM CoreSight Mali Source integration
|
||||
=====================================
|
||||
|
||||
See Documentation/trace/coresight/coresight.rst for detailed information
|
||||
about Coresight.
|
||||
|
||||
This documentation will cover Mali specific devicetree integration.
|
||||
|
||||
References to Sink ports are given as examples. Access to Sink is specific
|
||||
to an implementation and would require dedicated kernel modules.
|
||||
|
||||
ARM Coresight Mali Source ITM
|
||||
=============================
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
- compatible: Has to be "arm,coresight-mali-source-itm"
|
||||
- gpu : phandle to a Mali GPU definition
|
||||
- port:
|
||||
- endpoint:
|
||||
- remote-endpoint: phandle to a Coresight sink port
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
mali-source-itm {
|
||||
compatible = "arm,coresight-mali-source-itm";
|
||||
gpu = <&gpu>;
|
||||
port {
|
||||
mali_source_itm_out_port0: endpoint {
|
||||
remote-endpoint = <&mali_sink_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ARM Coresight Mali Source ETM
|
||||
=============================
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
- compatible: Has to be "arm,coresight-mali-source-etm"
|
||||
- gpu : phandle to a Mali GPU definition
|
||||
- port:
|
||||
- endpoint:
|
||||
- remote-endpoint: phandle to a Coresight sink port
|
||||
|
||||
Example
|
||||
-------
|
||||
|
||||
mali-source-etm {
|
||||
compatible = "arm,coresight-mali-source-etm";
|
||||
gpu = <&gpu>;
|
||||
port {
|
||||
mali_source_etm_out_port0: endpoint {
|
||||
remote-endpoint = <&mali_sink_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ARM Coresight Mali Source ELA
|
||||
=============================
|
||||
|
||||
Required properties
|
||||
-------------------
|
||||
|
||||
- compatible: Has to be "arm,coresight-mali-source-ela"
|
||||
- gpu : phandle to a Mali GPU definition
|
||||
- signal-groups: Signal groups indexed from 0 to 5.
|
||||
Used to configure the signal channels.
|
||||
- sgN: Types of signals attached to one channel.
|
||||
It can be more than one type in the case of
|
||||
JCN request/response.
|
||||
|
||||
Types:
|
||||
- "jcn-request": Can share the channel with "jcn-response"
|
||||
- "jcn-response": Can share the channel with "jcn-request"
|
||||
- "ceu-execution": Cannot share the channel with other types
|
||||
- "ceu-commands": Cannot share the channel with other types
|
||||
- "mcu-ahbp": Cannot share the channel with other types
|
||||
- "host-axi": Cannot share the channel with other types
|
||||
|
||||
|
||||
If the HW implementation shares a common channel
|
||||
for JCN response and request (total of 4 channels),
|
||||
Refer to:
|
||||
- "Example: Shared JCN request/response channel"
|
||||
Otherwise (total of 5 channels), refer to:
|
||||
- "Example: Split JCN request/response channel"
|
||||
- port:
|
||||
- endpoint:
|
||||
- remote-endpoint: phandle to a Coresight sink port
|
||||
|
||||
Example: Split JCN request/response channel
|
||||
--------------------------------------------
|
||||
|
||||
This examples applies to implementations with a total of 5 signal groups,
|
||||
where JCN request and response are assigned to independent channels.
|
||||
|
||||
mali-source-ela {
|
||||
compatible = "arm,coresight-mali-source-ela";
|
||||
gpu = <&gpu>;
|
||||
signal-groups {
|
||||
sg0 = "jcn-request";
|
||||
sg1 = "jcn-response";
|
||||
sg2 = "ceu-execution";
|
||||
sg3 = "ceu-commands";
|
||||
sg4 = "mcu-ahbp";
|
||||
sg5 = "host-axi";
|
||||
};
|
||||
port {
|
||||
mali_source_ela_out_port0: endpoint {
|
||||
remote-endpoint = <&mali_sink_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example: Shared JCN request/response channel
|
||||
--------------------------------------------
|
||||
|
||||
This examples applies to implementations with a total of 4 signal groups,
|
||||
where JCN request and response are assigned to the same channel.
|
||||
|
||||
mali-source-ela {
|
||||
compatible = "arm,coresight-mali-source-ela";
|
||||
gpu = <&gpu>;
|
||||
signal-groups {
|
||||
sg0 = "jcn-request", "jcn-response";
|
||||
sg1 = "ceu-execution";
|
||||
sg2 = "ceu-commands";
|
||||
sg3 = "mcu-ahbp";
|
||||
sg4 = "host-axi";
|
||||
};
|
||||
port {
|
||||
mali_source_ela_out_port0: endpoint {
|
||||
remote-endpoint = <&mali_sink_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
96
Documentation/devicetree/bindings/arm/mali-midgard.txt
Normal file
96
Documentation/devicetree/bindings/arm/mali-midgard.txt
Normal file
@@ -0,0 +1,96 @@
|
||||
#
|
||||
# (C) COPYRIGHT 2013-2017 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU licence.
|
||||
#
|
||||
# A copy of the licence is included with the program, and can also be obtained
|
||||
# from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
#
|
||||
|
||||
|
||||
* ARM Mali Midgard devices
|
||||
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : Should be mali<chip>, replacing digits with x from the back,
|
||||
until malit<Major>xx, ending with arm,mali-midgard, the latter not optional.
|
||||
- reg : Physical base address of the device and length of the register area.
|
||||
- interrupts : Contains the three IRQ lines required by T-6xx devices
|
||||
- interrupt-names : Contains the names of IRQ resources in the order they were
|
||||
provided in the interrupts property. Must contain: "JOB, "MMU", "GPU".
|
||||
|
||||
Optional:
|
||||
|
||||
- clocks : Phandle to clock for the Mali T-6xx device.
|
||||
- clock-names : Shall be "clk_mali".
|
||||
- mali-supply : Phandle to regulator for the Mali device. Refer to
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt for details.
|
||||
- operating-points : Refer to Documentation/devicetree/bindings/power/opp.txt
|
||||
for details.
|
||||
- jm_config : For T860/T880. Sets job manager configuration. An array containing:
|
||||
- 1 to override the TIMESTAMP value, 0 otherwise.
|
||||
- 1 to override clock gate, forcing them to be always on, 0 otherwise.
|
||||
- 1 to enable job throttle, limiting the number of cores that can be started
|
||||
simultaneously, 0 otherwise.
|
||||
- Value between 0 and 63 (including). If job throttle is enabled, this is one
|
||||
less than the number of cores that can be started simultaneously.
|
||||
- power_model : Sets power model parameters. Note that this model was designed for the Juno
|
||||
platform, and may not be suitable for other platforms. A structure containing :
|
||||
- compatible: Should be arm,mali-simple-power-model
|
||||
- dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is multiplied
|
||||
by v^2*f to calculate the dynamic power consumption.
|
||||
- static-coefficient: Coefficient, in uW/V^3, which is multiplied by
|
||||
v^3 to calculate the static power consumption.
|
||||
- ts: An array containing coefficients for the temperature scaling
|
||||
factor. This is used to scale the static power by a factor of
|
||||
tsf/1000000, where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0],
|
||||
and T = temperature in degrees.
|
||||
- thermal-zone: A string identifying the thermal zone used for the GPU
|
||||
- system-coherency : Sets the coherency protocol to be used for coherent
|
||||
accesses made from the GPU.
|
||||
If not set then no coherency is used.
|
||||
- 0 : ACE-Lite
|
||||
- 1 : ACE
|
||||
- 31 : No coherency
|
||||
- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the
|
||||
model is not found in the registered models list. If no model is specified here,
|
||||
a gpu-id based model is picked if available, otherwise the default model is used.
|
||||
- mali-simple-power-model: Default model used on mali
|
||||
- protected-mode-switcher : Phandle to device implemented protected mode switching functionality.
|
||||
Refer to Documentation/devicetree/bindings/arm/smc-protected-mode-switcher.txt for one implementation.
|
||||
|
||||
Example for a Mali-T602:
|
||||
|
||||
gpu@0xfc010000 {
|
||||
compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
|
||||
reg = <0xfc010000 0x4000>;
|
||||
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
|
||||
interrupt-names = "JOB", "MMU", "GPU";
|
||||
|
||||
clocks = <&pclk_mali>;
|
||||
clock-names = "clk_mali";
|
||||
mali-supply = <&vdd_mali>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
533000 1250000,
|
||||
450000 1150000,
|
||||
400000 1125000,
|
||||
350000 1075000,
|
||||
266000 1025000,
|
||||
160000 925000,
|
||||
100000 912500,
|
||||
>;
|
||||
power_model {
|
||||
compatible = "arm,mali-simple-power-model";
|
||||
static-coefficient = <2427750>;
|
||||
dynamic-coefficient = <4687>;
|
||||
ts = <20000 2000 (-20) 2>;
|
||||
thermal-zone = "gpu";
|
||||
};
|
||||
};
|
||||
68
Documentation/devicetree/bindings/arm/mali-utgard.txt
Normal file
68
Documentation/devicetree/bindings/arm/mali-utgard.txt
Normal file
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* Copyright (C) 2014, 2016-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* This program is free software and is provided to you under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation, and any use by you of this program is subject to the terms of such GNU licence.
|
||||
*
|
||||
* A copy of the licence is included with the program, and can also be obtained from Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
* ARM Mali-300/400/450 GPU
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
At least one of these: "arm,mali-300", "arm,mali-400", "arm,mali-450"
|
||||
Always: "arm,mali-utgard"
|
||||
Mali-450 can also include "arm,mali-400" as it is compatible.
|
||||
- "arm,mali-400", "arm,mali-utgard" for any Mali-400 GPU.
|
||||
- "arm,mali-450", "arm,mali-400", "arm,mali-utgard" for any Mali-450 GPU.
|
||||
- reg:
|
||||
Physical base address and length of the GPU's registers.
|
||||
- interrupts:
|
||||
- List of all Mali interrupts.
|
||||
- This list must match the number of and the order of entries in
|
||||
interrupt-names.
|
||||
- interrupt-names:
|
||||
- IRQPP<X> - Name for PP interrupts.
|
||||
- IRQPPMMU<X> - Name for interrupts from the PP MMU.
|
||||
- IRQPP - Name for the PP broadcast interrupt (Mali-450 only).
|
||||
- IRQGP - Name for the GP interrupt.
|
||||
- IRQGPMMU - Name for the interrupt from the GP MMU.
|
||||
- IRQPMU - Name for the PMU interrupt (If pmu is implemented in HW, it must be contained).
|
||||
|
||||
Optional properties:
|
||||
- pmu_domain_config:
|
||||
- If the Mali internal PMU is present and the PMU IRQ is specified in
|
||||
interrupt/interrupt-names ("IRQPMU").This contains the mapping of
|
||||
Mali HW units to the PMU power domain.
|
||||
-Mali Dynamic power domain configuration in sequence from 0-11, like:
|
||||
<GP PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 L2$0 L2$1 L2$2>.
|
||||
- pmu-switch-delay:
|
||||
- Only needed if the power gates are connected to the PMU in a high fanout
|
||||
network. This value is the number of Mali clock cycles it takes to
|
||||
enable the power gates and turn on the power mesh. This value will
|
||||
have no effect if a daisy chain implementation is used.
|
||||
|
||||
Platform related properties:
|
||||
- clocks: Phandle to clock for Mali utgard device.
|
||||
- clock-names: the corresponding names of clock in clocks property.
|
||||
- regulator: Phandle to regulator which is power supplier of mali device.
|
||||
|
||||
Example for a Mali400_MP1_PMU device:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
gpu@12300000 {
|
||||
compatible = "arm,mali-400", "arm,mali-utgard";
|
||||
reg = <0x12300000 0x30000>;
|
||||
interrupts = <0 55 4>, <0 56 4>, <0 57 4>, <0 58 4>, <0 59 4>;
|
||||
interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPMU";
|
||||
|
||||
pmu_domain_config = <0x1 0x4 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x2 0x0 0x0>;
|
||||
pmu_switch_delay = <0xff>;
|
||||
clocks = <clock 122>, <clock 123>;
|
||||
clock-names = "mali_parent", "mali";
|
||||
vdd_g3d-supply = <regulator_Phandle>;
|
||||
};
|
||||
}
|
||||
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
#
|
||||
# (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU license.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, you can access it online at
|
||||
# http://www.gnu.org/licenses/gpl-2.0.html.
|
||||
#
|
||||
#
|
||||
|
||||
* Arm memory group manager for Mali GPU device drivers
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "arm,physical-memory-group-manager"
|
||||
|
||||
An example node:
|
||||
|
||||
gpu_physical_memory_group_manager: physical-memory-group-manager {
|
||||
compatible = "arm,physical-memory-group-manager";
|
||||
};
|
||||
|
||||
It must be referenced by the GPU as well, see physical-memory-group-manager:
|
||||
|
||||
gpu: gpu@0x6e000000 {
|
||||
compatible = "arm,mali-midgard";
|
||||
reg = <0x0 0x6e000000 0x0 0x200000>;
|
||||
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
|
||||
interrupt-names = "JOB", "MMU", "GPU";
|
||||
clocks = <&scpi_dvfs 2>;
|
||||
clock-names = "clk_mali";
|
||||
system-coherency = <31>;
|
||||
physical-memory-group-manager = <&gpu_physical_memory_group_manager>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
50000 820000
|
||||
>;
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
#
|
||||
# (C) COPYRIGHT 2020-2021 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU license.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, you can access it online at
|
||||
# http://www.gnu.org/licenses/gpl-2.0.html.
|
||||
#
|
||||
#
|
||||
|
||||
* Arm priority control manager for Mali GPU device drivers
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "arm,priority-control-manager"
|
||||
|
||||
An example node:
|
||||
|
||||
gpu_priority_control_manager: priority-control-manager {
|
||||
compatible = "arm,priority-control-manager";
|
||||
};
|
||||
|
||||
It must be referenced by the GPU as well, see priority-control-manager:
|
||||
|
||||
gpu: gpu@0x6e000000 {
|
||||
compatible = "arm,mali-midgard";
|
||||
reg = <0x0 0x6e000000 0x0 0x200000>;
|
||||
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
|
||||
interrupt-names = "JOB", "MMU", "GPU";
|
||||
clocks = <&scpi_dvfs 2>;
|
||||
clock-names = "clk_mali";
|
||||
system-coherency = <31>;
|
||||
priority-control-manager = <&gpu_priority_control_manager>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
50000 820000
|
||||
>;
|
||||
};
|
||||
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
|
||||
#
|
||||
# (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
|
||||
#
|
||||
# This program is free software and is provided to you under the terms of the
|
||||
# GNU General Public License version 2 as published by the Free Software
|
||||
# Foundation, and any use by you of this program is subject to the terms
|
||||
# of such GNU license.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, you can access it online at
|
||||
# http://www.gnu.org/licenses/gpl-2.0.html.
|
||||
#
|
||||
#
|
||||
|
||||
* Arm protected memory allocator for Mali GPU device drivers
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Must be "arm,protected-memory-allocator"
|
||||
|
||||
The protected memory allocator manages allocation of physical pages of a
|
||||
reserved memory region of protected memory, therefore its device node shall
|
||||
reference a reserved memory region.
|
||||
|
||||
In addition to that, the protected memory allocator shall be referenced
|
||||
by the GPU.
|
||||
|
||||
A complete example configuration for the device tree:
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
mali_protected: mali_protected@c0000000 {
|
||||
compatible = "mali-reserved";
|
||||
reg = <0x0 0xc0000000 0x0 0x1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpu_protected_memory_allocator: protected-memory-allocator {
|
||||
compatible = "arm,protected-memory-allocator";
|
||||
memory-region = <&mali_protected>;
|
||||
};
|
||||
|
||||
gpu_fpga: gpu@0x6e000000 {
|
||||
compatible = "arm,mali-midgard";
|
||||
reg = <0x0 0x6e000000 0x0 0x200000>;
|
||||
interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
|
||||
interrupt-names = "JOB", "MMU", "GPU";
|
||||
clocks = <&scpi_dvfs 2>;
|
||||
clock-names = "clk_mali";
|
||||
protected-memory-allocator = <&gpu_protected_memory_allocator>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
50000 820000
|
||||
>;
|
||||
};
|
||||
|
||||
The protected memory allocator is gpu_protected_memory_allocator.
|
||||
It references the mali_protected reserved memory region and, in turn,
|
||||
it is referenced by the GPU as protected-memory-allocator.
|
||||
24
Documentation/devicetree/bindings/clock/clk-pvtm.txt
Normal file
24
Documentation/devicetree/bindings/clock/clk-pvtm.txt
Normal file
@@ -0,0 +1,24 @@
|
||||
ROCKCHIP PVTM 32KHz clocks *
|
||||
|
||||
ROCKCHIP device has two clock sources for 32KHz, external 32k osc and internal pvtm 32k.
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : "rockchip,rk3368-pvtm-clock" for rk3368 soc pvtm 32k clock
|
||||
- #clock-cells : shall be set to 0.
|
||||
|
||||
Optional property:
|
||||
- clock-output-names : From common clock binding.
|
||||
|
||||
Example:
|
||||
pvtm_clock: pvtm-clock {
|
||||
compatible = "rockchip,rk3368-pvtm-clock";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&cru SCLK_PVTM_PMU>;
|
||||
clock-names = "pvtm_pmu_clk";
|
||||
clock-output-names = "xin32k_pvtm";
|
||||
status = "okay";
|
||||
};
|
||||
107
Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
Normal file
107
Documentation/devicetree/bindings/clock/rockchip,clk-out.yaml
Normal file
@@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip Clock Out Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Sugar Zhang <sugar.zhang@rock-chips.com>
|
||||
|
||||
description: |
|
||||
This add support switch for clk-bidirection which located
|
||||
at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
|
||||
and these config maybe located in many pieces of GRF,
|
||||
which hard to addressed in one single clk driver. so, we add
|
||||
this simple helper driver to address this situation.
|
||||
|
||||
In order to simplify implement and usage, and also for safety
|
||||
clk usage (avoid high freq glitch), we set all clk out as disabled
|
||||
(which means Input default for clk-bidrection) in the pre-stage,
|
||||
such boot-loader or init by HW default. And then set a safety freq
|
||||
before enable clk-out, such as "assign-clock-rates" or clk_set_rate
|
||||
in drivers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,clk-out
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description: parent clocks.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
rockchip,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Defines the bit shift of clk out enable.
|
||||
|
||||
rockchip,bit-set-to-disable:
|
||||
type: boolean
|
||||
description: |
|
||||
By default this clock sets the bit at bit-shift to enable the clock.
|
||||
Setting this property does the opposite: setting the bit disable
|
||||
the clock and clearing it enables the clock.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
- clock-output-names
|
||||
- rockchip,bit-shift
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Provider node:
|
||||
- |
|
||||
mclkin_sai0: mclkin-sai0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12288000>;
|
||||
clock-output-names = "mclk_sai0_from_io";
|
||||
};
|
||||
|
||||
mclkout_sai0: mclkout-sai0@ff040070 {
|
||||
compatible = "rockchip,clk-out";
|
||||
reg = <0 0xff040070 0 0x4>;
|
||||
clocks = <&cru MCLK_SAI0_OUT2IO>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk_sai0_to_io";
|
||||
rockchip,bit-shift = <4>;
|
||||
};
|
||||
|
||||
# Clock mclkout Consumer node:
|
||||
- |
|
||||
ext_codec {
|
||||
clocks = <&mclkout_sai0>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&mclkout_sai0>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_mclk>;
|
||||
};
|
||||
|
||||
# Clock mclkin Consumer node:
|
||||
- |
|
||||
ext_codec {
|
||||
clocks = <&mclkin_sai0>;
|
||||
clock-names = "mclk";
|
||||
assigned-clocks = <&cru CLK_SAI0>;
|
||||
assigned-clock-parents = <&mclkin_sai0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s0m0_mclk>;
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
* Rockchip RK1808 Clock and Reset Unit
|
||||
|
||||
The RK1808 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk1808-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk1808-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "mclk_i2s0_8ch_in" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff350000 {
|
||||
compatible = "rockchip,rk1808-cru";
|
||||
reg = <0x0 0xff350000 0x0 0x5000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart1: serial@ff540000 {
|
||||
compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff540000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
};
|
||||
58
Documentation/devicetree/bindings/clock/rockchip,rk3308.txt
Normal file
58
Documentation/devicetree/bindings/clock/rockchip,rk3308.txt
Normal file
@@ -0,0 +1,58 @@
|
||||
* Rockchip RK3308 Clock and Reset Unit
|
||||
|
||||
The RK3308 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: CRU should be "rockchip,rk3308-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3308-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "mclk_i2sx_xch_in" - external I2S or SPDIF clock - optional,
|
||||
- "mac_clkin" - external MAC clock - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff500000 {
|
||||
compatible = "rockchip,rk3308-cru";
|
||||
reg = <0x0 0xff500000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff0a0000 {
|
||||
compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff0a0000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -0,0 +1,66 @@
|
||||
* Rockchip RK3568 Clock and Reset Unit
|
||||
|
||||
The RK3568 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: PMU for CRU should be "rockchip,rk3568-pmucru"
|
||||
- compatible: CRU should be "rockchip,rk3568-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing, pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3568-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "i2sx_mclkin" - external I2S clock - optional,
|
||||
- "xin_osc0_usbphyx_g" - external USBPHY clock - optional,
|
||||
- "xin_osc0_mipidsiphyx_g" - external MIPIDSIPHY clock - optional,
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
pmucru: clock-controller@fdd00000 {
|
||||
compatible = "rockchip,rK3568-pmucru";
|
||||
reg = <0x0 0xfdd00000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@fdd20000 {
|
||||
compatible = "rockchip,rK3568-cru";
|
||||
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart1: serial@fe650000 {
|
||||
compatible = "rockchip,rK3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe650000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
};
|
||||
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ROCKCHIP rk3588 Family Clock Control Module Binding
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3588 clock controller generates the clock and also implements a
|
||||
reset controller for SoC peripherals.
|
||||
(examples: provide SCLK_UART2\PCLK_UART2 and SRST_P_UART2\SRST_S_UART2 for UART module)
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3588-cru.h headers and can be
|
||||
used in device tree sources.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3588-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks: true
|
||||
|
||||
assigned-clocks:
|
||||
minItems: 1
|
||||
|
||||
assigned-clock-parents:
|
||||
minItems: 1
|
||||
|
||||
assigned-clock-rates:
|
||||
minItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock Control Module node:
|
||||
- |
|
||||
cru: clock-controller@fd7c0000 {
|
||||
compatible = "rockchip,rk3588-cru";
|
||||
reg = <0xfd7c0000 0x5c000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,29 @@
|
||||
Rockchip RK618 Clock and Reset Unit
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties :
|
||||
- compatible : Should be "rockchip,rk618-cru"
|
||||
- clocks : Should contain phandle and clock specifiers for the input clock:
|
||||
the AP I2S master clock output(mclk) "clkin", and the AP LCDC master
|
||||
dclk output(dclk) "lcdc0_dclkp".
|
||||
- #clock-cells : Should be 1.
|
||||
|
||||
Example:
|
||||
|
||||
&rk618 {
|
||||
CRU: cru {
|
||||
compatible = "rockchip,rk618-cru";
|
||||
clocks = <&cru SCLK_I2S_8CH_OUT>, <&cru DCLK_VOP>;
|
||||
clock-names = "clkin", "lcdc0_dclkp";
|
||||
assigned-clocks = <&CRU SCALER_PLLIN_CLK>, <&CRU VIF_PLLIN_CLK>,
|
||||
<&CRU HDMI_CLK>, <&CRU SCALER_CLK>,
|
||||
<&CRU CODEC_CLK>;
|
||||
assigned-clock-parents = <&CRU LCDC0_CLK>, <&CRU LCDC0_CLK>,
|
||||
<&CRU VIF0_CLK>, <&CRU SCALER_PLL_CLK>,
|
||||
<&cru SCLK_I2S_8CH_OUT>;
|
||||
#clock-cells = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user