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Merge 4.5-rc4 into driver-core-next
We want the fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
@@ -7,7 +7,7 @@ This is the authoritative documentation on the design, interface and
|
||||
conventions of cgroup v2. It describes all userland-visible aspects
|
||||
of cgroup including core and specific controller behaviors. All
|
||||
future changes must be reflected in this document. Documentation for
|
||||
v1 is available under Documentation/cgroup-legacy/.
|
||||
v1 is available under Documentation/cgroup-v1/.
|
||||
|
||||
CONTENTS
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|
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@@ -8,6 +8,7 @@ OHCI and EHCI controllers.
|
||||
Required properties:
|
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- compatible: "renesas,pci-r8a7790" for the R8A7790 SoC;
|
||||
"renesas,pci-r8a7791" for the R8A7791 SoC;
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"renesas,pci-r8a7793" for the R8A7793 SoC;
|
||||
"renesas,pci-r8a7794" for the R8A7794 SoC;
|
||||
"renesas,pci-rcar-gen2" for a generic R-Car Gen2 compatible device
|
||||
|
||||
|
||||
@@ -4,6 +4,7 @@ Required properties:
|
||||
compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
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"renesas,pcie-r8a7790" for the R8A7790 SoC;
|
||||
"renesas,pcie-r8a7791" for the R8A7791 SoC;
|
||||
"renesas,pcie-r8a7793" for the R8A7793 SoC;
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"renesas,pcie-r8a7795" for the R8A7795 SoC;
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"renesas,pcie-rcar-gen2" for a generic R-Car Gen2 compatible device.
|
||||
|
||||
|
||||
@@ -30,6 +30,8 @@ The compatible list for this generic sound card currently:
|
||||
"fsl,imx-audio-sgtl5000"
|
||||
(compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt)
|
||||
|
||||
"fsl,imx-audio-wm8960"
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|
||||
Required properties:
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||||
|
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- compatible : Contains one of entries in the compatible list.
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@@ -1,8 +1,9 @@
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* Renesas R-Car Thermal
|
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|
||||
Required properties:
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- compatible : "renesas,thermal-<soctype>", "renesas,rcar-thermal"
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as fallback.
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- compatible : "renesas,thermal-<soctype>",
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"renesas,rcar-gen2-thermal" (with thermal-zone) or
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"renesas,rcar-thermal" (without thermal-zone) as fallback.
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Examples with soctypes are:
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- "renesas,thermal-r8a73a4" (R-Mobile APE6)
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- "renesas,thermal-r8a7779" (R-Car H1)
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@@ -36,3 +37,35 @@ thermal@e61f0000 {
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0xe61f0300 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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};
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Example (with thermal-zone):
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <1000>;
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polling-delay = <5000>;
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thermal-sensors = <&thermal>;
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trips {
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cpu-crit {
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temperature = <115000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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};
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};
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};
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thermal: thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7790",
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"renesas,rcar-gen2-thermal",
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"renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
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power-domains = <&cpg_clocks>;
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#thermal-sensor-cells = <0>;
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};
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@@ -4235,6 +4235,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
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The default value of this parameter is determined by
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the config option CONFIG_WQ_POWER_EFFICIENT_DEFAULT.
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workqueue.debug_force_rr_cpu
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Workqueue used to implicitly guarantee that work
|
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items queued without explicit CPU specified are put
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on the local CPU. This guarantee is no longer true
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and while local CPU is still preferred work items
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may be put on foreign CPUs. This debug option
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forces round-robin CPU selection to flush out
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usages which depend on the now broken guarantee.
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When enabled, memory and cache locality will be
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impacted.
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x2apic_phys [X86-64,APIC] Use x2apic physical mode instead of
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default x2apic cluster mode on platforms
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supporting x2apic.
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|
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17
MAINTAINERS
17
MAINTAINERS
@@ -2362,14 +2362,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git
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S: Maintained
|
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N: bcm2835
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BROADCOM BCM33XX MIPS ARCHITECTURE
|
||||
M: Kevin Cernekee <cernekee@gmail.com>
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L: linux-mips@linux-mips.org
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S: Maintained
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F: arch/mips/bcm3384/*
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F: arch/mips/include/asm/mach-bcm3384/*
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F: arch/mips/kernel/*bmips*
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|
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BROADCOM BCM47XX MIPS ARCHITECTURE
|
||||
M: Hauke Mehrtens <hauke@hauke-m.de>
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M: Rafał Miłecki <zajec5@gmail.com>
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@@ -9787,10 +9779,11 @@ S: Supported
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F: drivers/scsi/be2iscsi/
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|
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Emulex 10Gbps NIC BE2, BE3-R, Lancer, Skyhawk-R DRIVER
|
||||
M: Sathya Perla <sathya.perla@avagotech.com>
|
||||
M: Ajit Khaparde <ajit.khaparde@avagotech.com>
|
||||
M: Padmanabh Ratnakar <padmanabh.ratnakar@avagotech.com>
|
||||
M: Sriharsha Basavapatna <sriharsha.basavapatna@avagotech.com>
|
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M: Sathya Perla <sathya.perla@broadcom.com>
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M: Ajit Khaparde <ajit.khaparde@broadcom.com>
|
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M: Padmanabh Ratnakar <padmanabh.ratnakar@broadcom.com>
|
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M: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com>
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M: Somnath Kotur <somnath.kotur@broadcom.com>
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L: netdev@vger.kernel.org
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W: http://www.emulex.com
|
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S: Supported
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|
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2
Makefile
2
Makefile
@@ -1,7 +1,7 @@
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VERSION = 4
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PATCHLEVEL = 5
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SUBLEVEL = 0
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EXTRAVERSION = -rc3
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EXTRAVERSION = -rc4
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NAME = Blurry Fish Butt
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# *DOCUMENTATION*
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@@ -338,6 +338,19 @@ config ARC_PAGE_SIZE_4K
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endchoice
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choice
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prompt "MMU Super Page Size"
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depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
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default ARC_HUGEPAGE_2M
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config ARC_HUGEPAGE_2M
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bool "2MB"
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config ARC_HUGEPAGE_16M
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bool "16MB"
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endchoice
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if ISA_ARCOMPACT
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config ARC_COMPACT_IRQ_LEVELS
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@@ -410,7 +423,7 @@ config ARC_HAS_RTC
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default n
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depends on !SMP
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config ARC_HAS_GRTC
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config ARC_HAS_GFRC
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bool "SMP synchronized 64-bit cycle counter"
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default y
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depends on SMP
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@@ -566,6 +579,12 @@ endmenu
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endmenu # "ARC Architecture Configuration"
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source "mm/Kconfig"
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config FORCE_MAX_ZONEORDER
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int "Maximum zone order"
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default "12" if ARC_HUGEPAGE_16M
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default "11"
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source "net/Kconfig"
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source "drivers/Kconfig"
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source "fs/Kconfig"
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@@ -16,7 +16,7 @@ CONFIG_ARC_PLAT_AXS10X=y
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CONFIG_AXS103=y
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CONFIG_ISA_ARCV2=y
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CONFIG_SMP=y
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# CONFIG_ARC_HAS_GRTC is not set
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# CONFIG_ARC_HAS_GFRC is not set
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CONFIG_ARC_UBOOT_SUPPORT=y
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CONFIG_ARC_BUILTIN_DTB_NAME="vdk_hs38_smp"
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CONFIG_PREEMPT=y
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@@ -349,14 +349,13 @@ struct cpuinfo_arc {
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struct cpuinfo_arc_bpu bpu;
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struct bcr_identity core;
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struct bcr_isa isa;
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struct bcr_timer timers;
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unsigned int vec_base;
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struct cpuinfo_arc_ccm iccm, dccm;
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struct {
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unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3,
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fpu_sp:1, fpu_dp:1, pad2:6,
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debug:1, ap:1, smart:1, rtt:1, pad3:4,
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pad4:8;
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timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
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} extn;
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struct bcr_mpy extn_mpy;
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struct bcr_extn_xymem extn_xymem;
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@@ -30,8 +30,11 @@
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/* Was Intr taken in User Mode */
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#define AUX_IRQ_ACT_BIT_U 31
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/* 0 is highest level, but taken by FIRQs, if present in design */
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#define ARCV2_IRQ_DEF_PRIO 0
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/*
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* User space should be interruptable even by lowest prio interrupt
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* Safe even if actual interrupt priorities is fewer or even one
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*/
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#define ARCV2_IRQ_DEF_PRIO 15
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/* seed value for status register */
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#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
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@@ -39,8 +39,8 @@ struct mcip_cmd {
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#define CMD_DEBUG_SET_MASK 0x34
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#define CMD_DEBUG_SET_SELECT 0x36
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#define CMD_GRTC_READ_LO 0x42
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#define CMD_GRTC_READ_HI 0x43
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#define CMD_GFRC_READ_LO 0x42
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#define CMD_GFRC_READ_HI 0x43
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#define CMD_IDU_ENABLE 0x71
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#define CMD_IDU_DISABLE 0x72
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@@ -179,37 +179,44 @@
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#define __S111 PAGE_U_X_W_R
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/****************************************************************
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* Page Table Lookup split
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* 2 tier (PGD:PTE) software page walker
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*
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* We implement 2 tier paging and since this is all software, we are free
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* to customize the span of a PGD / PTE entry to suit us
|
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*
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* 32 bit virtual address
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* [31] 32 bit virtual address [0]
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* -------------------------------------------------------
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* | BITS_FOR_PGD | BITS_FOR_PTE | BITS_IN_PAGE |
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* | | <------------ PGDIR_SHIFT ----------> |
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* | | |
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* | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
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* -------------------------------------------------------
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* | | |
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* | | --> off in page frame
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* | |
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* | ---> index into Page Table
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* |
|
||||
* ----> index into Page Directory
|
||||
*
|
||||
* In a single page size configuration, only PAGE_SHIFT is fixed
|
||||
* So both PGD and PTE sizing can be tweaked
|
||||
* e.g. 8K page (PAGE_SHIFT 13) can have
|
||||
* - PGDIR_SHIFT 21 -> 11:8:13 address split
|
||||
* - PGDIR_SHIFT 24 -> 8:11:13 address split
|
||||
*
|
||||
* If Super Page is configured, PGDIR_SHIFT becomes fixed too,
|
||||
* so the sizing flexibility is gone.
|
||||
*/
|
||||
|
||||
#define BITS_IN_PAGE PAGE_SHIFT
|
||||
|
||||
/* Optimal Sizing of Pg Tbl - based on MMU page size */
|
||||
#if defined(CONFIG_ARC_PAGE_SIZE_8K)
|
||||
#define BITS_FOR_PTE 8 /* 11:8:13 */
|
||||
#elif defined(CONFIG_ARC_PAGE_SIZE_16K)
|
||||
#define BITS_FOR_PTE 8 /* 10:8:14 */
|
||||
#elif defined(CONFIG_ARC_PAGE_SIZE_4K)
|
||||
#define BITS_FOR_PTE 9 /* 11:9:12 */
|
||||
#if defined(CONFIG_ARC_HUGEPAGE_16M)
|
||||
#define PGDIR_SHIFT 24
|
||||
#elif defined(CONFIG_ARC_HUGEPAGE_2M)
|
||||
#define PGDIR_SHIFT 21
|
||||
#else
|
||||
/*
|
||||
* Only Normal page support so "hackable" (see comment above)
|
||||
* Default value provides 11:8:13 (8K), 11:9:12 (4K)
|
||||
*/
|
||||
#define PGDIR_SHIFT 21
|
||||
#endif
|
||||
|
||||
#define BITS_FOR_PGD (32 - BITS_FOR_PTE - BITS_IN_PAGE)
|
||||
#define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
|
||||
#define BITS_FOR_PGD (32 - PGDIR_SHIFT)
|
||||
|
||||
#define PGDIR_SHIFT (32 - BITS_FOR_PGD)
|
||||
#define PGDIR_SIZE (1UL << PGDIR_SHIFT) /* vaddr span, not PDG sz */
|
||||
#define PGDIR_MASK (~(PGDIR_SIZE-1))
|
||||
|
||||
|
||||
@@ -211,7 +211,11 @@ debug_marker_syscall:
|
||||
; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
|
||||
; entry was via Exception in DS which got preempted in kernel).
|
||||
;
|
||||
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs handling
|
||||
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
|
||||
;
|
||||
; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
|
||||
; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
|
||||
|
||||
.Lintr_ret_to_delay_slot:
|
||||
debug_marker_ds:
|
||||
|
||||
@@ -222,18 +226,23 @@ debug_marker_ds:
|
||||
ld r2, [sp, PT_ret]
|
||||
ld r3, [sp, PT_status32]
|
||||
|
||||
; STAT32 for Int return created from scratch
|
||||
; (No delay dlot, disable Further intr in trampoline)
|
||||
|
||||
bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
|
||||
st r0, [sp, PT_status32]
|
||||
|
||||
mov r1, .Lintr_ret_to_delay_slot_2
|
||||
st r1, [sp, PT_ret]
|
||||
|
||||
; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
|
||||
st r2, [sp, 0]
|
||||
st r3, [sp, 4]
|
||||
|
||||
b .Lisr_ret_fast_path
|
||||
|
||||
.Lintr_ret_to_delay_slot_2:
|
||||
; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
|
||||
sub sp, sp, SZ_PT_REGS
|
||||
st r9, [sp, -4]
|
||||
|
||||
@@ -243,11 +252,19 @@ debug_marker_ds:
|
||||
ld r9, [sp, 4]
|
||||
sr r9, [erstatus]
|
||||
|
||||
; restore AUX_USER_SP if returning to U mode
|
||||
bbit0 r9, STATUS_U_BIT, 1f
|
||||
ld r9, [sp, PT_sp]
|
||||
sr r9, [AUX_USER_SP]
|
||||
|
||||
1:
|
||||
ld r9, [sp, 8]
|
||||
sr r9, [erbta]
|
||||
|
||||
ld r9, [sp, -4]
|
||||
add sp, sp, SZ_PT_REGS
|
||||
|
||||
; return from pure kernel mode to delay slot
|
||||
rtie
|
||||
|
||||
END(ret_from_exception)
|
||||
|
||||
@@ -14,6 +14,8 @@
|
||||
#include <linux/irqchip.h>
|
||||
#include <asm/irq.h>
|
||||
|
||||
static int irq_prio;
|
||||
|
||||
/*
|
||||
* Early Hardware specific Interrupt setup
|
||||
* -Called very early (start_kernel -> setup_arch -> setup_processor)
|
||||
@@ -24,6 +26,14 @@ void arc_init_IRQ(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
struct irq_build {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad:3, firq:1, prio:4, exts:8, irqs:8, ver:8;
|
||||
#else
|
||||
unsigned int ver:8, irqs:8, exts:8, prio:4, firq:1, pad:3;
|
||||
#endif
|
||||
} irq_bcr;
|
||||
|
||||
struct aux_irq_ctrl {
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int res3:18, save_idx_regs:1, res2:1,
|
||||
@@ -46,28 +56,25 @@ void arc_init_IRQ(void)
|
||||
|
||||
WRITE_AUX(AUX_IRQ_CTRL, ictrl);
|
||||
|
||||
/* setup status32, don't enable intr yet as kernel doesn't want */
|
||||
tmp = read_aux_reg(0xa);
|
||||
tmp |= ISA_INIT_STATUS_BITS;
|
||||
tmp &= ~STATUS_IE_MASK;
|
||||
asm volatile("flag %0 \n"::"r"(tmp));
|
||||
|
||||
/*
|
||||
* ARCv2 core intc provides multiple interrupt priorities (upto 16).
|
||||
* Typical builds though have only two levels (0-high, 1-low)
|
||||
* Linux by default uses lower prio 1 for most irqs, reserving 0 for
|
||||
* NMI style interrupts in future (say perf)
|
||||
*
|
||||
* Read the intc BCR to confirm that Linux default priority is avail
|
||||
* in h/w
|
||||
*
|
||||
* Note:
|
||||
* IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level
|
||||
* is 0 based.
|
||||
*/
|
||||
tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF;
|
||||
if (ARCV2_IRQ_DEF_PRIO > tmp)
|
||||
panic("Linux default irq prio incorrect\n");
|
||||
|
||||
READ_BCR(ARC_REG_IRQ_BCR, irq_bcr);
|
||||
|
||||
irq_prio = irq_bcr.prio; /* Encoded as N-1 for N levels */
|
||||
pr_info("archs-intc\t: %d priority levels (default %d)%s\n",
|
||||
irq_prio + 1, irq_prio,
|
||||
irq_bcr.firq ? " FIRQ (not used)":"");
|
||||
|
||||
/* setup status32, don't enable intr yet as kernel doesn't want */
|
||||
tmp = read_aux_reg(0xa);
|
||||
tmp |= STATUS_AD_MASK | (irq_prio << 1);
|
||||
tmp &= ~STATUS_IE_MASK;
|
||||
asm volatile("flag %0 \n"::"r"(tmp));
|
||||
}
|
||||
|
||||
static void arcv2_irq_mask(struct irq_data *data)
|
||||
@@ -86,7 +93,7 @@ void arcv2_irq_enable(struct irq_data *data)
|
||||
{
|
||||
/* set default priority */
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, irq_prio);
|
||||
|
||||
/*
|
||||
* hw auto enables (linux unmask) all by default
|
||||
|
||||
@@ -96,13 +96,13 @@ static void mcip_probe_n_setup(void)
|
||||
#ifdef CONFIG_CPU_BIG_ENDIAN
|
||||
unsigned int pad3:8,
|
||||
idu:1, llm:1, num_cores:6,
|
||||
iocoh:1, grtc:1, dbg:1, pad2:1,
|
||||
iocoh:1, gfrc:1, dbg:1, pad2:1,
|
||||
msg:1, sem:1, ipi:1, pad:1,
|
||||
ver:8;
|
||||
#else
|
||||
unsigned int ver:8,
|
||||
pad:1, ipi:1, sem:1, msg:1,
|
||||
pad2:1, dbg:1, grtc:1, iocoh:1,
|
||||
pad2:1, dbg:1, gfrc:1, iocoh:1,
|
||||
num_cores:6, llm:1, idu:1,
|
||||
pad3:8;
|
||||
#endif
|
||||
@@ -116,7 +116,7 @@ static void mcip_probe_n_setup(void)
|
||||
IS_AVAIL1(mp.ipi, "IPI "),
|
||||
IS_AVAIL1(mp.idu, "IDU "),
|
||||
IS_AVAIL1(mp.dbg, "DEBUG "),
|
||||
IS_AVAIL1(mp.grtc, "GRTC"));
|
||||
IS_AVAIL1(mp.gfrc, "GFRC"));
|
||||
|
||||
idu_detected = mp.idu;
|
||||
|
||||
@@ -125,8 +125,8 @@ static void mcip_probe_n_setup(void)
|
||||
__mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc)
|
||||
panic("kernel trying to use non-existent GRTC\n");
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_GFRC) && !mp.gfrc)
|
||||
panic("kernel trying to use non-existent GFRC\n");
|
||||
}
|
||||
|
||||
struct plat_smp_ops plat_smp_ops = {
|
||||
|
||||
@@ -45,6 +45,7 @@ struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
|
||||
static void read_arc_build_cfg_regs(void)
|
||||
{
|
||||
struct bcr_perip uncached_space;
|
||||
struct bcr_timer timer;
|
||||
struct bcr_generic bcr;
|
||||
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
|
||||
unsigned long perip_space;
|
||||
@@ -53,7 +54,11 @@ static void read_arc_build_cfg_regs(void)
|
||||
READ_BCR(AUX_IDENTITY, cpu->core);
|
||||
READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
|
||||
|
||||
READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
|
||||
READ_BCR(ARC_REG_TIMERS_BCR, timer);
|
||||
cpu->extn.timer0 = timer.t0;
|
||||
cpu->extn.timer1 = timer.t1;
|
||||
cpu->extn.rtc = timer.rtc;
|
||||
|
||||
cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
|
||||
|
||||
READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
|
||||
@@ -208,9 +213,9 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
|
||||
(unsigned int)(arc_get_core_freq() / 10000) % 100);
|
||||
|
||||
n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
|
||||
IS_AVAIL1(cpu->timers.t0, "Timer0 "),
|
||||
IS_AVAIL1(cpu->timers.t1, "Timer1 "),
|
||||
IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ",
|
||||
IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
|
||||
IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
|
||||
IS_AVAIL2(cpu->extn.rtc, "Local-64-bit-Ctr ",
|
||||
CONFIG_ARC_HAS_RTC));
|
||||
|
||||
n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
|
||||
@@ -293,13 +298,13 @@ static void arc_chk_core_config(void)
|
||||
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
|
||||
int fpu_enabled;
|
||||
|
||||
if (!cpu->timers.t0)
|
||||
if (!cpu->extn.timer0)
|
||||
panic("Timer0 is not present!\n");
|
||||
|
||||
if (!cpu->timers.t1)
|
||||
if (!cpu->extn.timer1)
|
||||
panic("Timer1 is not present!\n");
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc)
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->extn.rtc)
|
||||
panic("RTC is not present\n");
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_DCCM
|
||||
@@ -334,6 +339,7 @@ static void arc_chk_core_config(void)
|
||||
panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
|
||||
|
||||
if (is_isa_arcv2() && IS_ENABLED(CONFIG_SMP) && cpu->isa.atomic &&
|
||||
IS_ENABLED(CONFIG_ARC_HAS_LLSC) &&
|
||||
!IS_ENABLED(CONFIG_ARC_STAR_9000923308))
|
||||
panic("llock/scond livelock workaround missing\n");
|
||||
}
|
||||
|
||||
@@ -62,7 +62,7 @@
|
||||
|
||||
/********** Clock Source Device *********/
|
||||
|
||||
#ifdef CONFIG_ARC_HAS_GRTC
|
||||
#ifdef CONFIG_ARC_HAS_GFRC
|
||||
|
||||
static int arc_counter_setup(void)
|
||||
{
|
||||
@@ -83,10 +83,10 @@ static cycle_t arc_counter_read(struct clocksource *cs)
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
__mcip_cmd(CMD_GRTC_READ_LO, 0);
|
||||
__mcip_cmd(CMD_GFRC_READ_LO, 0);
|
||||
stamp.l = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
|
||||
__mcip_cmd(CMD_GRTC_READ_HI, 0);
|
||||
__mcip_cmd(CMD_GFRC_READ_HI, 0);
|
||||
stamp.h = read_aux_reg(ARC_REG_MCIP_READBACK);
|
||||
|
||||
local_irq_restore(flags);
|
||||
@@ -95,7 +95,7 @@ static cycle_t arc_counter_read(struct clocksource *cs)
|
||||
}
|
||||
|
||||
static struct clocksource arc_counter = {
|
||||
.name = "ARConnect GRTC",
|
||||
.name = "ARConnect GFRC",
|
||||
.rating = 400,
|
||||
.read = arc_counter_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
|
||||
@@ -16,7 +16,7 @@
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
#include <asm/hardware/icst.h>
|
||||
|
||||
/*
|
||||
@@ -29,7 +29,11 @@ EXPORT_SYMBOL(icst525_s2div);
|
||||
|
||||
unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
|
||||
{
|
||||
return p->ref * 2 * (vco.v + 8) / ((vco.r + 2) * p->s2div[vco.s]);
|
||||
u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
|
||||
u32 divisor = (vco.r + 2) * p->s2div[vco.s];
|
||||
|
||||
do_div(dividend, divisor);
|
||||
return (unsigned long)dividend;
|
||||
}
|
||||
|
||||
EXPORT_SYMBOL(icst_hz);
|
||||
@@ -58,6 +62,7 @@ icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
|
||||
|
||||
if (f > p->vco_min && f <= p->vco_max)
|
||||
break;
|
||||
i++;
|
||||
} while (i < 8);
|
||||
|
||||
if (i >= 8)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user