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Merge tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull ARM SoC devicetree updates from Arnd Bergmann:
 "As usual, this is the bulk of the updates for the SoC tree, adding
  more devices to existing files, addressing issues from ever improving
  automated checking, and fixing minor issues.

  The most interesting bits as usual are the new platforms. All the
  newly supported SoCs belong into existing families this time:

   - Qualcomm gets support for two newly announced platforms, both of
     which can now work in production environments: the SDX65 5G modem
     that can run a minimal Linux on its Cortex-A7 core, and the
     Snapdragon 8 Gen 1, their latest high-end phone SoC.

   - Renesas adds support for R-Car S4-8, the most recent automotive
     Server/Communication SoC.

   - TI adds support for J721s2, a new automotive SoC in the K3 family.

   - Mediatek MT7986a/b is a SoC used in Wifi routers, the latest
     generation following their popular MT76xx series. Only basic
     support is added for now.

   - NXP i.MX8 ULP8 is a new low-power variant of the widespread i.MX8
     series.

   - TI SPEAr320s is a minor variant of the old SPEAr320 SoC that we
     have supported for a long time.

  New boards with the existing SoCs include

   - Aspeed AST2500/AST2600 BMCs in TYAN, Facebook and Yadro servers

   - AT91/SAMA5 based evaluation board

   - NXP gains twenty new development and industrial boards for their
     i.MX and Layerscape SoCs

   - Intel IXP4xx now supports the final two machines in device tree
     that were previously only supported in old style board files.

   - Mediatek MT6589 is used in the Fairphone FP1 phone from 2013, while
     MT8183 is used in the Acer Chromebook 314.

   - Qualcomm gains support for the reference machines using the two new
     SoCs, plus a number of Chromebook variants and phones based on the
     Snapdragon 7c, 845 and 888 SoCs, including various Sony Xperia
     devices and the Microsoft Surface Duo 2.

   - ST STM32 now supports the Engicam i.Core STM32MP1 carrier board.

   - Tegra now boots various older Android devices based on 32-bit chips
     out of the box, including a number of ASUS Transformer tablets.

     There is also a new Jetson AGX Orin developer kit.

   - Apple support adds the missing device trees for all the remaining
     M1 Macbook and iMac variants, though not yet the M1 Pro/Max
     versions.

   - Allwinner now supports another version of the Tanix TX6 set-top box
     based on the H6 SoC.

   - Broadcom gains support for the Netgear RAXE500 Wireless router
     based on BCM4908"

* tag 'dt-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (574 commits)
  Revert "ARM: dts: BCM5301X: define RTL8365MB switch on Asus RT-AC88U"
  arm64: dts: qcom: sm6125: Avoid using missing SM6125_VDDCX
  arm64: dts: qcom: sm8450-qrd: Enable USB nodes
  arm64: dts: qcom: sm8450: Add usb nodes
  ARM: dts: aspeed: add LCLK setting into LPC KCS nodes
  dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property
  ARM: dts: aspeed: add LCLK setting into LPC IBT node
  ARM: dts: aspeed: p10: Add TPM device
  ARM: dts: aspeed: p10: Enable USB host ports
  ARM: dts: aspeed: Add TYAN S8036 BMC machine
  ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config
  ARM: dts: aspeed: Adding Facebook Bletchley BMC
  ARM: dts: aspeed: g220a: Enable secondary flash
  ARM: dts: Add openbmc-flash-layout-64-alt.dtsi
  ARM: dts: aspeed: Add secure boot controller node
  dt-bindings: aspeed: Add Secure Boot Controller bindings
  ARM: dts: Remove "spidev" nodes
  dt-bindings: pinctrl: samsung: Add pin drive definitions for Exynos850
  dt-bindings: arm: samsung: Document E850-96 board binding
  dt-bindings: Add vendor prefix for WinLink
  ...
This commit is contained in:
Linus Torvalds
2022-01-10 08:24:40 -08:00
parent e85195d5bf 8b0c59c622
commit aca48b2dd1
555 changed files with 49040 additions and 8838 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
Documentation/devicetree/bindings/arm/apple.yaml
View File

@@ -12,12 +12,19 @@ maintainers:
description: |
ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
This currently includes devices based on the "M1" SoC, starting with the
three Mac models released in late 2020:
This currently includes devices based on the "M1" SoC:
- Mac mini (M1, 2020)
- MacBook Pro (13-inch, M1, 2020)
- MacBook Air (M1, 2020)
- iMac (24-inch, M1, 2021)
And devices based on the "M1 Pro" and "M1 Max" SoCs:
- MacBook Pro (14-inch, M1 Pro, 2021)
- MacBook Pro (14-inch, M1 Max, 2021)
- MacBook Pro (16-inch, M1 Pro, 2021)
- MacBook Pro (16-inch, M1 Max, 2021)
The compatible property should follow this format:
@@ -56,8 +63,24 @@ properties:
- apple,j274 # Mac mini (M1, 2020)
- apple,j293 # MacBook Pro (13-inch, M1, 2020)
- apple,j313 # MacBook Air (M1, 2020)
- apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021)
- apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
- const: apple,t8103
- const: apple,arm-platform
- description: Apple M1 Pro SoC based platforms
items:
- enum:
- apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021)
- apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
- const: apple,t6000
- const: apple,arm-platform
- description: Apple M1 Max SoC based platforms
items:
- enum:
- apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
- apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
- const: apple,t6001
- const: apple,arm-platform
additionalProperties: true

134
Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml Normal file
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@@ -0,0 +1,134 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple SoC Power Manager (PMGR)
maintainers:
- Hector Martin <marcan@marcan.st>
description: |
Apple SoCs include PMGR blocks responsible for power management,
which can control various clocks, resets, power states, and
performance features. This node represents the PMGR as a syscon,
with sub-nodes representing individual features.
properties:
$nodename:
pattern: "^power-management@[0-9a-f]+$"
compatible:
items:
- enum:
- apple,t8103-pmgr
- apple,t6000-pmgr
- const: apple,pmgr
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
patternProperties:
"power-controller@[0-9a-f]+$":
description:
The individual power management domains within this controller
type: object
$ref: /power/apple,pmgr-pwrstate.yaml#
required:
- compatible
- reg
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
power-management@23b700000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3b700000 0x0 0x14000>;
ps_sio: power-controller@1c0 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x1c0 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "sio";
apple,always-on;
};
ps_uart_p: power-controller@220 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x220 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "uart_p";
power-domains = <&ps_sio>;
};
ps_uart0: power-controller@270 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x270 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "uart0";
power-domains = <&ps_uart_p>;
};
};
power-management@23d280000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3d280000 0x0 0xc000>;
ps_aop_filter: power-controller@4000 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4000 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_filter";
};
ps_aop_base: power-controller@4010 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4010 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_base";
power-domains = <&ps_aop_filter>;
};
ps_aop_shim: power-controller@4038 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4038 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_shim";
power-domains = <&ps_aop_base>;
};
ps_aop_uart0: power-controller@4048 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4048 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_uart0";
power-domains = <&ps_aop_shim>;
};
};
};

37
Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml Normal file
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@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2021 Joel Stanley, IBM Corp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ASPEED Secure Boot Controller
maintainers:
- Joel Stanley <joel@jms.id.au>
- Andrew Jeffery <andrew@aj.id.au>
description: |
The ASPEED SoCs have a register bank for interacting with the secure boot
controller.
properties:
compatible:
items:
- const: aspeed,ast2600-sbc
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
sbc: secure-boot-controller@1e6f2000 {
compatible = "aspeed,ast2600-sbc";
reg = <0x1e6f2000 0x1000>;
};

1
Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
View File

@@ -29,6 +29,7 @@ properties:
items:
- enum:
- asus,gt-ac5300
- netgear,raxe500
- const: brcm,bcm4908
- description: BCM49408 based boards

78
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@@ -240,6 +240,7 @@ properties:
- uniwest,imx6q-evi # Uniwest Evi
- variscite,dt6customboard
- wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
- ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board
- zealz,imx6q-gk802 # Zealz GK802
- zii,imx6q-zii-rdu2 # ZII RDU2 Board
- const: fsl,imx6q
@@ -323,6 +324,20 @@ properties:
- const: toradex,apalis_imx6q
- const: fsl,imx6q
- description: TQ-Systems TQMa6Q SoM (variant A) on MBa6x
items:
- const: tq,imx6q-mba6x-a
- const: tq,mba6a # Expected by bootloader, to be removed in the future
- const: tq,imx6q-tqma6q-a
- const: fsl,imx6q
- description: TQ-Systems TQMa6Q SoM (variant B) on MBa6x
items:
- const: tq,imx6q-mba6x-b
- const: tq,mba6b # Expected by bootloader, to be removed in the future
- const: tq,imx6q-tqma6q-b
- const: fsl,imx6q
- description: i.MX6QP based Boards
items:
- enum:
@@ -334,6 +349,7 @@ properties:
- kvg,vicutp # Kverneland UT1P board
- prt,prtwd3 # Protonic WD3 board
- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
- ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board
- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
- const: fsl,imx6qp
@@ -344,6 +360,13 @@ properties:
- const: phytec,imx6qdl-pcm058 # PHYTEC phyCORE-i.MX6
- const: fsl,imx6qp
- description: TQ-Systems TQMa6QP SoM on MBa6x
items:
- const: tq,imx6qp-mba6x-b
- const: tq,mba6b # Expected by bootloader, to be removed in the future
- const: tq,imx6qp-tqma6qp-b
- const: fsl,imx6qp
- description: i.MX6DL based Boards
items:
- enum:
@@ -482,6 +505,20 @@ properties:
- const: dh,imx6s-dhcom-som
- const: fsl,imx6dl
- description: TQ-Systems TQMa6DL SoM (variant A) on MBa6x
items:
- const: tq,imx6dl-mba6x-a
- const: tq,mba6a # Expected by bootloader, to be removed in the future
- const: tq,imx6dl-tqma6dl-a
- const: fsl,imx6dl
- description: TQ-Systems TQMa6DL SoM (variant B) on MBa6x
items:
- const: tq,imx6dl-mba6x-b
- const: tq,mba6b # Expected by bootloader, to be removed in the future
- const: tq,imx6dl-tqma6dl-b
- const: fsl,imx6dl
- description: i.MX6SL based Boards
items:
- enum:
@@ -580,6 +617,7 @@ properties:
items:
- enum:
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- joz,jozacp # JOZ Access Point
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
- toradex,colibri-imx6ull # Colibri iMX6ULL Modules
@@ -632,6 +670,7 @@ properties:
- description: i.MX6ULZ based Boards
items:
- enum:
- bsh,imx6ulz-bsh-smm-m2 # i.MX6 ULZ BSH SystemMaster
- fsl,imx6ulz-14x14-evk # i.MX6 ULZ 14x14 EVK Board
- const: fsl,imx6ull # This seems odd. Should be last?
- const: fsl,imx6ulz
@@ -754,10 +793,23 @@ properties:
- const: variscite,var-som-mx8mm
- const: fsl,imx8mm
- description:
TQMa8MxML is a series of SOM featuring NXP i.MX8MM system-on-chip
variants. It is designed to be soldered on different carrier boards.
All variants (TQMa8M[Q,D,S][L]ML) use the same device tree, hence only
one compatible is needed.
items:
- enum:
- tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx
- const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM
- const: fsl,imx8mm
- description: i.MX8MN based Boards
items:
- enum:
- beacon,imx8mn-beacon-kit # i.MX8MN Beacon Development Kit
- bsh,imx8mn-bsh-smm-s2 # i.MX8MN BSH SystemMaster S2
- bsh,imx8mn-bsh-smm-s2pro # i.MX8MN BSH SystemMaster S2 PRO
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
@@ -769,6 +821,17 @@ properties:
- const: variscite,var-som-mx8mn
- const: fsl,imx8mn
- description:
TQMa8MxNL is a series of SOM featuring NXP i.MX8MN system-on-chip
variants. It is designed to be soldered on different carrier boards.
All variants (TQMa8M[Q,D,S][L]NL) use the same device tree, hence only
one compatible is needed.
items:
- enum:
- tq,imx8mn-tqma8mqnl-mba8mx # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM on MBa8Mx
- const: tq,imx8mn-tqma8mqnl # TQ-Systems GmbH i.MX8MN TQMa8MQNL SOM
- const: fsl,imx8mn
- description: i.MX8MP based Boards
items:
- enum:
@@ -805,6 +868,15 @@ properties:
- const: purism,librem5
- const: fsl,imx8mq
- description:
TQMa8Mx is a series of SOM featuring NXP i.MX8MQ system-on-chip
variants. It is designed to be clicked on different carrier boards.
items:
- enum:
- tq,imx8mq-tqma8mq-mba8mx # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM on MBa8Mx
- const: tq,imx8mq-tqma8mq # TQ-Systems GmbH i.MX8MQ TQMa8Mx SOM
- const: fsl,imx8mq
- description: Zodiac Inflight Innovations Ultra Boards
items:
- enum:
@@ -834,6 +906,12 @@ properties:
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
- description: i.MX8ULP based Boards
items:
- enum:
- fsl,imx8ulp-evk # i.MX8ULP EVK Board
- const: fsl,imx8ulp
- description:
Freescale Vybrid Platform Device Tree Bindings

20
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -77,6 +77,14 @@ properties:
- enum:
- mediatek,mt7629-rfb
- const: mediatek,mt7629
- items:
- enum:
- mediatek,mt7986a-rfb
- const: mediatek,mt7986a
- items:
- enum:
- mediatek,mt7986b-rfb
- const: mediatek,mt7986b
- items:
- enum:
- mediatek,mt8127-moose
@@ -134,6 +142,10 @@ properties:
- google,krane-sku176
- const: google,krane
- const: mediatek,mt8183
- description: Google Cozmo (Acer Chromebook 314)
items:
- const: google,cozmo
- const: mediatek,mt8183
- description: Google Damu (ASUS Chromebook Flip CM3)
items:
- const: google,damu
@@ -143,7 +155,9 @@ properties:
- enum:
- google,fennel-sku0
- google,fennel-sku1
- google,fennel-sku2
- google,fennel-sku6
- google,fennel-sku7
- const: google,fennel
- const: mediatek,mt8183
- description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
@@ -159,6 +173,12 @@ properties:
- const: google,kakadu-rev2
- const: google,kakadu
- const: mediatek,mt8183
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
items:
- const: google,kakadu-rev3-sku22
- const: google,kakadu-rev2-sku22
- const: google,kakadu
- const: mediatek,mt8183
- description: Google Kappa (HP Chromebook 11a)
items:
- const: google,kappa

8
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@@ -48,6 +48,7 @@ description: |
sdx65
sm7225
sm8150
sdx65
sm8250
sm8350
sm8450
@@ -202,8 +203,10 @@ properties:
- items:
- enum:
- qcom,sc7280-crd
- qcom,sc7280-idp
- qcom,sc7280-idp2
- google,hoglin
- google,piglin
- google,senor
- const: qcom,sc7280
@@ -225,6 +228,11 @@ properties:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,ipq6018-cp01

12
Documentation/devicetree/bindings/arm/renesas.yaml
View File

@@ -315,6 +315,18 @@ properties:
- const: renesas,falcon-cpu
- const: renesas,r8a779a0
- description: R-Car S4-8 (R8A779F0)
items:
- enum:
- renesas,spider-cpu # Spider CPU board (RTP8A779F0ASKB0SC2S)
- const: renesas,r8a779f0
- items:
- enum:
- renesas,spider-breakout # Spider BreakOut board (RTP8A779F0ASKB0SB0S)
- const: renesas,spider-cpu
- const: renesas,r8a779f0
- description: R-Car H3e (R8A779M0)
items:
- enum:

12
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
View File

@@ -199,6 +199,18 @@ properties:
- samsung,exynos7-espresso # Samsung Exynos7 Espresso
- const: samsung,exynos7
- description: Exynos7885 based boards
items:
- enum:
- samsung,jackpotlte # Samsung Galaxy A8 (2018)
- const: samsung,exynos7885
- description: Exynos850 based boards
items:
- enum:
- winlink,e850-96 # WinLink E850-96
- const: samsung,exynos850
- description: Exynos Auto v9 based boards
items:
- enum:

1
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@@ -77,6 +77,7 @@ properties:
items:
- enum:
- engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
- engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
- engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
- const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
- const: st,stm32mp157

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@@ -808,6 +808,11 @@ properties:
- const: oranth,tanix-tx6
- const: allwinner,sun50i-h6
- description: Tanix TX6 mini
items:
- const: oranth,tanix-tx6-mini
- const: allwinner,sun50i-h6
- description: TBS A711 Tablet
items:
- const: tbs-biometrics,a711

91
Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml
View File

@@ -32,12 +32,38 @@ properties:
- allwinner,sun8i-h3-mbus
- allwinner,sun8i-r40-mbus
- allwinner,sun50i-a64-mbus
- allwinner,sun50i-h5-mbus
reg:
maxItems: 1
minItems: 1
items:
- description: MBUS interconnect/bandwidth limit/PMU registers
- description: DRAM controller/PHY registers
reg-names:
minItems: 1
items:
- const: mbus
- const: dram
clocks:
minItems: 1
items:
- description: MBUS interconnect module clock
- description: DRAM controller/PHY module clock
- description: Register bus clock, shared by MBUS and DRAM
clock-names:
minItems: 1
items:
- const: mbus
- const: dram
- const: bus
interrupts:
maxItems: 1
description:
MBUS PMU activity interrupt.
dma-ranges:
description:
@@ -54,13 +80,55 @@ required:
- clocks
- dma-ranges
if:
properties:
compatible:
contains:
enum:
- allwinner,sun8i-h3-mbus
- allwinner,sun50i-a64-mbus
- allwinner,sun50i-h5-mbus
then:
properties:
reg:
minItems: 2
reg-names:
minItems: 2
clocks:
minItems: 3
clock-names:
minItems: 3
required:
- reg-names
- clock-names
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mbus: dram-controller@1c01000 {
dram-controller@1c01000 {
compatible = "allwinner,sun5i-a13-mbus";
reg = <0x01c01000 0x1000>;
clocks = <&ccu CLK_MBUS>;
@@ -70,4 +138,21 @@ examples:
#interconnect-cells = <1>;
};
- |
dram-controller@1c62000 {
compatible = "allwinner,sun50i-a64-mbus";
reg = <0x01c62000 0x1000>,
<0x01c63000 0x1000>;
reg-names = "mbus", "dram";
clocks = <&ccu CLK_MBUS>,
<&ccu CLK_DRAM>,
<&ccu CLK_BUS_DRAM>;
clock-names = "mbus", "dram", "bus";
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
#interconnect-cells = <1>;
};
...

48
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@@ -36,6 +36,9 @@ properties:
- toradex,colibri_t20-iris
- const: toradex,colibri_t20
- const: nvidia,tegra20
- items:
- const: asus,tf101
- const: nvidia,tegra20
- items:
- const: acer,picasso
- const: nvidia,tegra20
@@ -49,6 +52,18 @@ properties:
- nvidia,cardhu-a04
- const: nvidia,cardhu
- const: nvidia,tegra30
- items:
- const: asus,tf201
- const: nvidia,tegra30
- items:
- const: asus,tf300t
- const: nvidia,tegra30
- items:
- const: asus,tf300tg
- const: nvidia,tegra30
- items:
- const: asus,tf700t
- const: nvidia,tegra30
- items:
- const: toradex,apalis_t30-eval
- const: toradex,apalis_t30
@@ -74,8 +89,12 @@ properties:
- items:
- const: ouya,ouya
- const: nvidia,tegra30
- items:
- const: pegatron,chagall
- const: nvidia,tegra30
- items:
- enum:
- asus,tf701t
- nvidia,dalmore
- nvidia,roth
- nvidia,tn7
@@ -108,14 +127,17 @@ properties:
- nvidia,p2571
- nvidia,p2894-0050-a08
- const: nvidia,tegra210
- items:
- enum:
- nvidia,p2771-0000
- nvidia,p3509-0000+p3636-0001
- description: Jetson TX2 Developer Kit
items:
- const: nvidia,p2771-0000
- const: nvidia,tegra186
- items:
- enum:
- nvidia,p2972-0000
- description: Jetson TX2 NX Developer Kit
items:
- const: nvidia,p3509-0000+p3636-0001
- const: nvidia,tegra186
- description: Jetson AGX Xavier Developer Kit
items:
- const: nvidia,p2972-0000
- const: nvidia,tegra194
- description: Jetson Xavier NX
items:
@@ -134,8 +156,16 @@ properties:
- const: nvidia,p3509-0000+p3668-0001
- const: nvidia,tegra194
- items:
- enum:
- nvidia,tegra234-vdk
- const: nvidia,tegra234-vdk
- const: nvidia,tegra234
- description: Jetson AGX Orin
items:
- const: nvidia,p3701-0000
- const: nvidia,tegra234
- description: Jetson AGX Orin Developer Kit
items:
- const: nvidia,p3737-0000+p3701-0000
- const: nvidia,p3701-0000
- const: nvidia,tegra234
additionalProperties: true

133
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.txt
View File

@@ -1,133 +0,0 @@
NVIDIA Tegra Power Management Controller (PMC)
Required properties:
- compatible: Should contain one of the following:
- "nvidia,tegra186-pmc": for Tegra186
- "nvidia,tegra194-pmc": for Tegra194
- "nvidia,tegra234-pmc": for Tegra234
- reg: Must contain an (offset, length) pair of the register set for each
entry in reg-names.
- reg-names: Must include the following entries:
- "pmc"
- "wake"
- "aotag"
- "scratch"
- "misc" (Only for Tegra194 and later)
Optional properties:
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
- interrupt-controller: Identifies the node as an interrupt controller.
- #interrupt-cells: Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
Example:
SoC DTSI:
pmc@c3600000 {
compatible = "nvidia,tegra186-pmc";
reg = <0 0x0c360000 0 0x10000>,
<0 0x0c370000 0 0x10000>,
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
};
Board DTS:
pmc@c360000 {
nvidia,invert-interrupt;
};
== Pad Control ==
On Tegra SoCs a pad is a set of pins which are configured as a group.
The pin grouping is a fixed attribute of the hardware. The PMC can be
used to set pad power state and signaling voltage. A pad can be either
in active or power down mode. The support for power state and signaling
voltage configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.
Pad configurations are described with pin configuration nodes which
are placed under the pmc node and they are referred to by the pinctrl
client properties. For more information see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
The following pads are present on Tegra186:
csia csib dsi mipi-bias
pex-clk-bias pex-clk3 pex-clk2 pex-clk1
usb0 usb1 usb2 usb-bias
uart audio hsic dbg
hdmi-dp0 hdmi-dp1 pex-cntrl sdmmc2-hv
sdmmc4 cam dsib dsic
dsid csic csid csie
dsif spi ufs dmic-hv
edp sdmmc1-hv sdmmc3-hv conn
audio-hv ao-hv
Required pin configuration properties:
- pins: A list of strings, each of which contains the name of a pad
to be configured.
Optional pin configuration properties:
- low-power-enable: Configure the pad into power down mode
- low-power-disable: Configure the pad into active mode
- power-source: Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
Note: The power state can be configured on all of the above pads except
for ao-hv. Following pads have software configurable signaling
voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv, audio-hv,
ao-hv.
Pad configuration state example:
pmc: pmc@7000e400 {
compatible = "nvidia,tegra186-pmc";
reg = <0 0x0c360000 0 0x10000>,
<0 0x0c370000 0 0x10000>,
<0 0x0c380000 0 0x10000>,
<0 0x0c390000 0 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
...
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
hdmi_off: hdmi-off {
pins = "hdmi";
low-power-enable;
}
hdmi_on: hdmi-on {
pins = "hdmi";
low-power-disable;
}
};
Pinctrl client example:
sdmmc1: sdhci@3400000 {
...
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
};
...
sor0: sor@15540000 {
...
pinctrl-0 = <&hdmi_off>;
pinctrl-1 = <&hdmi_on>;
pinctrl-names = "hdmi-on", "hdmi-off";
};

198
Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml Normal file
View File

@@ -0,0 +1,198 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Power Management Controller (PMC)
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra186-pmc
- nvidia,tegra194-pmc
- nvidia,tegra234-pmc
reg:
minItems: 4
maxItems: 5
reg-names:
minItems: 4
items:
- const: pmc
- const: wake
- const: aotag
- const: scratch
- const: misc
interrupt-controller: true
"#interrupt-cells":
description: Specifies the number of cells needed to encode an
interrupt source. The value must be 2.
const: 2
nvidia,invert-interrupt:
description: If present, inverts the PMU interrupt signal.
$ref: /schemas/types.yaml#/definitions/flag
if:
properties:
compatible:
contains:
const: nvidia,tegra186-pmc
then:
properties:
reg:
maxItems: 4
reg-names:
maxItems: 4
else:
properties:
reg:
minItems: 5
reg-names:
minItems: 5
patternProperties:
"^[a-z0-9]+-[a-z0-9]+$":
if:
type: object
then:
description: |
These are pad configuration nodes. On Tegra SoCs a pad is a set of
pins which are configured as a group. The pin grouping is a fixed
attribute of the hardware. The PMC can be used to set pad power
state and signaling voltage. A pad can be either in active or
power down mode. The support for power state and signaling voltage
configuration varies depending on the pad in question. 3.3 V and
1.8 V signaling voltages are supported on pins where software
controllable signaling voltage switching is available.
Pad configurations are described with pin configuration nodes
which are placed under the pmc node and they are referred to by
the pinctrl client properties. For more information see
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
The following pads are present on Tegra186:
csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
The following pads are present on Tegra194:
csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
audio-hv, ao-hv
properties:
pins:
$ref: /schemas/types.yaml#/definitions/string
description: Must contain the name of the pad(s) to be
configured.
low-power-enable:
description: Configure the pad into power down mode.
$ref: /schemas/types.yaml#/definitions/flag
low-power-disable:
description: Configure the pad into active mode.
$ref: /schemas/types.yaml#/definitions/flag
power-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
voltages.
The values are defined in
include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
The power state can be configured on all of the above pads
except for ao-hv. Following pads have software configurable
signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
audio-hv, ao-hv.
phandle: true
required:
- pins
additionalProperties: false
required:
- compatible
- reg
- reg-names
additionalProperties: false
dependencies:
interrupt-controller: ['#interrupt-cells']
"#interrupt-cells":
required:
- interrupt-controller
examples:
- |
#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/memory/tegra186-mc.h>
#include <dt-bindings/reset/tegra186-reset.h>
pmc@c3600000 {
compatible = "nvidia,tegra186-pmc";
reg = <0x0c360000 0x10000>,
<0x0c370000 0x10000>,
<0x0c380000 0x10000>,
<0x0c390000 0x10000>;
reg-names = "pmc", "wake", "aotag", "scratch";
nvidia,invert-interrupt;
sdmmc1_3v3: sdmmc1-3v3 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
};
sdmmc1_1v8: sdmmc1-1v8 {
pins = "sdmmc1-hv";
power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
};
};
sdmmc1: mmc@3400000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x03400000 0x10000>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
<&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
clock-names = "sdhci", "tmclk";
resets = <&bpmp TEGRA186_RESET_SDMMC1>;
reset-names = "sdhci";
interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
iommus = <&smmu TEGRA186_SID_SDMMC1>;
pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
};

6
Documentation/devicetree/bindings/arm/ti/k3.yaml
View File

@@ -53,6 +53,12 @@ properties:
- ti,am642-sk
- const: ti,am642
- description: K3 J721s2 SoC
items:
- enum:
- ti,j721s2-evm
- const: ti,j721s2
additionalProperties: true
...

68
Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml Normal file
View File

@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/fsl,spba-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Shared Peripherals Bus Interface
maintainers:
- Shawn Guo <shawnguo@kernel.org>
description: |
A simple bus enabling access to shared peripherals.
The "spba-bus" follows the "simple-bus" set of properties, as
specified in the Devicetree Specification. It is an extension of
"simple-bus" because the SDMA controller uses this compatible flag to
determine which peripherals are available to it and the range over which
the SDMA can access. There are no special clocks for the bus, because
the SDMA controller itself has its interrupt and clock assignments.
select:
properties:
compatible:
contains:
const: fsl,spba-bus
required:
- compatible
properties:
$nodename:
pattern: "^spba-bus(@[0-9a-f]+)?$"
compatible:
items:
- const: fsl,spba-bus
- const: simple-bus
'#address-cells':
enum: [ 1, 2 ]
'#size-cells':
enum: [ 1, 2 ]
reg:
maxItems: 1
ranges: true
required:
- compatible
- '#address-cells'
- '#size-cells'
- reg
- ranges
additionalProperties:
type: object
examples:
- |
spba-bus@30000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x30000000 0x100000>;
ranges;
};

5
Documentation/devicetree/bindings/bus/imx-weim.txt
View File

@@ -48,6 +48,11 @@ Optional properties:
devices, the presence of this property indicates that
the weim bus should operate in Burst Clock Mode.
- fsl,continuous-burst-clk Make Burst Clock to output continuous clock.
Without this option Burst Clock will output clock
only when necessary. This takes effect only if
"fsl,burst-clk-enable" is set.
Timing property for child nodes. It is mandatory, not optional.
- fsl,weim-cs-timing: The timing array, contains timing values for the

37
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
View File

@@ -42,6 +42,36 @@ properties:
"#reset-cells":
const: 1
patternProperties:
"^(sclk)|(pll-[cem])$":
type: object
properties:
compatible:
enum:
- nvidia,tegra20-sclk
- nvidia,tegra30-sclk
- nvidia,tegra30-pllc
- nvidia,tegra30-plle
- nvidia,tegra30-pllm
operating-points-v2: true
clocks:
items:
- description: node's clock
power-domains:
maxItems: 1
description: phandle to the core SoC power domain
required:
- compatible
- operating-points-v2
- clocks
- power-domains
additionalProperties: false
required:
- compatible
- reg
@@ -59,6 +89,13 @@ examples:
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
sclk {
compatible = "nvidia,tegra20-sclk";
operating-points-v2 = <&opp_table>;
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
power-domains = <&domain>;
};
};
usb-controller@c5004000 {

80
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml Normal file
View File

@@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
maintainers:
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and
power domains on SDX65
See also:
- dt-bindings/clock/qcom,gcc-sdx65.h
properties:
compatible:
const: qcom,gcc-sdx65
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
- description: PLL test clock source (Optional clock)
minItems: 5
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
- const: pcie_pipe_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
- const: core_bi_pll_test_se # Optional clock
minItems: 5
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,gcc-sdx65";
reg = <0x100000 0x1f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

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