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clk: rockchip: rk3576: export pclk_hdptx_apb

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For edp and hdmi phy low power mode.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I288be0ffbf50a7ed78614d4813c5d4f8508d7405
This commit is contained in:
Elaine Zhang
2024-06-05 14:51:46 +08:00
committed by Tao Huang
parent 9eacb0f92f
commit a66d9bdbbe
2 changed files with 3 additions and 0 deletions
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2
drivers/clk/rockchip/clk-rk3576.c
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@@ -1594,6 +1594,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = {
RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS),
GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS),
GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0,
RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS),
GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0,
RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS),
GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0,

1
include/dt-bindings/clock/rockchip,rk3576-cru.h
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@@ -557,6 +557,7 @@
#define CLK_AUDIO_FRAC_1_SRC 555
#define CLK_AUDIO_FRAC_2_SRC 556
#define CLK_AUDIO_FRAC_3_SRC 557
#define PCLK_HDPTX_APB 558
/* secure clk */
#define CLK_STIMER0_ROOT 600