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pinctrl: rockchip: add rk3576 support

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Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ib5d22b9aeee559ad7bd7202b1586326f6f8cf8ab
This commit is contained in:
Steven Liu
2023-05-30 15:42:02 +08:00
committed by Tao Huang
parent d6510db1a1
commit 9f71509836
2 changed files with 231 additions and 0 deletions
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228
drivers/pinctrl/pinctrl-rockchip.c
View File

@@ -102,6 +102,27 @@
}, \
}
#define PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(id, pins, label, iom0, \
iom1, iom2, iom3, \
offset0, offset1, \
offset2, offset3, pull0, \
pull1, pull2, pull3) \
{ \
.bank_num = id, \
.nr_pins = pins, \
.name = label, \
.iomux = { \
{ .type = iom0, .offset = offset0 }, \
{ .type = iom1, .offset = offset1 }, \
{ .type = iom2, .offset = offset2 }, \
{ .type = iom3, .offset = offset3 }, \
}, \
.pull_type[0] = pull0, \
.pull_type[1] = pull1, \
.pull_type[2] = pull2, \
.pull_type[3] = pull3, \
}
#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
{ \
.bank_num = id, \
@@ -1134,6 +1155,11 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (ctrl->type == RK3576) {
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
}
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
@@ -1207,6 +1233,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
struct device *dev = info->dev;
int iomux_num = (pin / 8);
struct regmap *regmap;
struct regmap *regmap_sys;
int reg, ret, mask, mux_type;
u8 bit;
u32 data, rmask, route_location, route_reg, route_val;
@@ -1227,6 +1254,8 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
else
regmap = info->regmap_base;
regmap_sys = info->regmap_sys_grf;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
reg = bank->iomux[iomux_num].offset;
@@ -1261,6 +1290,20 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
}
}
if (ctrl->type == RK3576) {
if ((bank->bank_num == 0) && (pin >= RK_PB4) && (pin <= RK_PB7))
reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
/* i3c0 weakpull controlled by software */
if (((bank->bank_num == 0) && (pin == RK_PC5) && (mux == 0xb)) ||
((bank->bank_num == 1) && (pin == RK_PD1) && (mux == 0xa)))
regmap_update_bits(regmap_sys, 0x4, 0xc000c0, 0xc000c0);
/* i3c1 weakpull controlled by software */
if (((bank->bank_num == 2) && (pin == RK_PA5) && (mux == 0xe)) ||
((bank->bank_num == 2) && (pin == RK_PD6) && (mux == 0xc)) ||
((bank->bank_num == 3) && (pin == RK_PD1) && (mux == 0xb)))
regmap_update_bits(regmap_sys, 0x4, 0x3000300, 0x3000300);
}
if (ctrl->type == RK3588) {
if (bank->bank_num == 0) {
if ((pin >= RK_PB4) && (pin <= RK_PD7)) {
@@ -2698,6 +2741,142 @@ static int rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
#define RK3576_DRV_BITS_PER_PIN 4
#define RK3576_DRV_PINS_PER_REG 4
#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
#define RK3576_DRV_GPIO1_OFFSET 0x6020
#define RK3576_DRV_GPIO2_OFFSET 0x6040
#define RK3576_DRV_GPIO3_OFFSET 0x6060
#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
static int rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
if (bank->bank_num == 0 && pin_num < 12)
*reg = RK3576_DRV_GPIO0_AL_OFFSET;
else if (bank->bank_num == 0)
*reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
else if (bank->bank_num == 1)
*reg = RK3576_DRV_GPIO1_OFFSET;
else if (bank->bank_num == 2)
*reg = RK3576_DRV_GPIO2_OFFSET;
else if (bank->bank_num == 3)
*reg = RK3576_DRV_GPIO3_OFFSET;
else if (bank->bank_num == 4 && pin_num < 16)
*reg = RK3576_DRV_GPIO4_AL_OFFSET;
else if (bank->bank_num == 4 && pin_num < 24)
*reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
else if (bank->bank_num == 4)
*reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
else
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
*reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
*bit = pin_num % RK3576_DRV_PINS_PER_REG;
*bit *= RK3576_DRV_BITS_PER_PIN;
return 0;
}
#define RK3576_PULL_BITS_PER_PIN 2
#define RK3576_PULL_PINS_PER_REG 8
#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
#define RK3576_PULL_GPIO1_OFFSET 0x6110
#define RK3576_PULL_GPIO2_OFFSET 0x6120
#define RK3576_PULL_GPIO3_OFFSET 0x6130
#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
static int rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
if (bank->bank_num == 0 && pin_num < 12)
*reg = RK3576_PULL_GPIO0_AL_OFFSET;
else if (bank->bank_num == 0)
*reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
else if (bank->bank_num == 1)
*reg = RK3576_PULL_GPIO1_OFFSET;
else if (bank->bank_num == 2)
*reg = RK3576_PULL_GPIO2_OFFSET;
else if (bank->bank_num == 3)
*reg = RK3576_PULL_GPIO3_OFFSET;
else if (bank->bank_num == 4 && pin_num < 16)
*reg = RK3576_PULL_GPIO4_AL_OFFSET;
else if (bank->bank_num == 4 && pin_num < 24)
*reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
else if (bank->bank_num == 4)
*reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
else
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
*reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK3576_PULL_PINS_PER_REG;
*bit *= RK3576_PULL_BITS_PER_PIN;
return 0;
}
#define RK3576_SMT_BITS_PER_PIN 1
#define RK3576_SMT_PINS_PER_REG 8
#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
#define RK3576_SMT_GPIO1_OFFSET 0x6210
#define RK3576_SMT_GPIO2_OFFSET 0x6220
#define RK3576_SMT_GPIO3_OFFSET 0x6230
#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
if (bank->bank_num == 0 && pin_num < 12)
*reg = RK3576_SMT_GPIO0_AL_OFFSET;
else if (bank->bank_num == 0)
*reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
else if (bank->bank_num == 1)
*reg = RK3576_SMT_GPIO1_OFFSET;
else if (bank->bank_num == 2)
*reg = RK3576_SMT_GPIO2_OFFSET;
else if (bank->bank_num == 3)
*reg = RK3576_SMT_GPIO3_OFFSET;
else if (bank->bank_num == 4 && pin_num < 16)
*reg = RK3576_SMT_GPIO4_AL_OFFSET;
else if (bank->bank_num == 4 && pin_num < 24)
*reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
else if (bank->bank_num == 4)
*reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
else
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
*reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
*bit = pin_num % RK3576_SMT_PINS_PER_REG;
*bit *= RK3576_SMT_BITS_PER_PIN;
return 0;
}
#define RK3588_PMU1_IOC_REG (0x0000)
#define RK3588_PMU2_IOC_REG (0x4000)
#define RK3588_BUS_IOC_REG (0x8000)
@@ -3020,6 +3199,10 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
rmask_bits = RK3568_DRV_BITS_PER_PIN;
ret = (1 << (strength + 1)) - 1;
goto config;
} else if (ctrl->type == RK3576) {
rmask_bits = RK3576_DRV_BITS_PER_PIN;
ret = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
goto config;
}
ret = -EINVAL;
@@ -3191,6 +3374,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
case RK3528:
case RK3562:
case RK3568:
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
data >>= bit;
@@ -3253,6 +3437,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
case RK3528:
case RK3562:
case RK3568:
case RK3576:
case RK3588:
pull_type = bank->pull_type[pin_num / 8];
ret = -EINVAL;
@@ -3604,6 +3789,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
case RK3528:
case RK3562:
case RK3568:
case RK3576:
case RK3588:
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
}
@@ -4318,6 +4504,15 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
}
}
/* try to find the optional reference to the sys_grf syscon */
node = of_parse_phandle(np, "rockchip,sys-grf", 0);
if (node) {
info->regmap_sys_grf = syscon_node_to_regmap(node);
of_node_put(node);
if (IS_ERR(info->regmap_sys_grf))
return PTR_ERR(info->regmap_sys_grf);
}
/* try to find the optional reference to the pmu syscon */
node = of_parse_phandle(np, "rockchip,pmu", 0);
if (node) {
@@ -5024,6 +5219,35 @@ static struct rockchip_pin_ctrl rk3568_pin_ctrl __maybe_unused = {
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
};
#define RK3576_PIN_BANK(ID, LABEL, OFFSET0, OFFSET1, OFFSET2, OFFSET3) \
PIN_BANK_IOMUX_FLAGS_OFFSET_PULL_FLAGS(ID, 32, LABEL, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
IOMUX_WIDTH_4BIT, \
OFFSET0, OFFSET1, \
OFFSET2, OFFSET3, \
PULL_TYPE_IO_1, PULL_TYPE_IO_1, \
PULL_TYPE_IO_1, PULL_TYPE_IO_1)
static struct rockchip_pin_bank rk3576_pin_banks[] = {
RK3576_PIN_BANK(0, "gpio0", 0, 0x8, 0x2004, 0x200C),
RK3576_PIN_BANK(1, "gpio1", 0x4020, 0x4028, 0x4030, 0x4038),
RK3576_PIN_BANK(2, "gpio2", 0x4040, 0x4048, 0x4050, 0x4058),
RK3576_PIN_BANK(3, "gpio3", 0x4060, 0x4068, 0x4070, 0x4078),
RK3576_PIN_BANK(4, "gpio4", 0x4080, 0x4088, 0xA390, 0xB398),
};
static struct rockchip_pin_ctrl rk3576_pin_ctrl __maybe_unused = {
.pin_banks = rk3576_pin_banks,
.nr_banks = ARRAY_SIZE(rk3576_pin_banks),
.label = "RK3576-GPIO",
.type = RK3576,
.pull_calc_reg = rk3576_calc_pull_reg_and_bit,
.drv_calc_reg = rk3576_calc_drv_reg_and_bit,
.schmitt_calc_reg = rk3576_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk3588_pin_banks[] = {
RK3588_PIN_BANK_FLAGS(0, 32, "gpio0",
IOMUX_WIDTH_4BIT, PULL_TYPE_IO_1V8_ONLY),
@@ -5126,6 +5350,10 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
{ .compatible = "rockchip,rk3568-pinctrl",
.data = &rk3568_pin_ctrl },
#endif
#ifdef CONFIG_CPU_RK3576
{ .compatible = "rockchip,rk3576-pinctrl",
.data = &rk3576_pin_ctrl },
#endif
#ifdef CONFIG_CPU_RK3588
{ .compatible = "rockchip,rk3588-pinctrl",
.data = &rk3588_pin_ctrl },

3
drivers/pinctrl/pinctrl-rockchip.h
View File

@@ -200,6 +200,7 @@ enum rockchip_pinctrl_type {
RK3528,
RK3562,
RK3568,
RK3576,
RK3588,
};
@@ -270,6 +271,7 @@ enum rockchip_pin_drv_type {
enum rockchip_pin_pull_type {
PULL_TYPE_IO_DEFAULT = 0,
PULL_TYPE_IO_1V8_ONLY,
PULL_TYPE_IO_1 = 1,
PULL_TYPE_MAX
};
@@ -462,6 +464,7 @@ struct rockchip_pinctrl {
int reg_size;
struct regmap *regmap_pull;
struct regmap *regmap_pmu;
struct regmap *regmap_sys_grf;
struct device *dev;
struct rockchip_pin_ctrl *ctrl;
struct pinctrl_desc pctl;