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arm64: dts: rockchip: rk3576: Enable high speed interfaces use DMA coherent

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The GMAC0/1 and MMU0/1(PCIe, SATA, USB OTG1) support CCI
(Cache Coherent Interconnect), Mark them as such.

Hardware feature for CCI were enabled at U-Boot miniloader level.

Note that MMU2 for USB OTG0 doesn't support CCI.

Change-Id: Ie632fc2ad987c3972076f65559c043b3da67d858
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
This commit is contained in:
David Wu
2024-04-19 15:10:41 +08:00
committed by Tao Huang
parent 15f661b3f5
commit 5a1ef132de
1 changed files with 7 additions and 0 deletions
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7
arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -1474,6 +1474,7 @@
snps,dis_rxdet_inp3_quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
dma-coherent;
status = "disabled";
};
@@ -3587,6 +3588,7 @@
reg-names = "pcie-apb", "pcie-dbi", "config";
resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
reset-names = "pipe", "p_pcie0";
dma-coherent;
status = "disabled";
pcie0_intc: legacy-interrupt-controller {
@@ -3642,6 +3644,7 @@
reg-names = "pcie-apb", "pcie-dbi", "config";
resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
reset-names = "pipe", "p_pcie1";
dma-coherent;
status = "disabled";
pcie1_intc: legacy-interrupt-controller {
@@ -3671,6 +3674,7 @@
reset-names = "stmmaceth";
power-domains = <&power RK3576_PD_SDGMAC>;
dma-coherent;
snps,mixed-burst;
snps,tso;
@@ -3720,6 +3724,7 @@
reset-names = "stmmaceth";
power-domains = <&power RK3576_PD_SDGMAC>;
dma-coherent;
snps,mixed-burst;
snps,tso;
@@ -3763,6 +3768,7 @@
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};
@@ -3778,6 +3784,7 @@
phys = <&combphy1_psu PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
dma-coherent;
status = "disabled";
};