armbian/linux-rockchip
0
0
Fork 0
mirror of https://github.com/armbian/linux-rockchip.git synced 2026-01-06 11:08:10 -08:00
Code Issues Packages Projects Releases Wiki Activity

perf/dwc_pcie: Fix lane event support for Rockchip

Browse Source 
Lane event counter usage in Rockchip is slightly different with
T-Head. Fix it by checking vendor ID.

Fixes: 6cb6a00862 ("perf/dwc_pcie: Add support for Rockchip vendor devices")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iccc25bb7b352f73bae963d827f14b2f7405608b2
This commit is contained in:
Shawn Lin
2024-09-30 17:29:57 +08:00
committed by Tao Huang
parent 149b66f314
commit 4e89810905
1 changed files with 23 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
drivers/perf/dwc_pcie_pmu.c
View File

@@ -256,12 +256,31 @@ static const struct attribute_group *dwc_pcie_attr_groups[] = {
NULL
};
static void dwc_pcie_pmu_lane_event_enable_for_rk(struct pci_dev *pdev,
u16 ras_des_offset,
bool enable)
{
if (enable) {
pci_write_config_dword(pdev,
ras_des_offset + DWC_PCIE_EVENT_CNT_CTL, 0x1c);
pci_write_config_dword(pdev,
ras_des_offset + DWC_PCIE_EVENT_CNT_CTL, 0x3);
} else {
pci_write_config_dword(pdev,
ras_des_offset + DWC_PCIE_EVENT_CNT_CTL, 0x14);
}
}
static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu,
bool enable)
{
struct pci_dev *pdev = pcie_pmu->pdev;
u16 ras_des_offset = pcie_pmu->ras_des_offset;
if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
return dwc_pcie_pmu_lane_event_enable_for_rk(pdev, ras_des_offset,
enable);
if (enable)
pci_clear_and_set_config_dword(pdev,
ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
@@ -287,9 +306,13 @@ static u64 dwc_pcie_pmu_read_lane_event_counter(struct perf_event *event)
{
struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu);
struct pci_dev *pdev = pcie_pmu->pdev;
int event_id = DWC_PCIE_EVENT_ID(event);
u16 ras_des_offset = pcie_pmu->ras_des_offset;
u32 val;
if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
event_id << 16);
pci_read_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_DATA, &val);
return val;